xref: /openbmc/linux/drivers/infiniband/hw/hfi1/mad.h (revision bf90aadd630c2c9f7f965ba1e90d41b5b46db7c9)
1f48ad614SDennis Dalessandro /*
2*bf90aaddSMichael J. Ruhl  * Copyright(c) 2015 - 2017 Intel Corporation.
3f48ad614SDennis Dalessandro  *
4f48ad614SDennis Dalessandro  * This file is provided under a dual BSD/GPLv2 license.  When using or
5f48ad614SDennis Dalessandro  * redistributing this file, you may do so under either license.
6f48ad614SDennis Dalessandro  *
7f48ad614SDennis Dalessandro  * GPL LICENSE SUMMARY
8f48ad614SDennis Dalessandro  *
9f48ad614SDennis Dalessandro  * This program is free software; you can redistribute it and/or modify
10f48ad614SDennis Dalessandro  * it under the terms of version 2 of the GNU General Public License as
11f48ad614SDennis Dalessandro  * published by the Free Software Foundation.
12f48ad614SDennis Dalessandro  *
13f48ad614SDennis Dalessandro  * This program is distributed in the hope that it will be useful, but
14f48ad614SDennis Dalessandro  * WITHOUT ANY WARRANTY; without even the implied warranty of
15f48ad614SDennis Dalessandro  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16f48ad614SDennis Dalessandro  * General Public License for more details.
17f48ad614SDennis Dalessandro  *
18f48ad614SDennis Dalessandro  * BSD LICENSE
19f48ad614SDennis Dalessandro  *
20f48ad614SDennis Dalessandro  * Redistribution and use in source and binary forms, with or without
21f48ad614SDennis Dalessandro  * modification, are permitted provided that the following conditions
22f48ad614SDennis Dalessandro  * are met:
23f48ad614SDennis Dalessandro  *
24f48ad614SDennis Dalessandro  *  - Redistributions of source code must retain the above copyright
25f48ad614SDennis Dalessandro  *    notice, this list of conditions and the following disclaimer.
26f48ad614SDennis Dalessandro  *  - Redistributions in binary form must reproduce the above copyright
27f48ad614SDennis Dalessandro  *    notice, this list of conditions and the following disclaimer in
28f48ad614SDennis Dalessandro  *    the documentation and/or other materials provided with the
29f48ad614SDennis Dalessandro  *    distribution.
30f48ad614SDennis Dalessandro  *  - Neither the name of Intel Corporation nor the names of its
31f48ad614SDennis Dalessandro  *    contributors may be used to endorse or promote products derived
32f48ad614SDennis Dalessandro  *    from this software without specific prior written permission.
33f48ad614SDennis Dalessandro  *
34f48ad614SDennis Dalessandro  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35f48ad614SDennis Dalessandro  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36f48ad614SDennis Dalessandro  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37f48ad614SDennis Dalessandro  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38f48ad614SDennis Dalessandro  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39f48ad614SDennis Dalessandro  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40f48ad614SDennis Dalessandro  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41f48ad614SDennis Dalessandro  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42f48ad614SDennis Dalessandro  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43f48ad614SDennis Dalessandro  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44f48ad614SDennis Dalessandro  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45f48ad614SDennis Dalessandro  *
46f48ad614SDennis Dalessandro  */
47f48ad614SDennis Dalessandro #ifndef _HFI1_MAD_H
48f48ad614SDennis Dalessandro #define _HFI1_MAD_H
49f48ad614SDennis Dalessandro 
50f48ad614SDennis Dalessandro #include <rdma/ib_pma.h>
51f48ad614SDennis Dalessandro #include <rdma/opa_smi.h>
52f48ad614SDennis Dalessandro #include <rdma/opa_port_info.h>
53f48ad614SDennis Dalessandro #include "opa_compat.h"
54f48ad614SDennis Dalessandro 
55f48ad614SDennis Dalessandro /*
56f48ad614SDennis Dalessandro  * OPA Traps
57f48ad614SDennis Dalessandro  */
58f48ad614SDennis Dalessandro #define OPA_TRAP_GID_NOW_IN_SERVICE             cpu_to_be16(64)
59f48ad614SDennis Dalessandro #define OPA_TRAP_GID_OUT_OF_SERVICE             cpu_to_be16(65)
60f48ad614SDennis Dalessandro #define OPA_TRAP_ADD_MULTICAST_GROUP            cpu_to_be16(66)
61f48ad614SDennis Dalessandro #define OPA_TRAL_DEL_MULTICAST_GROUP            cpu_to_be16(67)
62f48ad614SDennis Dalessandro #define OPA_TRAP_UNPATH                         cpu_to_be16(68)
63f48ad614SDennis Dalessandro #define OPA_TRAP_REPATH                         cpu_to_be16(69)
64f48ad614SDennis Dalessandro #define OPA_TRAP_PORT_CHANGE_STATE              cpu_to_be16(128)
65f48ad614SDennis Dalessandro #define OPA_TRAP_LINK_INTEGRITY                 cpu_to_be16(129)
66f48ad614SDennis Dalessandro #define OPA_TRAP_EXCESSIVE_BUFFER_OVERRUN       cpu_to_be16(130)
67f48ad614SDennis Dalessandro #define OPA_TRAP_FLOW_WATCHDOG                  cpu_to_be16(131)
68f48ad614SDennis Dalessandro #define OPA_TRAP_CHANGE_CAPABILITY              cpu_to_be16(144)
69f48ad614SDennis Dalessandro #define OPA_TRAP_CHANGE_SYSGUID                 cpu_to_be16(145)
70f48ad614SDennis Dalessandro #define OPA_TRAP_BAD_M_KEY                      cpu_to_be16(256)
71f48ad614SDennis Dalessandro #define OPA_TRAP_BAD_P_KEY                      cpu_to_be16(257)
72f48ad614SDennis Dalessandro #define OPA_TRAP_BAD_Q_KEY                      cpu_to_be16(258)
73f48ad614SDennis Dalessandro #define OPA_TRAP_SWITCH_BAD_PKEY                cpu_to_be16(259)
74f48ad614SDennis Dalessandro #define OPA_SMA_TRAP_DATA_LINK_WIDTH            cpu_to_be16(2048)
75f48ad614SDennis Dalessandro 
76f48ad614SDennis Dalessandro /*
77f48ad614SDennis Dalessandro  * Generic trap/notice other local changes flags (trap 144).
78f48ad614SDennis Dalessandro  */
79f48ad614SDennis Dalessandro #define	OPA_NOTICE_TRAP_LWDE_CHG        0x08 /* Link Width Downgrade Enable
80f48ad614SDennis Dalessandro 					      * changed
81f48ad614SDennis Dalessandro 					      */
82f48ad614SDennis Dalessandro #define OPA_NOTICE_TRAP_LSE_CHG         0x04 /* Link Speed Enable changed */
83f48ad614SDennis Dalessandro #define OPA_NOTICE_TRAP_LWE_CHG         0x02 /* Link Width Enable changed */
84f48ad614SDennis Dalessandro #define OPA_NOTICE_TRAP_NODE_DESC_CHG   0x01
85f48ad614SDennis Dalessandro 
86f48ad614SDennis Dalessandro struct opa_mad_notice_attr {
87f48ad614SDennis Dalessandro 	u8 generic_type;
88f48ad614SDennis Dalessandro 	u8 prod_type_msb;
89f48ad614SDennis Dalessandro 	__be16 prod_type_lsb;
90f48ad614SDennis Dalessandro 	__be16 trap_num;
91f48ad614SDennis Dalessandro 	__be16 toggle_count;
92f48ad614SDennis Dalessandro 	__be32 issuer_lid;
93f48ad614SDennis Dalessandro 	__be32 reserved1;
94f48ad614SDennis Dalessandro 	union ib_gid issuer_gid;
95f48ad614SDennis Dalessandro 
96f48ad614SDennis Dalessandro 	union {
97f48ad614SDennis Dalessandro 		struct {
98f48ad614SDennis Dalessandro 			u8	details[64];
99f48ad614SDennis Dalessandro 		} raw_data;
100f48ad614SDennis Dalessandro 
101f48ad614SDennis Dalessandro 		struct {
102f48ad614SDennis Dalessandro 			union ib_gid	gid;
103f48ad614SDennis Dalessandro 		} __packed ntc_64_65_66_67;
104f48ad614SDennis Dalessandro 
105f48ad614SDennis Dalessandro 		struct {
106f48ad614SDennis Dalessandro 			__be32	lid;
107f48ad614SDennis Dalessandro 		} __packed ntc_128;
108f48ad614SDennis Dalessandro 
109f48ad614SDennis Dalessandro 		struct {
110f48ad614SDennis Dalessandro 			__be32	lid;		/* where violation happened */
111f48ad614SDennis Dalessandro 			u8	port_num;	/* where violation happened */
112f48ad614SDennis Dalessandro 		} __packed ntc_129_130_131;
113f48ad614SDennis Dalessandro 
114f48ad614SDennis Dalessandro 		struct {
115f48ad614SDennis Dalessandro 			__be32	lid;		/* LID where change occurred */
116f48ad614SDennis Dalessandro 			__be32	new_cap_mask;	/* new capability mask */
117f48ad614SDennis Dalessandro 			__be16	reserved2;
118cb49366fSVishwanathapura, Niranjana 			__be16	cap_mask3;
119f48ad614SDennis Dalessandro 			__be16	change_flags;	/* low 4 bits only */
120f48ad614SDennis Dalessandro 		} __packed ntc_144;
121f48ad614SDennis Dalessandro 
122f48ad614SDennis Dalessandro 		struct {
123f48ad614SDennis Dalessandro 			__be64	new_sys_guid;
124f48ad614SDennis Dalessandro 			__be32	lid;		/* lid where sys guid changed */
125f48ad614SDennis Dalessandro 		} __packed ntc_145;
126f48ad614SDennis Dalessandro 
127f48ad614SDennis Dalessandro 		struct {
128f48ad614SDennis Dalessandro 			__be32	lid;
129f48ad614SDennis Dalessandro 			__be32	dr_slid;
130f48ad614SDennis Dalessandro 			u8	method;
131f48ad614SDennis Dalessandro 			u8	dr_trunc_hop;
132f48ad614SDennis Dalessandro 			__be16	attr_id;
133f48ad614SDennis Dalessandro 			__be32	attr_mod;
134f48ad614SDennis Dalessandro 			__be64	mkey;
135f48ad614SDennis Dalessandro 			u8	dr_rtn_path[30];
136f48ad614SDennis Dalessandro 		} __packed ntc_256;
137f48ad614SDennis Dalessandro 
138f48ad614SDennis Dalessandro 		struct {
139f48ad614SDennis Dalessandro 			__be32		lid1;
140f48ad614SDennis Dalessandro 			__be32		lid2;
141f48ad614SDennis Dalessandro 			__be32		key;
142f48ad614SDennis Dalessandro 			u8		sl;	/* SL: high 5 bits */
143f48ad614SDennis Dalessandro 			u8		reserved3[3];
144f48ad614SDennis Dalessandro 			union ib_gid	gid1;
145f48ad614SDennis Dalessandro 			union ib_gid	gid2;
146f48ad614SDennis Dalessandro 			__be32		qp1;	/* high 8 bits reserved */
147f48ad614SDennis Dalessandro 			__be32		qp2;	/* high 8 bits reserved */
148f48ad614SDennis Dalessandro 		} __packed ntc_257_258;
149f48ad614SDennis Dalessandro 
150f48ad614SDennis Dalessandro 		struct {
151f48ad614SDennis Dalessandro 			__be16		flags;	/* low 8 bits reserved */
152f48ad614SDennis Dalessandro 			__be16		pkey;
153f48ad614SDennis Dalessandro 			__be32		lid1;
154f48ad614SDennis Dalessandro 			__be32		lid2;
155f48ad614SDennis Dalessandro 			u8		sl;	/* SL: high 5 bits */
156f48ad614SDennis Dalessandro 			u8		reserved4[3];
157f48ad614SDennis Dalessandro 			union ib_gid	gid1;
158f48ad614SDennis Dalessandro 			union ib_gid	gid2;
159f48ad614SDennis Dalessandro 			__be32		qp1;	/* high 8 bits reserved */
160f48ad614SDennis Dalessandro 			__be32		qp2;	/* high 8 bits reserved */
161f48ad614SDennis Dalessandro 		} __packed ntc_259;
162f48ad614SDennis Dalessandro 
163f48ad614SDennis Dalessandro 		struct {
164f48ad614SDennis Dalessandro 			__be32	lid;
165f48ad614SDennis Dalessandro 		} __packed ntc_2048;
166f48ad614SDennis Dalessandro 
167f48ad614SDennis Dalessandro 	};
168f48ad614SDennis Dalessandro 	u8	class_data[0];
169f48ad614SDennis Dalessandro };
170f48ad614SDennis Dalessandro 
171f48ad614SDennis Dalessandro #define IB_VLARB_LOWPRI_0_31    1
172f48ad614SDennis Dalessandro #define IB_VLARB_LOWPRI_32_63   2
173f48ad614SDennis Dalessandro #define IB_VLARB_HIGHPRI_0_31   3
174f48ad614SDennis Dalessandro #define IB_VLARB_HIGHPRI_32_63  4
175f48ad614SDennis Dalessandro 
176f48ad614SDennis Dalessandro #define OPA_MAX_PREEMPT_CAP         32
177f48ad614SDennis Dalessandro #define OPA_VLARB_LOW_ELEMENTS       0
178f48ad614SDennis Dalessandro #define OPA_VLARB_HIGH_ELEMENTS      1
179f48ad614SDennis Dalessandro #define OPA_VLARB_PREEMPT_ELEMENTS   2
180f48ad614SDennis Dalessandro #define OPA_VLARB_PREEMPT_MATRIX     3
181f48ad614SDennis Dalessandro 
182f48ad614SDennis Dalessandro #define IB_PMA_PORT_COUNTERS_CONG       cpu_to_be16(0xFF00)
183f48ad614SDennis Dalessandro 
184f48ad614SDennis Dalessandro struct ib_pma_portcounters_cong {
185f48ad614SDennis Dalessandro 	u8 reserved;
186f48ad614SDennis Dalessandro 	u8 reserved1;
187f48ad614SDennis Dalessandro 	__be16 port_check_rate;
188f48ad614SDennis Dalessandro 	__be16 symbol_error_counter;
189f48ad614SDennis Dalessandro 	u8 link_error_recovery_counter;
190f48ad614SDennis Dalessandro 	u8 link_downed_counter;
191f48ad614SDennis Dalessandro 	__be16 port_rcv_errors;
192f48ad614SDennis Dalessandro 	__be16 port_rcv_remphys_errors;
193f48ad614SDennis Dalessandro 	__be16 port_rcv_switch_relay_errors;
194f48ad614SDennis Dalessandro 	__be16 port_xmit_discards;
195f48ad614SDennis Dalessandro 	u8 port_xmit_constraint_errors;
196f48ad614SDennis Dalessandro 	u8 port_rcv_constraint_errors;
197f48ad614SDennis Dalessandro 	u8 reserved2;
198f48ad614SDennis Dalessandro 	u8 link_overrun_errors; /* LocalLink: 7:4, BufferOverrun: 3:0 */
199f48ad614SDennis Dalessandro 	__be16 reserved3;
200f48ad614SDennis Dalessandro 	__be16 vl15_dropped;
201f48ad614SDennis Dalessandro 	__be64 port_xmit_data;
202f48ad614SDennis Dalessandro 	__be64 port_rcv_data;
203f48ad614SDennis Dalessandro 	__be64 port_xmit_packets;
204f48ad614SDennis Dalessandro 	__be64 port_rcv_packets;
205f48ad614SDennis Dalessandro 	__be64 port_xmit_wait;
206f48ad614SDennis Dalessandro 	__be64 port_adr_events;
207f48ad614SDennis Dalessandro } __packed;
208f48ad614SDennis Dalessandro 
209f48ad614SDennis Dalessandro #define IB_SMP_UNSUP_VERSION    cpu_to_be16(0x0004)
210f48ad614SDennis Dalessandro #define IB_SMP_UNSUP_METHOD     cpu_to_be16(0x0008)
211f48ad614SDennis Dalessandro #define IB_SMP_UNSUP_METH_ATTR  cpu_to_be16(0x000C)
212f48ad614SDennis Dalessandro #define IB_SMP_INVALID_FIELD    cpu_to_be16(0x001C)
213f48ad614SDennis Dalessandro 
214f48ad614SDennis Dalessandro #define OPA_MAX_PREEMPT_CAP         32
215f48ad614SDennis Dalessandro #define OPA_VLARB_LOW_ELEMENTS       0
216f48ad614SDennis Dalessandro #define OPA_VLARB_HIGH_ELEMENTS      1
217f48ad614SDennis Dalessandro #define OPA_VLARB_PREEMPT_ELEMENTS   2
218f48ad614SDennis Dalessandro #define OPA_VLARB_PREEMPT_MATRIX     3
219f48ad614SDennis Dalessandro 
220f48ad614SDennis Dalessandro #define HFI1_XMIT_RATE_UNSUPPORTED               0x0
221f48ad614SDennis Dalessandro #define HFI1_XMIT_RATE_PICO                      0x7
222f48ad614SDennis Dalessandro /* number of 4nsec cycles equaling 2secs */
223f48ad614SDennis Dalessandro #define HFI1_CONG_TIMER_PSINTERVAL               0x1DCD64EC
224f48ad614SDennis Dalessandro 
225f48ad614SDennis Dalessandro #define IB_CC_SVCTYPE_RC 0x0
226f48ad614SDennis Dalessandro #define IB_CC_SVCTYPE_UC 0x1
227f48ad614SDennis Dalessandro #define IB_CC_SVCTYPE_RD 0x2
228f48ad614SDennis Dalessandro #define IB_CC_SVCTYPE_UD 0x3
229f48ad614SDennis Dalessandro 
230f48ad614SDennis Dalessandro /*
231f48ad614SDennis Dalessandro  * There should be an equivalent IB #define for the following, but
232f48ad614SDennis Dalessandro  * I cannot find it.
233f48ad614SDennis Dalessandro  */
234f48ad614SDennis Dalessandro #define OPA_CC_LOG_TYPE_HFI	2
235f48ad614SDennis Dalessandro 
236f48ad614SDennis Dalessandro struct opa_hfi1_cong_log_event_internal {
237f48ad614SDennis Dalessandro 	u32 lqpn;
238f48ad614SDennis Dalessandro 	u32 rqpn;
239f48ad614SDennis Dalessandro 	u8 sl;
240f48ad614SDennis Dalessandro 	u8 svc_type;
241f48ad614SDennis Dalessandro 	u32 rlid;
242f48ad614SDennis Dalessandro 	s64 timestamp; /* wider than 32 bits to detect 32 bit rollover */
243f48ad614SDennis Dalessandro };
244f48ad614SDennis Dalessandro 
245f48ad614SDennis Dalessandro struct opa_hfi1_cong_log_event {
246f48ad614SDennis Dalessandro 	u8 local_qp_cn_entry[3];
247f48ad614SDennis Dalessandro 	u8 remote_qp_number_cn_entry[3];
248f48ad614SDennis Dalessandro 	u8 sl_svc_type_cn_entry; /* 5 bits SL, 3 bits svc type */
249f48ad614SDennis Dalessandro 	u8 reserved;
250f48ad614SDennis Dalessandro 	__be32 remote_lid_cn_entry;
251f48ad614SDennis Dalessandro 	__be32 timestamp_cn_entry;
252f48ad614SDennis Dalessandro } __packed;
253f48ad614SDennis Dalessandro 
254f48ad614SDennis Dalessandro #define OPA_CONG_LOG_ELEMS	96
255f48ad614SDennis Dalessandro 
256f48ad614SDennis Dalessandro struct opa_hfi1_cong_log {
257f48ad614SDennis Dalessandro 	u8 log_type;
258f48ad614SDennis Dalessandro 	u8 congestion_flags;
259f48ad614SDennis Dalessandro 	__be16 threshold_event_counter;
260f48ad614SDennis Dalessandro 	__be32 current_time_stamp;
261f48ad614SDennis Dalessandro 	u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
262f48ad614SDennis Dalessandro 	struct opa_hfi1_cong_log_event events[OPA_CONG_LOG_ELEMS];
263f48ad614SDennis Dalessandro } __packed;
264f48ad614SDennis Dalessandro 
265f48ad614SDennis Dalessandro #define IB_CC_TABLE_CAP_DEFAULT 31
266f48ad614SDennis Dalessandro 
267f48ad614SDennis Dalessandro /* Port control flags */
268f48ad614SDennis Dalessandro #define IB_CC_CCS_PC_SL_BASED 0x01
269f48ad614SDennis Dalessandro 
270f48ad614SDennis Dalessandro struct opa_congestion_setting_entry {
271f48ad614SDennis Dalessandro 	u8 ccti_increase;
272f48ad614SDennis Dalessandro 	u8 reserved;
273f48ad614SDennis Dalessandro 	__be16 ccti_timer;
274f48ad614SDennis Dalessandro 	u8 trigger_threshold;
275f48ad614SDennis Dalessandro 	u8 ccti_min; /* min CCTI for cc table */
276f48ad614SDennis Dalessandro } __packed;
277f48ad614SDennis Dalessandro 
278f48ad614SDennis Dalessandro struct opa_congestion_setting_entry_shadow {
279f48ad614SDennis Dalessandro 	u8 ccti_increase;
280f48ad614SDennis Dalessandro 	u8 reserved;
281f48ad614SDennis Dalessandro 	u16 ccti_timer;
282f48ad614SDennis Dalessandro 	u8 trigger_threshold;
283f48ad614SDennis Dalessandro 	u8 ccti_min; /* min CCTI for cc table */
284f48ad614SDennis Dalessandro } __packed;
285f48ad614SDennis Dalessandro 
286f48ad614SDennis Dalessandro struct opa_congestion_setting_attr {
287f48ad614SDennis Dalessandro 	__be32 control_map;
288f48ad614SDennis Dalessandro 	__be16 port_control;
289f48ad614SDennis Dalessandro 	struct opa_congestion_setting_entry entries[OPA_MAX_SLS];
290f48ad614SDennis Dalessandro } __packed;
291f48ad614SDennis Dalessandro 
292f48ad614SDennis Dalessandro struct opa_congestion_setting_attr_shadow {
293f48ad614SDennis Dalessandro 	u32 control_map;
294f48ad614SDennis Dalessandro 	u16 port_control;
295f48ad614SDennis Dalessandro 	struct opa_congestion_setting_entry_shadow entries[OPA_MAX_SLS];
296f48ad614SDennis Dalessandro } __packed;
297f48ad614SDennis Dalessandro 
298f48ad614SDennis Dalessandro #define IB_CC_TABLE_ENTRY_INCREASE_DEFAULT 1
299f48ad614SDennis Dalessandro #define IB_CC_TABLE_ENTRY_TIMER_DEFAULT 1
300f48ad614SDennis Dalessandro 
301f48ad614SDennis Dalessandro /* 64 Congestion Control table entries in a single MAD */
302f48ad614SDennis Dalessandro #define IB_CCT_ENTRIES 64
303f48ad614SDennis Dalessandro #define IB_CCT_MIN_ENTRIES (IB_CCT_ENTRIES * 2)
304f48ad614SDennis Dalessandro 
305f48ad614SDennis Dalessandro struct ib_cc_table_entry {
306f48ad614SDennis Dalessandro 	__be16 entry; /* shift:2, multiplier:14 */
307f48ad614SDennis Dalessandro };
308f48ad614SDennis Dalessandro 
309f48ad614SDennis Dalessandro struct ib_cc_table_entry_shadow {
310f48ad614SDennis Dalessandro 	u16 entry; /* shift:2, multiplier:14 */
311f48ad614SDennis Dalessandro };
312f48ad614SDennis Dalessandro 
313f48ad614SDennis Dalessandro struct ib_cc_table_attr {
314f48ad614SDennis Dalessandro 	__be16 ccti_limit; /* max CCTI for cc table */
315f48ad614SDennis Dalessandro 	struct ib_cc_table_entry ccti_entries[IB_CCT_ENTRIES];
316f48ad614SDennis Dalessandro } __packed;
317f48ad614SDennis Dalessandro 
318f48ad614SDennis Dalessandro struct ib_cc_table_attr_shadow {
319f48ad614SDennis Dalessandro 	u16 ccti_limit; /* max CCTI for cc table */
320f48ad614SDennis Dalessandro 	struct ib_cc_table_entry_shadow ccti_entries[IB_CCT_ENTRIES];
321f48ad614SDennis Dalessandro } __packed;
322f48ad614SDennis Dalessandro 
323f48ad614SDennis Dalessandro #define CC_TABLE_SHADOW_MAX \
324f48ad614SDennis Dalessandro 	(IB_CC_TABLE_CAP_DEFAULT * IB_CCT_ENTRIES)
325f48ad614SDennis Dalessandro 
326f48ad614SDennis Dalessandro struct cc_table_shadow {
327f48ad614SDennis Dalessandro 	u16 ccti_limit; /* max CCTI for cc table */
328f48ad614SDennis Dalessandro 	struct ib_cc_table_entry_shadow entries[CC_TABLE_SHADOW_MAX];
329f48ad614SDennis Dalessandro } __packed;
330f48ad614SDennis Dalessandro 
331f48ad614SDennis Dalessandro /*
332f48ad614SDennis Dalessandro  * struct cc_state combines the (active) per-port congestion control
333f48ad614SDennis Dalessandro  * table, and the (active) per-SL congestion settings. cc_state data
334f48ad614SDennis Dalessandro  * may need to be read in code paths that we want to be fast, so it
335f48ad614SDennis Dalessandro  * is an RCU protected structure.
336f48ad614SDennis Dalessandro  */
337f48ad614SDennis Dalessandro struct cc_state {
338f48ad614SDennis Dalessandro 	struct rcu_head rcu;
339f48ad614SDennis Dalessandro 	struct cc_table_shadow cct;
340f48ad614SDennis Dalessandro 	struct opa_congestion_setting_attr_shadow cong_setting;
341f48ad614SDennis Dalessandro };
342f48ad614SDennis Dalessandro 
343f48ad614SDennis Dalessandro /*
344f48ad614SDennis Dalessandro  * OPA BufferControl MAD
345f48ad614SDennis Dalessandro  */
346f48ad614SDennis Dalessandro 
347f48ad614SDennis Dalessandro /* attribute modifier macros */
348f48ad614SDennis Dalessandro #define OPA_AM_NPORT_SHIFT	24
349f48ad614SDennis Dalessandro #define OPA_AM_NPORT_MASK	0xff
350f48ad614SDennis Dalessandro #define OPA_AM_NPORT_SMASK	(OPA_AM_NPORT_MASK << OPA_AM_NPORT_SHIFT)
351f48ad614SDennis Dalessandro #define OPA_AM_NPORT(am)	(((am) >> OPA_AM_NPORT_SHIFT) & \
352f48ad614SDennis Dalessandro 					OPA_AM_NPORT_MASK)
353f48ad614SDennis Dalessandro 
354f48ad614SDennis Dalessandro #define OPA_AM_NBLK_SHIFT	24
355f48ad614SDennis Dalessandro #define OPA_AM_NBLK_MASK	0xff
356f48ad614SDennis Dalessandro #define OPA_AM_NBLK_SMASK	(OPA_AM_NBLK_MASK << OPA_AM_NBLK_SHIFT)
357f48ad614SDennis Dalessandro #define OPA_AM_NBLK(am)		(((am) >> OPA_AM_NBLK_SHIFT) & \
358f48ad614SDennis Dalessandro 					OPA_AM_NBLK_MASK)
359f48ad614SDennis Dalessandro 
360f48ad614SDennis Dalessandro #define OPA_AM_START_BLK_SHIFT	0
361f48ad614SDennis Dalessandro #define OPA_AM_START_BLK_MASK	0xff
362f48ad614SDennis Dalessandro #define OPA_AM_START_BLK_SMASK	(OPA_AM_START_BLK_MASK << \
363f48ad614SDennis Dalessandro 					OPA_AM_START_BLK_SHIFT)
364f48ad614SDennis Dalessandro #define OPA_AM_START_BLK(am)	(((am) >> OPA_AM_START_BLK_SHIFT) & \
365f48ad614SDennis Dalessandro 					OPA_AM_START_BLK_MASK)
366f48ad614SDennis Dalessandro 
367f48ad614SDennis Dalessandro #define OPA_AM_PORTNUM_SHIFT	0
368f48ad614SDennis Dalessandro #define OPA_AM_PORTNUM_MASK	0xff
369f48ad614SDennis Dalessandro #define OPA_AM_PORTNUM_SMASK	(OPA_AM_PORTNUM_MASK << OPA_AM_PORTNUM_SHIFT)
370f48ad614SDennis Dalessandro #define OPA_AM_PORTNUM(am)	(((am) >> OPA_AM_PORTNUM_SHIFT) & \
371f48ad614SDennis Dalessandro 					OPA_AM_PORTNUM_MASK)
372f48ad614SDennis Dalessandro 
373f48ad614SDennis Dalessandro #define OPA_AM_ASYNC_SHIFT	12
374f48ad614SDennis Dalessandro #define OPA_AM_ASYNC_MASK	0x1
375f48ad614SDennis Dalessandro #define OPA_AM_ASYNC_SMASK	(OPA_AM_ASYNC_MASK << OPA_AM_ASYNC_SHIFT)
376f48ad614SDennis Dalessandro #define OPA_AM_ASYNC(am)	(((am) >> OPA_AM_ASYNC_SHIFT) & \
377f48ad614SDennis Dalessandro 					OPA_AM_ASYNC_MASK)
378f48ad614SDennis Dalessandro 
379f48ad614SDennis Dalessandro #define OPA_AM_START_SM_CFG_SHIFT	9
380f48ad614SDennis Dalessandro #define OPA_AM_START_SM_CFG_MASK	0x1
381f48ad614SDennis Dalessandro #define OPA_AM_START_SM_CFG_SMASK	(OPA_AM_START_SM_CFG_MASK << \
382f48ad614SDennis Dalessandro 						OPA_AM_START_SM_CFG_SHIFT)
383f48ad614SDennis Dalessandro #define OPA_AM_START_SM_CFG(am)		(((am) >> OPA_AM_START_SM_CFG_SHIFT) \
384f48ad614SDennis Dalessandro 						& OPA_AM_START_SM_CFG_MASK)
385f48ad614SDennis Dalessandro 
386f48ad614SDennis Dalessandro #define OPA_AM_CI_ADDR_SHIFT	19
387f48ad614SDennis Dalessandro #define OPA_AM_CI_ADDR_MASK	0xfff
388f48ad614SDennis Dalessandro #define OPA_AM_CI_ADDR_SMASK	(OPA_AM_CI_ADDR_MASK << OPA_CI_ADDR_SHIFT)
389f48ad614SDennis Dalessandro #define OPA_AM_CI_ADDR(am)	(((am) >> OPA_AM_CI_ADDR_SHIFT) & \
390f48ad614SDennis Dalessandro 					OPA_AM_CI_ADDR_MASK)
391f48ad614SDennis Dalessandro 
392f48ad614SDennis Dalessandro #define OPA_AM_CI_LEN_SHIFT	13
393f48ad614SDennis Dalessandro #define OPA_AM_CI_LEN_MASK	0x3f
394f48ad614SDennis Dalessandro #define OPA_AM_CI_LEN_SMASK	(OPA_AM_CI_LEN_MASK << OPA_CI_LEN_SHIFT)
395f48ad614SDennis Dalessandro #define OPA_AM_CI_LEN(am)	(((am) >> OPA_AM_CI_LEN_SHIFT) & \
396f48ad614SDennis Dalessandro 					OPA_AM_CI_LEN_MASK)
397f48ad614SDennis Dalessandro 
398f48ad614SDennis Dalessandro /* error info macros */
399f48ad614SDennis Dalessandro #define OPA_EI_STATUS_SMASK	0x80
400f48ad614SDennis Dalessandro #define OPA_EI_CODE_SMASK	0x0f
401f48ad614SDennis Dalessandro 
402f48ad614SDennis Dalessandro struct vl_limit {
403f48ad614SDennis Dalessandro 	__be16 dedicated;
404f48ad614SDennis Dalessandro 	__be16 shared;
405f48ad614SDennis Dalessandro };
406f48ad614SDennis Dalessandro 
407f48ad614SDennis Dalessandro struct buffer_control {
408f48ad614SDennis Dalessandro 	__be16 reserved;
409f48ad614SDennis Dalessandro 	__be16 overall_shared_limit;
410f48ad614SDennis Dalessandro 	struct vl_limit vl[OPA_MAX_VLS];
411f48ad614SDennis Dalessandro };
412f48ad614SDennis Dalessandro 
413f48ad614SDennis Dalessandro struct sc2vlnt {
414f48ad614SDennis Dalessandro 	u8 vlnt[32]; /* 5 bit VL, 3 bits reserved */
415f48ad614SDennis Dalessandro };
416f48ad614SDennis Dalessandro 
417f48ad614SDennis Dalessandro /*
418f48ad614SDennis Dalessandro  * The PortSamplesControl.CounterMasks field is an array of 3 bit fields
419f48ad614SDennis Dalessandro  * which specify the N'th counter's capabilities. See ch. 16.1.3.2.
420f48ad614SDennis Dalessandro  * We support 5 counters which only count the mandatory quantities.
421f48ad614SDennis Dalessandro  */
422f48ad614SDennis Dalessandro #define COUNTER_MASK(q, n) (q << ((9 - n) * 3))
423f48ad614SDennis Dalessandro #define COUNTER_MASK0_9 \
424f48ad614SDennis Dalessandro 	cpu_to_be32(COUNTER_MASK(1, 0) | \
425f48ad614SDennis Dalessandro 		    COUNTER_MASK(1, 1) | \
426f48ad614SDennis Dalessandro 		    COUNTER_MASK(1, 2) | \
427f48ad614SDennis Dalessandro 		    COUNTER_MASK(1, 3) | \
428f48ad614SDennis Dalessandro 		    COUNTER_MASK(1, 4))
429f48ad614SDennis Dalessandro 
43034d351f8SSebastian Sanchez void hfi1_event_pkey_change(struct hfi1_devdata *dd, u8 port);
431*bf90aaddSMichael J. Ruhl void hfi1_handle_trap_timer(unsigned long data);
43234d351f8SSebastian Sanchez 
433f48ad614SDennis Dalessandro #endif				/* _HFI1_MAD_H */
434