1*145eba1aSCai Huoqing /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
2f48ad614SDennis Dalessandro /*
3bf90aaddSMichael J. Ruhl * Copyright(c) 2015 - 2017 Intel Corporation.
4f48ad614SDennis Dalessandro */
5*145eba1aSCai Huoqing
6f48ad614SDennis Dalessandro #ifndef _HFI1_MAD_H
7f48ad614SDennis Dalessandro #define _HFI1_MAD_H
8f48ad614SDennis Dalessandro
9f48ad614SDennis Dalessandro #include <rdma/ib_pma.h>
10f48ad614SDennis Dalessandro #include <rdma/opa_smi.h>
11f48ad614SDennis Dalessandro #include <rdma/opa_port_info.h>
12f48ad614SDennis Dalessandro #include "opa_compat.h"
13f48ad614SDennis Dalessandro
14f48ad614SDennis Dalessandro /*
15f48ad614SDennis Dalessandro * OPA Traps
16f48ad614SDennis Dalessandro */
17f48ad614SDennis Dalessandro #define OPA_TRAP_GID_NOW_IN_SERVICE cpu_to_be16(64)
18f48ad614SDennis Dalessandro #define OPA_TRAP_GID_OUT_OF_SERVICE cpu_to_be16(65)
19f48ad614SDennis Dalessandro #define OPA_TRAP_ADD_MULTICAST_GROUP cpu_to_be16(66)
20f48ad614SDennis Dalessandro #define OPA_TRAL_DEL_MULTICAST_GROUP cpu_to_be16(67)
21f48ad614SDennis Dalessandro #define OPA_TRAP_UNPATH cpu_to_be16(68)
22f48ad614SDennis Dalessandro #define OPA_TRAP_REPATH cpu_to_be16(69)
23f48ad614SDennis Dalessandro #define OPA_TRAP_PORT_CHANGE_STATE cpu_to_be16(128)
24f48ad614SDennis Dalessandro #define OPA_TRAP_LINK_INTEGRITY cpu_to_be16(129)
25f48ad614SDennis Dalessandro #define OPA_TRAP_EXCESSIVE_BUFFER_OVERRUN cpu_to_be16(130)
26f48ad614SDennis Dalessandro #define OPA_TRAP_FLOW_WATCHDOG cpu_to_be16(131)
27f48ad614SDennis Dalessandro #define OPA_TRAP_CHANGE_CAPABILITY cpu_to_be16(144)
28f48ad614SDennis Dalessandro #define OPA_TRAP_CHANGE_SYSGUID cpu_to_be16(145)
29f48ad614SDennis Dalessandro #define OPA_TRAP_BAD_M_KEY cpu_to_be16(256)
30f48ad614SDennis Dalessandro #define OPA_TRAP_BAD_P_KEY cpu_to_be16(257)
31f48ad614SDennis Dalessandro #define OPA_TRAP_BAD_Q_KEY cpu_to_be16(258)
32f48ad614SDennis Dalessandro #define OPA_TRAP_SWITCH_BAD_PKEY cpu_to_be16(259)
33f48ad614SDennis Dalessandro #define OPA_SMA_TRAP_DATA_LINK_WIDTH cpu_to_be16(2048)
34f48ad614SDennis Dalessandro
35f48ad614SDennis Dalessandro /*
36f48ad614SDennis Dalessandro * Generic trap/notice other local changes flags (trap 144).
37f48ad614SDennis Dalessandro */
38f48ad614SDennis Dalessandro #define OPA_NOTICE_TRAP_LWDE_CHG 0x08 /* Link Width Downgrade Enable
39f48ad614SDennis Dalessandro * changed
40f48ad614SDennis Dalessandro */
41f48ad614SDennis Dalessandro #define OPA_NOTICE_TRAP_LSE_CHG 0x04 /* Link Speed Enable changed */
42f48ad614SDennis Dalessandro #define OPA_NOTICE_TRAP_LWE_CHG 0x02 /* Link Width Enable changed */
43f48ad614SDennis Dalessandro #define OPA_NOTICE_TRAP_NODE_DESC_CHG 0x01
44f48ad614SDennis Dalessandro
45f48ad614SDennis Dalessandro struct opa_mad_notice_attr {
46f48ad614SDennis Dalessandro u8 generic_type;
47f48ad614SDennis Dalessandro u8 prod_type_msb;
48f48ad614SDennis Dalessandro __be16 prod_type_lsb;
49f48ad614SDennis Dalessandro __be16 trap_num;
50f48ad614SDennis Dalessandro __be16 toggle_count;
51f48ad614SDennis Dalessandro __be32 issuer_lid;
52f48ad614SDennis Dalessandro __be32 reserved1;
53f48ad614SDennis Dalessandro union ib_gid issuer_gid;
54f48ad614SDennis Dalessandro
55f48ad614SDennis Dalessandro union {
56f48ad614SDennis Dalessandro struct {
57f48ad614SDennis Dalessandro u8 details[64];
58f48ad614SDennis Dalessandro } raw_data;
59f48ad614SDennis Dalessandro
60f48ad614SDennis Dalessandro struct {
61f48ad614SDennis Dalessandro union ib_gid gid;
62f48ad614SDennis Dalessandro } __packed ntc_64_65_66_67;
63f48ad614SDennis Dalessandro
64f48ad614SDennis Dalessandro struct {
65f48ad614SDennis Dalessandro __be32 lid;
66f48ad614SDennis Dalessandro } __packed ntc_128;
67f48ad614SDennis Dalessandro
68f48ad614SDennis Dalessandro struct {
69f48ad614SDennis Dalessandro __be32 lid; /* where violation happened */
70f48ad614SDennis Dalessandro u8 port_num; /* where violation happened */
71f48ad614SDennis Dalessandro } __packed ntc_129_130_131;
72f48ad614SDennis Dalessandro
73f48ad614SDennis Dalessandro struct {
74f48ad614SDennis Dalessandro __be32 lid; /* LID where change occurred */
75f48ad614SDennis Dalessandro __be32 new_cap_mask; /* new capability mask */
76f48ad614SDennis Dalessandro __be16 reserved2;
77cb49366fSVishwanathapura, Niranjana __be16 cap_mask3;
78f48ad614SDennis Dalessandro __be16 change_flags; /* low 4 bits only */
79f48ad614SDennis Dalessandro } __packed ntc_144;
80f48ad614SDennis Dalessandro
81f48ad614SDennis Dalessandro struct {
82f48ad614SDennis Dalessandro __be64 new_sys_guid;
83f48ad614SDennis Dalessandro __be32 lid; /* lid where sys guid changed */
84f48ad614SDennis Dalessandro } __packed ntc_145;
85f48ad614SDennis Dalessandro
86f48ad614SDennis Dalessandro struct {
87f48ad614SDennis Dalessandro __be32 lid;
88f48ad614SDennis Dalessandro __be32 dr_slid;
89f48ad614SDennis Dalessandro u8 method;
90f48ad614SDennis Dalessandro u8 dr_trunc_hop;
91f48ad614SDennis Dalessandro __be16 attr_id;
92f48ad614SDennis Dalessandro __be32 attr_mod;
93f48ad614SDennis Dalessandro __be64 mkey;
94f48ad614SDennis Dalessandro u8 dr_rtn_path[30];
95f48ad614SDennis Dalessandro } __packed ntc_256;
96f48ad614SDennis Dalessandro
97f48ad614SDennis Dalessandro struct {
98f48ad614SDennis Dalessandro __be32 lid1;
99f48ad614SDennis Dalessandro __be32 lid2;
100f48ad614SDennis Dalessandro __be32 key;
101f48ad614SDennis Dalessandro u8 sl; /* SL: high 5 bits */
102f48ad614SDennis Dalessandro u8 reserved3[3];
103f48ad614SDennis Dalessandro union ib_gid gid1;
104f48ad614SDennis Dalessandro union ib_gid gid2;
105f48ad614SDennis Dalessandro __be32 qp1; /* high 8 bits reserved */
106f48ad614SDennis Dalessandro __be32 qp2; /* high 8 bits reserved */
107f48ad614SDennis Dalessandro } __packed ntc_257_258;
108f48ad614SDennis Dalessandro
109f48ad614SDennis Dalessandro struct {
110f48ad614SDennis Dalessandro __be16 flags; /* low 8 bits reserved */
111f48ad614SDennis Dalessandro __be16 pkey;
112f48ad614SDennis Dalessandro __be32 lid1;
113f48ad614SDennis Dalessandro __be32 lid2;
114f48ad614SDennis Dalessandro u8 sl; /* SL: high 5 bits */
115f48ad614SDennis Dalessandro u8 reserved4[3];
116f48ad614SDennis Dalessandro union ib_gid gid1;
117f48ad614SDennis Dalessandro union ib_gid gid2;
118f48ad614SDennis Dalessandro __be32 qp1; /* high 8 bits reserved */
119f48ad614SDennis Dalessandro __be32 qp2; /* high 8 bits reserved */
120f48ad614SDennis Dalessandro } __packed ntc_259;
121f48ad614SDennis Dalessandro
122f48ad614SDennis Dalessandro struct {
123f48ad614SDennis Dalessandro __be32 lid;
124f48ad614SDennis Dalessandro } __packed ntc_2048;
125f48ad614SDennis Dalessandro
126f48ad614SDennis Dalessandro };
1275b361328SGustavo A. R. Silva u8 class_data[];
128f48ad614SDennis Dalessandro };
129f48ad614SDennis Dalessandro
130f48ad614SDennis Dalessandro #define IB_VLARB_LOWPRI_0_31 1
131f48ad614SDennis Dalessandro #define IB_VLARB_LOWPRI_32_63 2
132f48ad614SDennis Dalessandro #define IB_VLARB_HIGHPRI_0_31 3
133f48ad614SDennis Dalessandro #define IB_VLARB_HIGHPRI_32_63 4
134f48ad614SDennis Dalessandro
135f48ad614SDennis Dalessandro #define OPA_MAX_PREEMPT_CAP 32
136f48ad614SDennis Dalessandro #define OPA_VLARB_LOW_ELEMENTS 0
137f48ad614SDennis Dalessandro #define OPA_VLARB_HIGH_ELEMENTS 1
138f48ad614SDennis Dalessandro #define OPA_VLARB_PREEMPT_ELEMENTS 2
139f48ad614SDennis Dalessandro #define OPA_VLARB_PREEMPT_MATRIX 3
140f48ad614SDennis Dalessandro
141f48ad614SDennis Dalessandro #define IB_PMA_PORT_COUNTERS_CONG cpu_to_be16(0xFF00)
14207190076SKamenee Arumugam #define LINK_SPEED_25G 1
14307190076SKamenee Arumugam #define LINK_SPEED_12_5G 2
14407190076SKamenee Arumugam #define LINK_WIDTH_DEFAULT 4
14507190076SKamenee Arumugam #define DECIMAL_FACTORING 1000
14607190076SKamenee Arumugam /*
14707190076SKamenee Arumugam * The default link width is multiplied by 1000
14807190076SKamenee Arumugam * to get accurate value after division.
14907190076SKamenee Arumugam */
15007190076SKamenee Arumugam #define FACTOR_LINK_WIDTH (LINK_WIDTH_DEFAULT * DECIMAL_FACTORING)
151f48ad614SDennis Dalessandro
152f48ad614SDennis Dalessandro struct ib_pma_portcounters_cong {
153f48ad614SDennis Dalessandro u8 reserved;
154f48ad614SDennis Dalessandro u8 reserved1;
155f48ad614SDennis Dalessandro __be16 port_check_rate;
156f48ad614SDennis Dalessandro __be16 symbol_error_counter;
157f48ad614SDennis Dalessandro u8 link_error_recovery_counter;
158f48ad614SDennis Dalessandro u8 link_downed_counter;
159f48ad614SDennis Dalessandro __be16 port_rcv_errors;
160f48ad614SDennis Dalessandro __be16 port_rcv_remphys_errors;
161f48ad614SDennis Dalessandro __be16 port_rcv_switch_relay_errors;
162f48ad614SDennis Dalessandro __be16 port_xmit_discards;
163f48ad614SDennis Dalessandro u8 port_xmit_constraint_errors;
164f48ad614SDennis Dalessandro u8 port_rcv_constraint_errors;
165f48ad614SDennis Dalessandro u8 reserved2;
166f48ad614SDennis Dalessandro u8 link_overrun_errors; /* LocalLink: 7:4, BufferOverrun: 3:0 */
167f48ad614SDennis Dalessandro __be16 reserved3;
168f48ad614SDennis Dalessandro __be16 vl15_dropped;
169f48ad614SDennis Dalessandro __be64 port_xmit_data;
170f48ad614SDennis Dalessandro __be64 port_rcv_data;
171f48ad614SDennis Dalessandro __be64 port_xmit_packets;
172f48ad614SDennis Dalessandro __be64 port_rcv_packets;
173f48ad614SDennis Dalessandro __be64 port_xmit_wait;
174f48ad614SDennis Dalessandro __be64 port_adr_events;
175f48ad614SDennis Dalessandro } __packed;
176f48ad614SDennis Dalessandro
177f48ad614SDennis Dalessandro #define IB_SMP_UNSUP_VERSION cpu_to_be16(0x0004)
178f48ad614SDennis Dalessandro #define IB_SMP_UNSUP_METHOD cpu_to_be16(0x0008)
179f48ad614SDennis Dalessandro #define IB_SMP_UNSUP_METH_ATTR cpu_to_be16(0x000C)
180f48ad614SDennis Dalessandro #define IB_SMP_INVALID_FIELD cpu_to_be16(0x001C)
181f48ad614SDennis Dalessandro
182f48ad614SDennis Dalessandro #define OPA_MAX_PREEMPT_CAP 32
183f48ad614SDennis Dalessandro #define OPA_VLARB_LOW_ELEMENTS 0
184f48ad614SDennis Dalessandro #define OPA_VLARB_HIGH_ELEMENTS 1
185f48ad614SDennis Dalessandro #define OPA_VLARB_PREEMPT_ELEMENTS 2
186f48ad614SDennis Dalessandro #define OPA_VLARB_PREEMPT_MATRIX 3
187f48ad614SDennis Dalessandro
188f48ad614SDennis Dalessandro #define HFI1_XMIT_RATE_UNSUPPORTED 0x0
189f48ad614SDennis Dalessandro #define HFI1_XMIT_RATE_PICO 0x7
190f48ad614SDennis Dalessandro /* number of 4nsec cycles equaling 2secs */
191f48ad614SDennis Dalessandro #define HFI1_CONG_TIMER_PSINTERVAL 0x1DCD64EC
192f48ad614SDennis Dalessandro
193f48ad614SDennis Dalessandro #define IB_CC_SVCTYPE_RC 0x0
194f48ad614SDennis Dalessandro #define IB_CC_SVCTYPE_UC 0x1
195f48ad614SDennis Dalessandro #define IB_CC_SVCTYPE_RD 0x2
196f48ad614SDennis Dalessandro #define IB_CC_SVCTYPE_UD 0x3
197f48ad614SDennis Dalessandro
198f48ad614SDennis Dalessandro /*
199f48ad614SDennis Dalessandro * There should be an equivalent IB #define for the following, but
200f48ad614SDennis Dalessandro * I cannot find it.
201f48ad614SDennis Dalessandro */
202f48ad614SDennis Dalessandro #define OPA_CC_LOG_TYPE_HFI 2
203f48ad614SDennis Dalessandro
204f48ad614SDennis Dalessandro struct opa_hfi1_cong_log_event_internal {
205f48ad614SDennis Dalessandro u32 lqpn;
206f48ad614SDennis Dalessandro u32 rqpn;
207f48ad614SDennis Dalessandro u8 sl;
208f48ad614SDennis Dalessandro u8 svc_type;
209f48ad614SDennis Dalessandro u32 rlid;
210d61ea075SMike Marciniszyn u64 timestamp; /* wider than 32 bits to detect 32 bit rollover */
211f48ad614SDennis Dalessandro };
212f48ad614SDennis Dalessandro
213f48ad614SDennis Dalessandro struct opa_hfi1_cong_log_event {
214f48ad614SDennis Dalessandro u8 local_qp_cn_entry[3];
215f48ad614SDennis Dalessandro u8 remote_qp_number_cn_entry[3];
216f48ad614SDennis Dalessandro u8 sl_svc_type_cn_entry; /* 5 bits SL, 3 bits svc type */
217f48ad614SDennis Dalessandro u8 reserved;
218f48ad614SDennis Dalessandro __be32 remote_lid_cn_entry;
219f48ad614SDennis Dalessandro __be32 timestamp_cn_entry;
220f48ad614SDennis Dalessandro } __packed;
221f48ad614SDennis Dalessandro
222f48ad614SDennis Dalessandro #define OPA_CONG_LOG_ELEMS 96
223f48ad614SDennis Dalessandro
224f48ad614SDennis Dalessandro struct opa_hfi1_cong_log {
225f48ad614SDennis Dalessandro u8 log_type;
226f48ad614SDennis Dalessandro u8 congestion_flags;
227f48ad614SDennis Dalessandro __be16 threshold_event_counter;
228f48ad614SDennis Dalessandro __be32 current_time_stamp;
229f48ad614SDennis Dalessandro u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
230f48ad614SDennis Dalessandro struct opa_hfi1_cong_log_event events[OPA_CONG_LOG_ELEMS];
231f48ad614SDennis Dalessandro } __packed;
232f48ad614SDennis Dalessandro
233f48ad614SDennis Dalessandro #define IB_CC_TABLE_CAP_DEFAULT 31
234f48ad614SDennis Dalessandro
235f48ad614SDennis Dalessandro /* Port control flags */
236f48ad614SDennis Dalessandro #define IB_CC_CCS_PC_SL_BASED 0x01
237f48ad614SDennis Dalessandro
238f48ad614SDennis Dalessandro struct opa_congestion_setting_entry {
239f48ad614SDennis Dalessandro u8 ccti_increase;
240f48ad614SDennis Dalessandro u8 reserved;
241f48ad614SDennis Dalessandro __be16 ccti_timer;
242f48ad614SDennis Dalessandro u8 trigger_threshold;
243f48ad614SDennis Dalessandro u8 ccti_min; /* min CCTI for cc table */
244f48ad614SDennis Dalessandro } __packed;
245f48ad614SDennis Dalessandro
246f48ad614SDennis Dalessandro struct opa_congestion_setting_entry_shadow {
247f48ad614SDennis Dalessandro u8 ccti_increase;
248f48ad614SDennis Dalessandro u8 reserved;
249f48ad614SDennis Dalessandro u16 ccti_timer;
250f48ad614SDennis Dalessandro u8 trigger_threshold;
251f48ad614SDennis Dalessandro u8 ccti_min; /* min CCTI for cc table */
252f48ad614SDennis Dalessandro } __packed;
253f48ad614SDennis Dalessandro
254f48ad614SDennis Dalessandro struct opa_congestion_setting_attr {
255f48ad614SDennis Dalessandro __be32 control_map;
256f48ad614SDennis Dalessandro __be16 port_control;
257f48ad614SDennis Dalessandro struct opa_congestion_setting_entry entries[OPA_MAX_SLS];
258f48ad614SDennis Dalessandro } __packed;
259f48ad614SDennis Dalessandro
260f48ad614SDennis Dalessandro struct opa_congestion_setting_attr_shadow {
261f48ad614SDennis Dalessandro u32 control_map;
262f48ad614SDennis Dalessandro u16 port_control;
263f48ad614SDennis Dalessandro struct opa_congestion_setting_entry_shadow entries[OPA_MAX_SLS];
264f48ad614SDennis Dalessandro } __packed;
265f48ad614SDennis Dalessandro
266f48ad614SDennis Dalessandro #define IB_CC_TABLE_ENTRY_INCREASE_DEFAULT 1
267f48ad614SDennis Dalessandro #define IB_CC_TABLE_ENTRY_TIMER_DEFAULT 1
268f48ad614SDennis Dalessandro
269f48ad614SDennis Dalessandro /* 64 Congestion Control table entries in a single MAD */
270f48ad614SDennis Dalessandro #define IB_CCT_ENTRIES 64
271f48ad614SDennis Dalessandro #define IB_CCT_MIN_ENTRIES (IB_CCT_ENTRIES * 2)
272f48ad614SDennis Dalessandro
273f48ad614SDennis Dalessandro struct ib_cc_table_entry {
274f48ad614SDennis Dalessandro __be16 entry; /* shift:2, multiplier:14 */
275f48ad614SDennis Dalessandro };
276f48ad614SDennis Dalessandro
277f48ad614SDennis Dalessandro struct ib_cc_table_entry_shadow {
278f48ad614SDennis Dalessandro u16 entry; /* shift:2, multiplier:14 */
279f48ad614SDennis Dalessandro };
280f48ad614SDennis Dalessandro
281f48ad614SDennis Dalessandro struct ib_cc_table_attr {
282f48ad614SDennis Dalessandro __be16 ccti_limit; /* max CCTI for cc table */
283f48ad614SDennis Dalessandro struct ib_cc_table_entry ccti_entries[IB_CCT_ENTRIES];
284f48ad614SDennis Dalessandro } __packed;
285f48ad614SDennis Dalessandro
286f48ad614SDennis Dalessandro struct ib_cc_table_attr_shadow {
287f48ad614SDennis Dalessandro u16 ccti_limit; /* max CCTI for cc table */
288f48ad614SDennis Dalessandro struct ib_cc_table_entry_shadow ccti_entries[IB_CCT_ENTRIES];
289f48ad614SDennis Dalessandro } __packed;
290f48ad614SDennis Dalessandro
291f48ad614SDennis Dalessandro #define CC_TABLE_SHADOW_MAX \
292f48ad614SDennis Dalessandro (IB_CC_TABLE_CAP_DEFAULT * IB_CCT_ENTRIES)
293f48ad614SDennis Dalessandro
294f48ad614SDennis Dalessandro struct cc_table_shadow {
295f48ad614SDennis Dalessandro u16 ccti_limit; /* max CCTI for cc table */
296f48ad614SDennis Dalessandro struct ib_cc_table_entry_shadow entries[CC_TABLE_SHADOW_MAX];
297f48ad614SDennis Dalessandro } __packed;
298f48ad614SDennis Dalessandro
299f48ad614SDennis Dalessandro /*
300f48ad614SDennis Dalessandro * struct cc_state combines the (active) per-port congestion control
301f48ad614SDennis Dalessandro * table, and the (active) per-SL congestion settings. cc_state data
302f48ad614SDennis Dalessandro * may need to be read in code paths that we want to be fast, so it
303f48ad614SDennis Dalessandro * is an RCU protected structure.
304f48ad614SDennis Dalessandro */
305f48ad614SDennis Dalessandro struct cc_state {
306f48ad614SDennis Dalessandro struct rcu_head rcu;
307f48ad614SDennis Dalessandro struct cc_table_shadow cct;
308f48ad614SDennis Dalessandro struct opa_congestion_setting_attr_shadow cong_setting;
309f48ad614SDennis Dalessandro };
310f48ad614SDennis Dalessandro
311f48ad614SDennis Dalessandro /*
312f48ad614SDennis Dalessandro * OPA BufferControl MAD
313f48ad614SDennis Dalessandro */
314f48ad614SDennis Dalessandro
315f48ad614SDennis Dalessandro /* attribute modifier macros */
316f48ad614SDennis Dalessandro #define OPA_AM_NPORT_SHIFT 24
317f48ad614SDennis Dalessandro #define OPA_AM_NPORT_MASK 0xff
318f48ad614SDennis Dalessandro #define OPA_AM_NPORT_SMASK (OPA_AM_NPORT_MASK << OPA_AM_NPORT_SHIFT)
319f48ad614SDennis Dalessandro #define OPA_AM_NPORT(am) (((am) >> OPA_AM_NPORT_SHIFT) & \
320f48ad614SDennis Dalessandro OPA_AM_NPORT_MASK)
321f48ad614SDennis Dalessandro
322f48ad614SDennis Dalessandro #define OPA_AM_NBLK_SHIFT 24
323f48ad614SDennis Dalessandro #define OPA_AM_NBLK_MASK 0xff
324f48ad614SDennis Dalessandro #define OPA_AM_NBLK_SMASK (OPA_AM_NBLK_MASK << OPA_AM_NBLK_SHIFT)
325f48ad614SDennis Dalessandro #define OPA_AM_NBLK(am) (((am) >> OPA_AM_NBLK_SHIFT) & \
326f48ad614SDennis Dalessandro OPA_AM_NBLK_MASK)
327f48ad614SDennis Dalessandro
328f48ad614SDennis Dalessandro #define OPA_AM_START_BLK_SHIFT 0
329f48ad614SDennis Dalessandro #define OPA_AM_START_BLK_MASK 0xff
330f48ad614SDennis Dalessandro #define OPA_AM_START_BLK_SMASK (OPA_AM_START_BLK_MASK << \
331f48ad614SDennis Dalessandro OPA_AM_START_BLK_SHIFT)
332f48ad614SDennis Dalessandro #define OPA_AM_START_BLK(am) (((am) >> OPA_AM_START_BLK_SHIFT) & \
333f48ad614SDennis Dalessandro OPA_AM_START_BLK_MASK)
334f48ad614SDennis Dalessandro
335f48ad614SDennis Dalessandro #define OPA_AM_PORTNUM_SHIFT 0
336f48ad614SDennis Dalessandro #define OPA_AM_PORTNUM_MASK 0xff
337f48ad614SDennis Dalessandro #define OPA_AM_PORTNUM_SMASK (OPA_AM_PORTNUM_MASK << OPA_AM_PORTNUM_SHIFT)
338f48ad614SDennis Dalessandro #define OPA_AM_PORTNUM(am) (((am) >> OPA_AM_PORTNUM_SHIFT) & \
339f48ad614SDennis Dalessandro OPA_AM_PORTNUM_MASK)
340f48ad614SDennis Dalessandro
341f48ad614SDennis Dalessandro #define OPA_AM_ASYNC_SHIFT 12
342f48ad614SDennis Dalessandro #define OPA_AM_ASYNC_MASK 0x1
343f48ad614SDennis Dalessandro #define OPA_AM_ASYNC_SMASK (OPA_AM_ASYNC_MASK << OPA_AM_ASYNC_SHIFT)
344f48ad614SDennis Dalessandro #define OPA_AM_ASYNC(am) (((am) >> OPA_AM_ASYNC_SHIFT) & \
345f48ad614SDennis Dalessandro OPA_AM_ASYNC_MASK)
346f48ad614SDennis Dalessandro
347f48ad614SDennis Dalessandro #define OPA_AM_START_SM_CFG_SHIFT 9
348f48ad614SDennis Dalessandro #define OPA_AM_START_SM_CFG_MASK 0x1
349f48ad614SDennis Dalessandro #define OPA_AM_START_SM_CFG_SMASK (OPA_AM_START_SM_CFG_MASK << \
350f48ad614SDennis Dalessandro OPA_AM_START_SM_CFG_SHIFT)
351f48ad614SDennis Dalessandro #define OPA_AM_START_SM_CFG(am) (((am) >> OPA_AM_START_SM_CFG_SHIFT) \
352f48ad614SDennis Dalessandro & OPA_AM_START_SM_CFG_MASK)
353f48ad614SDennis Dalessandro
354f48ad614SDennis Dalessandro #define OPA_AM_CI_ADDR_SHIFT 19
355f48ad614SDennis Dalessandro #define OPA_AM_CI_ADDR_MASK 0xfff
356f48ad614SDennis Dalessandro #define OPA_AM_CI_ADDR_SMASK (OPA_AM_CI_ADDR_MASK << OPA_CI_ADDR_SHIFT)
357f48ad614SDennis Dalessandro #define OPA_AM_CI_ADDR(am) (((am) >> OPA_AM_CI_ADDR_SHIFT) & \
358f48ad614SDennis Dalessandro OPA_AM_CI_ADDR_MASK)
359f48ad614SDennis Dalessandro
360f48ad614SDennis Dalessandro #define OPA_AM_CI_LEN_SHIFT 13
361f48ad614SDennis Dalessandro #define OPA_AM_CI_LEN_MASK 0x3f
362f48ad614SDennis Dalessandro #define OPA_AM_CI_LEN_SMASK (OPA_AM_CI_LEN_MASK << OPA_CI_LEN_SHIFT)
363f48ad614SDennis Dalessandro #define OPA_AM_CI_LEN(am) (((am) >> OPA_AM_CI_LEN_SHIFT) & \
364f48ad614SDennis Dalessandro OPA_AM_CI_LEN_MASK)
365f48ad614SDennis Dalessandro
366f48ad614SDennis Dalessandro /* error info macros */
367f48ad614SDennis Dalessandro #define OPA_EI_STATUS_SMASK 0x80
368f48ad614SDennis Dalessandro #define OPA_EI_CODE_SMASK 0x0f
369f48ad614SDennis Dalessandro
370f48ad614SDennis Dalessandro struct vl_limit {
371f48ad614SDennis Dalessandro __be16 dedicated;
372f48ad614SDennis Dalessandro __be16 shared;
373f48ad614SDennis Dalessandro };
374f48ad614SDennis Dalessandro
375f48ad614SDennis Dalessandro struct buffer_control {
376f48ad614SDennis Dalessandro __be16 reserved;
377f48ad614SDennis Dalessandro __be16 overall_shared_limit;
378f48ad614SDennis Dalessandro struct vl_limit vl[OPA_MAX_VLS];
379f48ad614SDennis Dalessandro };
380f48ad614SDennis Dalessandro
381f48ad614SDennis Dalessandro struct sc2vlnt {
382f48ad614SDennis Dalessandro u8 vlnt[32]; /* 5 bit VL, 3 bits reserved */
383f48ad614SDennis Dalessandro };
384f48ad614SDennis Dalessandro
385f48ad614SDennis Dalessandro /*
386f48ad614SDennis Dalessandro * The PortSamplesControl.CounterMasks field is an array of 3 bit fields
387f48ad614SDennis Dalessandro * which specify the N'th counter's capabilities. See ch. 16.1.3.2.
388f48ad614SDennis Dalessandro * We support 5 counters which only count the mandatory quantities.
389f48ad614SDennis Dalessandro */
390f48ad614SDennis Dalessandro #define COUNTER_MASK(q, n) (q << ((9 - n) * 3))
391f48ad614SDennis Dalessandro #define COUNTER_MASK0_9 \
392f48ad614SDennis Dalessandro cpu_to_be32(COUNTER_MASK(1, 0) | \
393f48ad614SDennis Dalessandro COUNTER_MASK(1, 1) | \
394f48ad614SDennis Dalessandro COUNTER_MASK(1, 2) | \
395f48ad614SDennis Dalessandro COUNTER_MASK(1, 3) | \
396f48ad614SDennis Dalessandro COUNTER_MASK(1, 4))
397f48ad614SDennis Dalessandro
3981fb7f897SMark Bloch void hfi1_event_pkey_change(struct hfi1_devdata *dd, u32 port);
3998064135eSKees Cook void hfi1_handle_trap_timer(struct timer_list *t);
40007190076SKamenee Arumugam u16 tx_link_width(u16 link_width);
40107190076SKamenee Arumugam u64 get_xmit_wait_counters(struct hfi1_pportdata *ppd, u16 link_width,
40207190076SKamenee Arumugam u16 link_speed, int vl);
40307190076SKamenee Arumugam /**
40407190076SKamenee Arumugam * get_link_speed - determine whether 12.5G or 25G speed
40507190076SKamenee Arumugam * @link_speed: the speed of active link
40607190076SKamenee Arumugam * @return: Return 2 if link speed identified as 12.5G
40707190076SKamenee Arumugam * or return 1 if link speed is 25G.
40807190076SKamenee Arumugam *
40907190076SKamenee Arumugam * The function indirectly calculate required link speed
41007190076SKamenee Arumugam * value for convert_xmit_counter function. If the link
41107190076SKamenee Arumugam * speed is 25G, the function return as 1 as it is required
41207190076SKamenee Arumugam * by xmit counter conversion formula :-( 25G / link_speed).
41307190076SKamenee Arumugam * This conversion will provide value 1 if current
41407190076SKamenee Arumugam * link speed is 25G or 2 if 12.5G.This is done to avoid
41507190076SKamenee Arumugam * 12.5 float number conversion.
41607190076SKamenee Arumugam */
get_link_speed(u16 link_speed)41707190076SKamenee Arumugam static inline u16 get_link_speed(u16 link_speed)
41807190076SKamenee Arumugam {
41907190076SKamenee Arumugam return (link_speed == 1) ?
42007190076SKamenee Arumugam LINK_SPEED_12_5G : LINK_SPEED_25G;
42107190076SKamenee Arumugam }
42234d351f8SSebastian Sanchez
42307190076SKamenee Arumugam /**
42407190076SKamenee Arumugam * convert_xmit_counter - calculate flit times for given xmit counter
42507190076SKamenee Arumugam * value
42607190076SKamenee Arumugam * @xmit_wait_val: current xmit counter value
42707190076SKamenee Arumugam * @link_width: width of active link
42807190076SKamenee Arumugam * @link_speed: speed of active link
42907190076SKamenee Arumugam * @return: return xmit counter value in flit times.
43007190076SKamenee Arumugam */
convert_xmit_counter(u64 xmit_wait_val,u16 link_width,u16 link_speed)43107190076SKamenee Arumugam static inline u64 convert_xmit_counter(u64 xmit_wait_val, u16 link_width,
43207190076SKamenee Arumugam u16 link_speed)
43307190076SKamenee Arumugam {
43407190076SKamenee Arumugam return (xmit_wait_val * 2 * (FACTOR_LINK_WIDTH / link_width)
43507190076SKamenee Arumugam * link_speed) / DECIMAL_FACTORING;
43607190076SKamenee Arumugam }
437f48ad614SDennis Dalessandro #endif /* _HFI1_MAD_H */
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