1 /* 2 * Copyright(c) 2015, 2016 Intel Corporation. 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Redistribution and use in source and binary forms, with or without 21 * modification, are permitted provided that the following conditions 22 * are met: 23 * 24 * - Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * - Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in 28 * the documentation and/or other materials provided with the 29 * distribution. 30 * - Neither the name of Intel Corporation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 * 46 */ 47 #include <linux/delay.h> 48 #include "hfi.h" 49 #include "common.h" 50 #include "eprom.h" 51 52 /* 53 * The EPROM is logically divided into three partitions: 54 * partition 0: the first 128K, visible from PCI ROM BAR 55 * partition 1: 4K config file (sector size) 56 * partition 2: the rest 57 */ 58 #define P0_SIZE (128 * 1024) 59 #define P1_SIZE (4 * 1024) 60 #define P1_START P0_SIZE 61 #define P2_START (P0_SIZE + P1_SIZE) 62 63 /* controller page size, in bytes */ 64 #define EP_PAGE_SIZE 256 65 #define EP_PAGE_MASK (EP_PAGE_SIZE - 1) 66 #define EP_PAGE_DWORDS (EP_PAGE_SIZE / sizeof(u32)) 67 68 /* controller commands */ 69 #define CMD_SHIFT 24 70 #define CMD_NOP (0) 71 #define CMD_READ_DATA(addr) ((0x03 << CMD_SHIFT) | addr) 72 #define CMD_RELEASE_POWERDOWN_NOID ((0xab << CMD_SHIFT)) 73 74 /* controller interface speeds */ 75 #define EP_SPEED_FULL 0x2 /* full speed */ 76 77 /* 78 * How long to wait for the EPROM to become available, in ms. 79 * The spec 32 Mb EPROM takes around 40s to erase then write. 80 * Double it for safety. 81 */ 82 #define EPROM_TIMEOUT 80000 /* ms */ 83 84 /* 85 * Read a 256 byte (64 dword) EPROM page. 86 * All callers have verified the offset is at a page boundary. 87 */ 88 static void read_page(struct hfi1_devdata *dd, u32 offset, u32 *result) 89 { 90 int i; 91 92 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_DATA(offset)); 93 for (i = 0; i < EP_PAGE_DWORDS; i++) 94 result[i] = (u32)read_csr(dd, ASIC_EEP_DATA); 95 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_NOP); /* close open page */ 96 } 97 98 /* 99 * Read length bytes starting at offset from the start of the EPROM. 100 */ 101 static int read_length(struct hfi1_devdata *dd, u32 start, u32 len, void *dest) 102 { 103 u32 buffer[EP_PAGE_DWORDS]; 104 u32 end; 105 u32 start_offset; 106 u32 read_start; 107 u32 bytes; 108 109 if (len == 0) 110 return 0; 111 112 end = start + len; 113 114 /* 115 * Make sure the read range is not outside of the controller read 116 * command address range. Note that '>' is correct below - the end 117 * of the range is OK if it stops at the limit, but no higher. 118 */ 119 if (end > (1 << CMD_SHIFT)) 120 return -EINVAL; 121 122 /* read the first partial page */ 123 start_offset = start & EP_PAGE_MASK; 124 if (start_offset) { 125 /* partial starting page */ 126 127 /* align and read the page that contains the start */ 128 read_start = start & ~EP_PAGE_MASK; 129 read_page(dd, read_start, buffer); 130 131 /* the rest of the page is available data */ 132 bytes = EP_PAGE_SIZE - start_offset; 133 134 if (len <= bytes) { 135 /* end is within this page */ 136 memcpy(dest, (u8 *)buffer + start_offset, len); 137 return 0; 138 } 139 140 memcpy(dest, (u8 *)buffer + start_offset, bytes); 141 142 start += bytes; 143 len -= bytes; 144 dest += bytes; 145 } 146 /* start is now page aligned */ 147 148 /* read whole pages */ 149 while (len >= EP_PAGE_SIZE) { 150 read_page(dd, start, buffer); 151 memcpy(dest, buffer, EP_PAGE_SIZE); 152 153 start += EP_PAGE_SIZE; 154 len -= EP_PAGE_SIZE; 155 dest += EP_PAGE_SIZE; 156 } 157 158 /* read the last partial page */ 159 if (len) { 160 read_page(dd, start, buffer); 161 memcpy(dest, buffer, len); 162 } 163 164 return 0; 165 } 166 167 /* 168 * Initialize the EPROM handler. 169 */ 170 int eprom_init(struct hfi1_devdata *dd) 171 { 172 int ret = 0; 173 174 /* only the discrete chip has an EPROM */ 175 if (dd->pcidev->device != PCI_DEVICE_ID_INTEL0) 176 return 0; 177 178 /* 179 * It is OK if both HFIs reset the EPROM as long as they don't 180 * do it at the same time. 181 */ 182 ret = acquire_chip_resource(dd, CR_EPROM, EPROM_TIMEOUT); 183 if (ret) { 184 dd_dev_err(dd, 185 "%s: unable to acquire EPROM resource, no EPROM support\n", 186 __func__); 187 goto done_asic; 188 } 189 190 /* reset EPROM to be sure it is in a good state */ 191 192 /* set reset */ 193 write_csr(dd, ASIC_EEP_CTL_STAT, ASIC_EEP_CTL_STAT_EP_RESET_SMASK); 194 /* clear reset, set speed */ 195 write_csr(dd, ASIC_EEP_CTL_STAT, 196 EP_SPEED_FULL << ASIC_EEP_CTL_STAT_RATE_SPI_SHIFT); 197 198 /* wake the device with command "release powerdown NoID" */ 199 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_RELEASE_POWERDOWN_NOID); 200 201 dd->eprom_available = true; 202 release_chip_resource(dd, CR_EPROM); 203 done_asic: 204 return ret; 205 } 206