1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 3 /* Authors: Cheng Xu <chengyou@linux.alibaba.com> */ 4 /* Kai Shen <kaishen@linux.alibaba.com> */ 5 /* Copyright (c) 2020-2022, Alibaba Group. */ 6 7 #include "erdma.h" 8 9 static void arm_cmdq_cq(struct erdma_cmdq *cmdq) 10 { 11 struct erdma_dev *dev = container_of(cmdq, struct erdma_dev, cmdq); 12 u64 db_data = FIELD_PREP(ERDMA_CQDB_CI_MASK, cmdq->cq.ci) | 13 FIELD_PREP(ERDMA_CQDB_ARM_MASK, 1) | 14 FIELD_PREP(ERDMA_CQDB_CMDSN_MASK, cmdq->cq.cmdsn) | 15 FIELD_PREP(ERDMA_CQDB_IDX_MASK, cmdq->cq.cmdsn); 16 17 *cmdq->cq.db_record = db_data; 18 writeq(db_data, dev->func_bar + ERDMA_CMDQ_CQDB_REG); 19 20 atomic64_inc(&cmdq->cq.armed_num); 21 } 22 23 static void kick_cmdq_db(struct erdma_cmdq *cmdq) 24 { 25 struct erdma_dev *dev = container_of(cmdq, struct erdma_dev, cmdq); 26 u64 db_data = FIELD_PREP(ERDMA_CMD_HDR_WQEBB_INDEX_MASK, cmdq->sq.pi); 27 28 *cmdq->sq.db_record = db_data; 29 writeq(db_data, dev->func_bar + ERDMA_CMDQ_SQDB_REG); 30 } 31 32 static struct erdma_comp_wait *get_comp_wait(struct erdma_cmdq *cmdq) 33 { 34 int comp_idx; 35 36 spin_lock(&cmdq->lock); 37 comp_idx = find_first_zero_bit(cmdq->comp_wait_bitmap, 38 cmdq->max_outstandings); 39 if (comp_idx == cmdq->max_outstandings) { 40 spin_unlock(&cmdq->lock); 41 return ERR_PTR(-ENOMEM); 42 } 43 44 __set_bit(comp_idx, cmdq->comp_wait_bitmap); 45 spin_unlock(&cmdq->lock); 46 47 return &cmdq->wait_pool[comp_idx]; 48 } 49 50 static void put_comp_wait(struct erdma_cmdq *cmdq, 51 struct erdma_comp_wait *comp_wait) 52 { 53 int used; 54 55 cmdq->wait_pool[comp_wait->ctx_id].cmd_status = ERDMA_CMD_STATUS_INIT; 56 spin_lock(&cmdq->lock); 57 used = __test_and_clear_bit(comp_wait->ctx_id, cmdq->comp_wait_bitmap); 58 spin_unlock(&cmdq->lock); 59 60 WARN_ON(!used); 61 } 62 63 static int erdma_cmdq_wait_res_init(struct erdma_dev *dev, 64 struct erdma_cmdq *cmdq) 65 { 66 int i; 67 68 cmdq->wait_pool = 69 devm_kcalloc(&dev->pdev->dev, cmdq->max_outstandings, 70 sizeof(struct erdma_comp_wait), GFP_KERNEL); 71 if (!cmdq->wait_pool) 72 return -ENOMEM; 73 74 spin_lock_init(&cmdq->lock); 75 cmdq->comp_wait_bitmap = devm_bitmap_zalloc( 76 &dev->pdev->dev, cmdq->max_outstandings, GFP_KERNEL); 77 if (!cmdq->comp_wait_bitmap) 78 return -ENOMEM; 79 80 for (i = 0; i < cmdq->max_outstandings; i++) { 81 init_completion(&cmdq->wait_pool[i].wait_event); 82 cmdq->wait_pool[i].ctx_id = i; 83 } 84 85 return 0; 86 } 87 88 static int erdma_cmdq_sq_init(struct erdma_dev *dev) 89 { 90 struct erdma_cmdq *cmdq = &dev->cmdq; 91 struct erdma_cmdq_sq *sq = &cmdq->sq; 92 u32 buf_size; 93 94 sq->wqebb_cnt = SQEBB_COUNT(ERDMA_CMDQ_SQE_SIZE); 95 sq->depth = cmdq->max_outstandings * sq->wqebb_cnt; 96 97 buf_size = sq->depth << SQEBB_SHIFT; 98 99 sq->qbuf = 100 dma_alloc_coherent(&dev->pdev->dev, WARPPED_BUFSIZE(buf_size), 101 &sq->qbuf_dma_addr, GFP_KERNEL); 102 if (!sq->qbuf) 103 return -ENOMEM; 104 105 sq->db_record = (u64 *)(sq->qbuf + buf_size); 106 107 spin_lock_init(&sq->lock); 108 109 erdma_reg_write32(dev, ERDMA_REGS_CMDQ_SQ_ADDR_H_REG, 110 upper_32_bits(sq->qbuf_dma_addr)); 111 erdma_reg_write32(dev, ERDMA_REGS_CMDQ_SQ_ADDR_L_REG, 112 lower_32_bits(sq->qbuf_dma_addr)); 113 erdma_reg_write32(dev, ERDMA_REGS_CMDQ_DEPTH_REG, sq->depth); 114 erdma_reg_write64(dev, ERDMA_CMDQ_SQ_DB_HOST_ADDR_REG, 115 sq->qbuf_dma_addr + buf_size); 116 117 return 0; 118 } 119 120 static int erdma_cmdq_cq_init(struct erdma_dev *dev) 121 { 122 struct erdma_cmdq *cmdq = &dev->cmdq; 123 struct erdma_cmdq_cq *cq = &cmdq->cq; 124 u32 buf_size; 125 126 cq->depth = cmdq->sq.depth; 127 buf_size = cq->depth << CQE_SHIFT; 128 129 cq->qbuf = 130 dma_alloc_coherent(&dev->pdev->dev, WARPPED_BUFSIZE(buf_size), 131 &cq->qbuf_dma_addr, GFP_KERNEL | __GFP_ZERO); 132 if (!cq->qbuf) 133 return -ENOMEM; 134 135 spin_lock_init(&cq->lock); 136 137 cq->db_record = (u64 *)(cq->qbuf + buf_size); 138 139 atomic64_set(&cq->armed_num, 0); 140 141 erdma_reg_write32(dev, ERDMA_REGS_CMDQ_CQ_ADDR_H_REG, 142 upper_32_bits(cq->qbuf_dma_addr)); 143 erdma_reg_write32(dev, ERDMA_REGS_CMDQ_CQ_ADDR_L_REG, 144 lower_32_bits(cq->qbuf_dma_addr)); 145 erdma_reg_write64(dev, ERDMA_CMDQ_CQ_DB_HOST_ADDR_REG, 146 cq->qbuf_dma_addr + buf_size); 147 148 return 0; 149 } 150 151 static int erdma_cmdq_eq_init(struct erdma_dev *dev) 152 { 153 struct erdma_cmdq *cmdq = &dev->cmdq; 154 struct erdma_eq *eq = &cmdq->eq; 155 u32 buf_size; 156 157 eq->depth = cmdq->max_outstandings; 158 buf_size = eq->depth << EQE_SHIFT; 159 160 eq->qbuf = 161 dma_alloc_coherent(&dev->pdev->dev, WARPPED_BUFSIZE(buf_size), 162 &eq->qbuf_dma_addr, GFP_KERNEL | __GFP_ZERO); 163 if (!eq->qbuf) 164 return -ENOMEM; 165 166 spin_lock_init(&eq->lock); 167 atomic64_set(&eq->event_num, 0); 168 169 eq->db = dev->func_bar + ERDMA_REGS_CEQ_DB_BASE_REG; 170 eq->db_record = (u64 *)(eq->qbuf + buf_size); 171 172 erdma_reg_write32(dev, ERDMA_REGS_CMDQ_EQ_ADDR_H_REG, 173 upper_32_bits(eq->qbuf_dma_addr)); 174 erdma_reg_write32(dev, ERDMA_REGS_CMDQ_EQ_ADDR_L_REG, 175 lower_32_bits(eq->qbuf_dma_addr)); 176 erdma_reg_write32(dev, ERDMA_REGS_CMDQ_EQ_DEPTH_REG, eq->depth); 177 erdma_reg_write64(dev, ERDMA_CMDQ_EQ_DB_HOST_ADDR_REG, 178 eq->qbuf_dma_addr + buf_size); 179 180 return 0; 181 } 182 183 int erdma_cmdq_init(struct erdma_dev *dev) 184 { 185 int err, i; 186 struct erdma_cmdq *cmdq = &dev->cmdq; 187 u32 sts, ctrl; 188 189 cmdq->max_outstandings = ERDMA_CMDQ_MAX_OUTSTANDING; 190 cmdq->use_event = false; 191 192 sema_init(&cmdq->credits, cmdq->max_outstandings); 193 194 err = erdma_cmdq_wait_res_init(dev, cmdq); 195 if (err) 196 return err; 197 198 err = erdma_cmdq_sq_init(dev); 199 if (err) 200 return err; 201 202 err = erdma_cmdq_cq_init(dev); 203 if (err) 204 goto err_destroy_sq; 205 206 err = erdma_cmdq_eq_init(dev); 207 if (err) 208 goto err_destroy_cq; 209 210 ctrl = FIELD_PREP(ERDMA_REG_DEV_CTRL_INIT_MASK, 1); 211 erdma_reg_write32(dev, ERDMA_REGS_DEV_CTRL_REG, ctrl); 212 213 for (i = 0; i < ERDMA_WAIT_DEV_DONE_CNT; i++) { 214 sts = erdma_reg_read32_filed(dev, ERDMA_REGS_DEV_ST_REG, 215 ERDMA_REG_DEV_ST_INIT_DONE_MASK); 216 if (sts) 217 break; 218 219 msleep(ERDMA_REG_ACCESS_WAIT_MS); 220 } 221 222 if (i == ERDMA_WAIT_DEV_DONE_CNT) { 223 dev_err(&dev->pdev->dev, "wait init done failed.\n"); 224 err = -ETIMEDOUT; 225 goto err_destroy_eq; 226 } 227 228 set_bit(ERDMA_CMDQ_STATE_OK_BIT, &cmdq->state); 229 230 return 0; 231 232 err_destroy_eq: 233 dma_free_coherent(&dev->pdev->dev, 234 (cmdq->eq.depth << EQE_SHIFT) + 235 ERDMA_EXTRA_BUFFER_SIZE, 236 cmdq->eq.qbuf, cmdq->eq.qbuf_dma_addr); 237 238 err_destroy_cq: 239 dma_free_coherent(&dev->pdev->dev, 240 (cmdq->cq.depth << CQE_SHIFT) + 241 ERDMA_EXTRA_BUFFER_SIZE, 242 cmdq->cq.qbuf, cmdq->cq.qbuf_dma_addr); 243 244 err_destroy_sq: 245 dma_free_coherent(&dev->pdev->dev, 246 (cmdq->sq.depth << SQEBB_SHIFT) + 247 ERDMA_EXTRA_BUFFER_SIZE, 248 cmdq->sq.qbuf, cmdq->sq.qbuf_dma_addr); 249 250 return err; 251 } 252 253 void erdma_finish_cmdq_init(struct erdma_dev *dev) 254 { 255 /* after device init successfully, change cmdq to event mode. */ 256 dev->cmdq.use_event = true; 257 arm_cmdq_cq(&dev->cmdq); 258 } 259 260 void erdma_cmdq_destroy(struct erdma_dev *dev) 261 { 262 struct erdma_cmdq *cmdq = &dev->cmdq; 263 264 clear_bit(ERDMA_CMDQ_STATE_OK_BIT, &cmdq->state); 265 266 dma_free_coherent(&dev->pdev->dev, 267 (cmdq->eq.depth << EQE_SHIFT) + 268 ERDMA_EXTRA_BUFFER_SIZE, 269 cmdq->eq.qbuf, cmdq->eq.qbuf_dma_addr); 270 dma_free_coherent(&dev->pdev->dev, 271 (cmdq->sq.depth << SQEBB_SHIFT) + 272 ERDMA_EXTRA_BUFFER_SIZE, 273 cmdq->sq.qbuf, cmdq->sq.qbuf_dma_addr); 274 dma_free_coherent(&dev->pdev->dev, 275 (cmdq->cq.depth << CQE_SHIFT) + 276 ERDMA_EXTRA_BUFFER_SIZE, 277 cmdq->cq.qbuf, cmdq->cq.qbuf_dma_addr); 278 } 279 280 static void *get_next_valid_cmdq_cqe(struct erdma_cmdq *cmdq) 281 { 282 __be32 *cqe = get_queue_entry(cmdq->cq.qbuf, cmdq->cq.ci, 283 cmdq->cq.depth, CQE_SHIFT); 284 u32 owner = FIELD_GET(ERDMA_CQE_HDR_OWNER_MASK, 285 be32_to_cpu(READ_ONCE(*cqe))); 286 287 return owner ^ !!(cmdq->cq.ci & cmdq->cq.depth) ? cqe : NULL; 288 } 289 290 static void push_cmdq_sqe(struct erdma_cmdq *cmdq, u64 *req, size_t req_len, 291 struct erdma_comp_wait *comp_wait) 292 { 293 __le64 *wqe; 294 u64 hdr = *req; 295 296 comp_wait->cmd_status = ERDMA_CMD_STATUS_ISSUED; 297 reinit_completion(&comp_wait->wait_event); 298 comp_wait->sq_pi = cmdq->sq.pi; 299 300 wqe = get_queue_entry(cmdq->sq.qbuf, cmdq->sq.pi, cmdq->sq.depth, 301 SQEBB_SHIFT); 302 memcpy(wqe, req, req_len); 303 304 cmdq->sq.pi += cmdq->sq.wqebb_cnt; 305 hdr |= FIELD_PREP(ERDMA_CMD_HDR_WQEBB_INDEX_MASK, cmdq->sq.pi) | 306 FIELD_PREP(ERDMA_CMD_HDR_CONTEXT_COOKIE_MASK, 307 comp_wait->ctx_id) | 308 FIELD_PREP(ERDMA_CMD_HDR_WQEBB_CNT_MASK, cmdq->sq.wqebb_cnt - 1); 309 *wqe = cpu_to_le64(hdr); 310 311 kick_cmdq_db(cmdq); 312 } 313 314 static int erdma_poll_single_cmd_completion(struct erdma_cmdq *cmdq) 315 { 316 struct erdma_comp_wait *comp_wait; 317 u32 hdr0, sqe_idx; 318 __be32 *cqe; 319 u16 ctx_id; 320 u64 *sqe; 321 322 cqe = get_next_valid_cmdq_cqe(cmdq); 323 if (!cqe) 324 return -EAGAIN; 325 326 cmdq->cq.ci++; 327 328 dma_rmb(); 329 hdr0 = be32_to_cpu(*cqe); 330 sqe_idx = be32_to_cpu(*(cqe + 1)); 331 332 sqe = get_queue_entry(cmdq->sq.qbuf, sqe_idx, cmdq->sq.depth, 333 SQEBB_SHIFT); 334 ctx_id = FIELD_GET(ERDMA_CMD_HDR_CONTEXT_COOKIE_MASK, *sqe); 335 comp_wait = &cmdq->wait_pool[ctx_id]; 336 if (comp_wait->cmd_status != ERDMA_CMD_STATUS_ISSUED) 337 return -EIO; 338 339 comp_wait->cmd_status = ERDMA_CMD_STATUS_FINISHED; 340 comp_wait->comp_status = FIELD_GET(ERDMA_CQE_HDR_SYNDROME_MASK, hdr0); 341 cmdq->sq.ci += cmdq->sq.wqebb_cnt; 342 /* Copy 16B comp data after cqe hdr to outer */ 343 be32_to_cpu_array(comp_wait->comp_data, cqe + 2, 4); 344 345 if (cmdq->use_event) 346 complete(&comp_wait->wait_event); 347 348 return 0; 349 } 350 351 static void erdma_polling_cmd_completions(struct erdma_cmdq *cmdq) 352 { 353 unsigned long flags; 354 u16 comp_num; 355 356 spin_lock_irqsave(&cmdq->cq.lock, flags); 357 358 /* We must have less than # of max_outstandings 359 * completions at one time. 360 */ 361 for (comp_num = 0; comp_num < cmdq->max_outstandings; comp_num++) 362 if (erdma_poll_single_cmd_completion(cmdq)) 363 break; 364 365 if (comp_num && cmdq->use_event) 366 arm_cmdq_cq(cmdq); 367 368 spin_unlock_irqrestore(&cmdq->cq.lock, flags); 369 } 370 371 void erdma_cmdq_completion_handler(struct erdma_cmdq *cmdq) 372 { 373 int got_event = 0; 374 375 if (!test_bit(ERDMA_CMDQ_STATE_OK_BIT, &cmdq->state) || 376 !cmdq->use_event) 377 return; 378 379 while (get_next_valid_eqe(&cmdq->eq)) { 380 cmdq->eq.ci++; 381 got_event++; 382 } 383 384 if (got_event) { 385 cmdq->cq.cmdsn++; 386 erdma_polling_cmd_completions(cmdq); 387 } 388 389 notify_eq(&cmdq->eq); 390 } 391 392 static int erdma_poll_cmd_completion(struct erdma_comp_wait *comp_ctx, 393 struct erdma_cmdq *cmdq, u32 timeout) 394 { 395 unsigned long comp_timeout = jiffies + msecs_to_jiffies(timeout); 396 397 while (1) { 398 erdma_polling_cmd_completions(cmdq); 399 if (comp_ctx->cmd_status != ERDMA_CMD_STATUS_ISSUED) 400 break; 401 402 if (time_is_before_jiffies(comp_timeout)) 403 return -ETIME; 404 405 msleep(20); 406 } 407 408 return 0; 409 } 410 411 static int erdma_wait_cmd_completion(struct erdma_comp_wait *comp_ctx, 412 struct erdma_cmdq *cmdq, u32 timeout) 413 { 414 unsigned long flags = 0; 415 416 wait_for_completion_timeout(&comp_ctx->wait_event, 417 msecs_to_jiffies(timeout)); 418 419 if (unlikely(comp_ctx->cmd_status != ERDMA_CMD_STATUS_FINISHED)) { 420 spin_lock_irqsave(&cmdq->cq.lock, flags); 421 comp_ctx->cmd_status = ERDMA_CMD_STATUS_TIMEOUT; 422 spin_unlock_irqrestore(&cmdq->cq.lock, flags); 423 return -ETIME; 424 } 425 426 return 0; 427 } 428 429 void erdma_cmdq_build_reqhdr(u64 *hdr, u32 mod, u32 op) 430 { 431 *hdr = FIELD_PREP(ERDMA_CMD_HDR_SUB_MOD_MASK, mod) | 432 FIELD_PREP(ERDMA_CMD_HDR_OPCODE_MASK, op); 433 } 434 435 int erdma_post_cmd_wait(struct erdma_cmdq *cmdq, void *req, u32 req_size, 436 u64 *resp0, u64 *resp1) 437 { 438 struct erdma_comp_wait *comp_wait; 439 int ret; 440 441 if (!test_bit(ERDMA_CMDQ_STATE_OK_BIT, &cmdq->state)) 442 return -ENODEV; 443 444 down(&cmdq->credits); 445 446 comp_wait = get_comp_wait(cmdq); 447 if (IS_ERR(comp_wait)) { 448 clear_bit(ERDMA_CMDQ_STATE_OK_BIT, &cmdq->state); 449 set_bit(ERDMA_CMDQ_STATE_CTX_ERR_BIT, &cmdq->state); 450 up(&cmdq->credits); 451 return PTR_ERR(comp_wait); 452 } 453 454 spin_lock(&cmdq->sq.lock); 455 push_cmdq_sqe(cmdq, req, req_size, comp_wait); 456 spin_unlock(&cmdq->sq.lock); 457 458 if (cmdq->use_event) 459 ret = erdma_wait_cmd_completion(comp_wait, cmdq, 460 ERDMA_CMDQ_TIMEOUT_MS); 461 else 462 ret = erdma_poll_cmd_completion(comp_wait, cmdq, 463 ERDMA_CMDQ_TIMEOUT_MS); 464 465 if (ret) { 466 set_bit(ERDMA_CMDQ_STATE_TIMEOUT_BIT, &cmdq->state); 467 clear_bit(ERDMA_CMDQ_STATE_OK_BIT, &cmdq->state); 468 goto out; 469 } 470 471 if (comp_wait->comp_status) 472 ret = -EIO; 473 474 if (resp0 && resp1) { 475 *resp0 = *((u64 *)&comp_wait->comp_data[0]); 476 *resp1 = *((u64 *)&comp_wait->comp_data[2]); 477 } 478 put_comp_wait(cmdq, comp_wait); 479 480 out: 481 up(&cmdq->credits); 482 483 return ret; 484 } 485