1 /* 2 * max30102.c - Support for MAX30102 heart rate and pulse oximeter sensor 3 * 4 * Copyright (C) 2017 Matt Ranostay <matt@ranostay.consulting> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * TODO: proximity power saving feature 17 */ 18 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/delay.h> 23 #include <linux/err.h> 24 #include <linux/irq.h> 25 #include <linux/i2c.h> 26 #include <linux/mutex.h> 27 #include <linux/of.h> 28 #include <linux/regmap.h> 29 #include <linux/iio/iio.h> 30 #include <linux/iio/buffer.h> 31 #include <linux/iio/kfifo_buf.h> 32 33 #define MAX30102_REGMAP_NAME "max30102_regmap" 34 #define MAX30102_DRV_NAME "max30102" 35 #define MAX30102_PART_NUMBER 0x15 36 37 #define MAX30102_REG_INT_STATUS 0x00 38 #define MAX30102_REG_INT_STATUS_PWR_RDY BIT(0) 39 #define MAX30102_REG_INT_STATUS_PROX_INT BIT(4) 40 #define MAX30102_REG_INT_STATUS_ALC_OVF BIT(5) 41 #define MAX30102_REG_INT_STATUS_PPG_RDY BIT(6) 42 #define MAX30102_REG_INT_STATUS_FIFO_RDY BIT(7) 43 44 #define MAX30102_REG_INT_ENABLE 0x02 45 #define MAX30102_REG_INT_ENABLE_PROX_INT_EN BIT(4) 46 #define MAX30102_REG_INT_ENABLE_ALC_OVF_EN BIT(5) 47 #define MAX30102_REG_INT_ENABLE_PPG_EN BIT(6) 48 #define MAX30102_REG_INT_ENABLE_FIFO_EN BIT(7) 49 #define MAX30102_REG_INT_ENABLE_MASK 0xf0 50 #define MAX30102_REG_INT_ENABLE_MASK_SHIFT 4 51 52 #define MAX30102_REG_FIFO_WR_PTR 0x04 53 #define MAX30102_REG_FIFO_OVR_CTR 0x05 54 #define MAX30102_REG_FIFO_RD_PTR 0x06 55 #define MAX30102_REG_FIFO_DATA 0x07 56 #define MAX30102_REG_FIFO_DATA_ENTRY_LEN 6 57 58 #define MAX30102_REG_FIFO_CONFIG 0x08 59 #define MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES BIT(1) 60 #define MAX30102_REG_FIFO_CONFIG_AVG_SHIFT 5 61 #define MAX30102_REG_FIFO_CONFIG_AFULL BIT(0) 62 63 #define MAX30102_REG_MODE_CONFIG 0x09 64 #define MAX30102_REG_MODE_CONFIG_MODE_HR 0x02 /* red LED */ 65 #define MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2 0x03 /* red + IR LED */ 66 #define MAX30102_REG_MODE_CONFIG_MODE_MULTI 0x07 /* multi-LED mode */ 67 #define MAX30102_REG_MODE_CONFIG_MODE_MASK GENMASK(2, 0) 68 #define MAX30102_REG_MODE_CONFIG_PWR BIT(7) 69 70 #define MAX30102_REG_SPO2_CONFIG 0x0a 71 #define MAX30102_REG_SPO2_CONFIG_PULSE_411_US 0x03 72 #define MAX30102_REG_SPO2_CONFIG_SR_400HZ 0x03 73 #define MAX30102_REG_SPO2_CONFIG_SR_MASK 0x07 74 #define MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT 2 75 #define MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS BIT(0) 76 #define MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT 5 77 78 #define MAX30102_REG_RED_LED_CONFIG 0x0c 79 #define MAX30102_REG_IR_LED_CONFIG 0x0d 80 81 #define MAX30102_REG_TEMP_CONFIG 0x21 82 #define MAX30102_REG_TEMP_CONFIG_TEMP_EN BIT(0) 83 84 #define MAX30102_REG_TEMP_INTEGER 0x1f 85 #define MAX30102_REG_TEMP_FRACTION 0x20 86 87 #define MAX30102_REG_REV_ID 0xfe 88 #define MAX30102_REG_PART_ID 0xff 89 90 struct max30102_data { 91 struct i2c_client *client; 92 struct iio_dev *indio_dev; 93 struct mutex lock; 94 struct regmap *regmap; 95 96 u8 buffer[8]; 97 __be32 processed_buffer[2]; /* 2 x 18-bit (padded to 32-bits) */ 98 }; 99 100 static const struct regmap_config max30102_regmap_config = { 101 .name = MAX30102_REGMAP_NAME, 102 103 .reg_bits = 8, 104 .val_bits = 8, 105 }; 106 107 static const unsigned long max30102_scan_masks[] = {0x3, 0}; 108 109 #define MAX30102_INTENSITY_CHANNEL(_si, _mod) { \ 110 .type = IIO_INTENSITY, \ 111 .channel2 = _mod, \ 112 .modified = 1, \ 113 .scan_index = _si, \ 114 .scan_type = { \ 115 .sign = 'u', \ 116 .shift = 8, \ 117 .realbits = 18, \ 118 .storagebits = 32, \ 119 .endianness = IIO_BE, \ 120 }, \ 121 } 122 123 static const struct iio_chan_spec max30102_channels[] = { 124 MAX30102_INTENSITY_CHANNEL(0, IIO_MOD_LIGHT_RED), 125 MAX30102_INTENSITY_CHANNEL(1, IIO_MOD_LIGHT_IR), 126 { 127 .type = IIO_TEMP, 128 .info_mask_separate = 129 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), 130 .scan_index = -1, 131 }, 132 }; 133 134 static int max30102_set_powermode(struct max30102_data *data, bool state) 135 { 136 return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG, 137 MAX30102_REG_MODE_CONFIG_PWR, 138 state ? 0 : MAX30102_REG_MODE_CONFIG_PWR); 139 } 140 141 static int max30102_buffer_postenable(struct iio_dev *indio_dev) 142 { 143 struct max30102_data *data = iio_priv(indio_dev); 144 145 return max30102_set_powermode(data, true); 146 } 147 148 static int max30102_buffer_predisable(struct iio_dev *indio_dev) 149 { 150 struct max30102_data *data = iio_priv(indio_dev); 151 152 return max30102_set_powermode(data, false); 153 } 154 155 static const struct iio_buffer_setup_ops max30102_buffer_setup_ops = { 156 .postenable = max30102_buffer_postenable, 157 .predisable = max30102_buffer_predisable, 158 }; 159 160 static inline int max30102_fifo_count(struct max30102_data *data) 161 { 162 unsigned int val; 163 int ret; 164 165 ret = regmap_read(data->regmap, MAX30102_REG_INT_STATUS, &val); 166 if (ret) 167 return ret; 168 169 /* FIFO has one sample slot left */ 170 if (val & MAX30102_REG_INT_STATUS_FIFO_RDY) 171 return 1; 172 173 return 0; 174 } 175 176 static int max30102_read_measurement(struct max30102_data *data) 177 { 178 int ret; 179 u8 *buffer = (u8 *) &data->buffer; 180 181 ret = i2c_smbus_read_i2c_block_data(data->client, 182 MAX30102_REG_FIFO_DATA, 183 MAX30102_REG_FIFO_DATA_ENTRY_LEN, 184 buffer); 185 186 memcpy(&data->processed_buffer[0], &buffer[0], 3); 187 memcpy(&data->processed_buffer[1], &buffer[3], 3); 188 189 return (ret == MAX30102_REG_FIFO_DATA_ENTRY_LEN) ? 0 : -EINVAL; 190 } 191 192 static irqreturn_t max30102_interrupt_handler(int irq, void *private) 193 { 194 struct iio_dev *indio_dev = private; 195 struct max30102_data *data = iio_priv(indio_dev); 196 int ret, cnt = 0; 197 198 mutex_lock(&data->lock); 199 200 while (cnt || (cnt = max30102_fifo_count(data)) > 0) { 201 ret = max30102_read_measurement(data); 202 if (ret) 203 break; 204 205 iio_push_to_buffers(data->indio_dev, data->processed_buffer); 206 cnt--; 207 } 208 209 mutex_unlock(&data->lock); 210 211 return IRQ_HANDLED; 212 } 213 214 static int max30102_get_current_idx(unsigned int val, int *reg) 215 { 216 /* each step is 0.200 mA */ 217 *reg = val / 200; 218 219 return *reg > 0xff ? -EINVAL : 0; 220 } 221 222 static int max30102_led_init(struct max30102_data *data) 223 { 224 struct device *dev = &data->client->dev; 225 struct device_node *np = dev->of_node; 226 unsigned int val; 227 int reg, ret; 228 229 ret = of_property_read_u32(np, "maxim,red-led-current-microamp", &val); 230 if (ret) { 231 dev_info(dev, "no red-led-current-microamp set\n"); 232 233 /* Default to 7 mA RED LED */ 234 val = 7000; 235 } 236 237 ret = max30102_get_current_idx(val, ®); 238 if (ret) { 239 dev_err(dev, "invalid RED LED current setting %d\n", val); 240 return ret; 241 } 242 243 ret = regmap_write(data->regmap, MAX30102_REG_RED_LED_CONFIG, reg); 244 if (ret) 245 return ret; 246 247 ret = of_property_read_u32(np, "maxim,ir-led-current-microamp", &val); 248 if (ret) { 249 dev_info(dev, "no ir-led-current-microamp set\n"); 250 251 /* Default to 7 mA IR LED */ 252 val = 7000; 253 } 254 255 ret = max30102_get_current_idx(val, ®); 256 if (ret) { 257 dev_err(dev, "invalid IR LED current setting %d\n", val); 258 return ret; 259 } 260 261 return regmap_write(data->regmap, MAX30102_REG_IR_LED_CONFIG, reg); 262 } 263 264 static int max30102_chip_init(struct max30102_data *data) 265 { 266 int ret; 267 268 /* setup LED current settings */ 269 ret = max30102_led_init(data); 270 if (ret) 271 return ret; 272 273 /* enable 18-bit HR + SPO2 readings at 400Hz */ 274 ret = regmap_write(data->regmap, MAX30102_REG_SPO2_CONFIG, 275 (MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS 276 << MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT) | 277 (MAX30102_REG_SPO2_CONFIG_SR_400HZ 278 << MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT) | 279 MAX30102_REG_SPO2_CONFIG_PULSE_411_US); 280 if (ret) 281 return ret; 282 283 /* enable HR + SPO2 mode */ 284 ret = regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG, 285 MAX30102_REG_MODE_CONFIG_MODE_MASK, 286 MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2); 287 if (ret) 288 return ret; 289 290 /* average 4 samples + generate FIFO interrupt */ 291 ret = regmap_write(data->regmap, MAX30102_REG_FIFO_CONFIG, 292 (MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES 293 << MAX30102_REG_FIFO_CONFIG_AVG_SHIFT) | 294 MAX30102_REG_FIFO_CONFIG_AFULL); 295 if (ret) 296 return ret; 297 298 /* enable FIFO interrupt */ 299 return regmap_update_bits(data->regmap, MAX30102_REG_INT_ENABLE, 300 MAX30102_REG_INT_ENABLE_MASK, 301 MAX30102_REG_INT_ENABLE_FIFO_EN); 302 } 303 304 static int max30102_read_temp(struct max30102_data *data, int *val) 305 { 306 int ret; 307 unsigned int reg; 308 309 ret = regmap_read(data->regmap, MAX30102_REG_TEMP_INTEGER, ®); 310 if (ret < 0) 311 return ret; 312 *val = reg << 4; 313 314 ret = regmap_read(data->regmap, MAX30102_REG_TEMP_FRACTION, ®); 315 if (ret < 0) 316 return ret; 317 318 *val |= reg & 0xf; 319 *val = sign_extend32(*val, 11); 320 321 return 0; 322 } 323 324 static int max30102_get_temp(struct max30102_data *data, int *val) 325 { 326 int ret; 327 328 /* start acquisition */ 329 ret = regmap_update_bits(data->regmap, MAX30102_REG_TEMP_CONFIG, 330 MAX30102_REG_TEMP_CONFIG_TEMP_EN, 331 MAX30102_REG_TEMP_CONFIG_TEMP_EN); 332 if (ret) 333 return ret; 334 335 msleep(35); 336 337 return max30102_read_temp(data, val); 338 } 339 340 static int max30102_read_raw(struct iio_dev *indio_dev, 341 struct iio_chan_spec const *chan, 342 int *val, int *val2, long mask) 343 { 344 struct max30102_data *data = iio_priv(indio_dev); 345 int ret = -EINVAL; 346 347 switch (mask) { 348 case IIO_CHAN_INFO_RAW: 349 /* 350 * Temperature reading can only be acquired while engine 351 * is running 352 */ 353 mutex_lock(&indio_dev->mlock); 354 355 if (!iio_buffer_enabled(indio_dev)) 356 ret = -EBUSY; 357 else { 358 ret = max30102_get_temp(data, val); 359 if (!ret) 360 ret = IIO_VAL_INT; 361 } 362 363 mutex_unlock(&indio_dev->mlock); 364 break; 365 case IIO_CHAN_INFO_SCALE: 366 *val = 1; /* 0.0625 */ 367 *val2 = 16; 368 ret = IIO_VAL_FRACTIONAL; 369 break; 370 } 371 372 return ret; 373 } 374 375 static const struct iio_info max30102_info = { 376 .read_raw = max30102_read_raw, 377 }; 378 379 static int max30102_probe(struct i2c_client *client, 380 const struct i2c_device_id *id) 381 { 382 struct max30102_data *data; 383 struct iio_buffer *buffer; 384 struct iio_dev *indio_dev; 385 int ret; 386 unsigned int reg; 387 388 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 389 if (!indio_dev) 390 return -ENOMEM; 391 392 buffer = devm_iio_kfifo_allocate(&client->dev); 393 if (!buffer) 394 return -ENOMEM; 395 396 iio_device_attach_buffer(indio_dev, buffer); 397 398 indio_dev->name = MAX30102_DRV_NAME; 399 indio_dev->channels = max30102_channels; 400 indio_dev->info = &max30102_info; 401 indio_dev->num_channels = ARRAY_SIZE(max30102_channels); 402 indio_dev->available_scan_masks = max30102_scan_masks; 403 indio_dev->modes = (INDIO_BUFFER_SOFTWARE | INDIO_DIRECT_MODE); 404 indio_dev->setup_ops = &max30102_buffer_setup_ops; 405 indio_dev->dev.parent = &client->dev; 406 407 data = iio_priv(indio_dev); 408 data->indio_dev = indio_dev; 409 data->client = client; 410 411 mutex_init(&data->lock); 412 i2c_set_clientdata(client, indio_dev); 413 414 data->regmap = devm_regmap_init_i2c(client, &max30102_regmap_config); 415 if (IS_ERR(data->regmap)) { 416 dev_err(&client->dev, "regmap initialization failed\n"); 417 return PTR_ERR(data->regmap); 418 } 419 420 /* check part ID */ 421 ret = regmap_read(data->regmap, MAX30102_REG_PART_ID, ®); 422 if (ret) 423 return ret; 424 if (reg != MAX30102_PART_NUMBER) 425 return -ENODEV; 426 427 /* show revision ID */ 428 ret = regmap_read(data->regmap, MAX30102_REG_REV_ID, ®); 429 if (ret) 430 return ret; 431 dev_dbg(&client->dev, "max3010x revision %02x\n", reg); 432 433 ret = max30102_set_powermode(data, false); 434 if (ret) 435 return ret; 436 437 ret = max30102_chip_init(data); 438 if (ret) 439 return ret; 440 441 if (client->irq <= 0) { 442 dev_err(&client->dev, "no valid irq defined\n"); 443 return -EINVAL; 444 } 445 446 ret = devm_request_threaded_irq(&client->dev, client->irq, 447 NULL, max30102_interrupt_handler, 448 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 449 "max30102_irq", indio_dev); 450 if (ret) { 451 dev_err(&client->dev, "request irq (%d) failed\n", client->irq); 452 return ret; 453 } 454 455 return iio_device_register(indio_dev); 456 } 457 458 static int max30102_remove(struct i2c_client *client) 459 { 460 struct iio_dev *indio_dev = i2c_get_clientdata(client); 461 struct max30102_data *data = iio_priv(indio_dev); 462 463 iio_device_unregister(indio_dev); 464 max30102_set_powermode(data, false); 465 466 return 0; 467 } 468 469 static const struct i2c_device_id max30102_id[] = { 470 { "max30102", 0 }, 471 {} 472 }; 473 MODULE_DEVICE_TABLE(i2c, max30102_id); 474 475 static const struct of_device_id max30102_dt_ids[] = { 476 { .compatible = "maxim,max30102" }, 477 { } 478 }; 479 MODULE_DEVICE_TABLE(of, max30102_dt_ids); 480 481 static struct i2c_driver max30102_driver = { 482 .driver = { 483 .name = MAX30102_DRV_NAME, 484 .of_match_table = of_match_ptr(max30102_dt_ids), 485 }, 486 .probe = max30102_probe, 487 .remove = max30102_remove, 488 .id_table = max30102_id, 489 }; 490 module_i2c_driver(max30102_driver); 491 492 MODULE_AUTHOR("Matt Ranostay <matt@ranostay.consulting>"); 493 MODULE_DESCRIPTION("MAX30102 heart rate and pulse oximeter sensor"); 494 MODULE_LICENSE("GPL"); 495