1 /* 2 * AFE4403 Heart Rate Monitors and Low-Cost Pulse Oximeters 3 * 4 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ 5 * Andrew F. Davis <afd@ti.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 */ 16 17 #include <linux/device.h> 18 #include <linux/err.h> 19 #include <linux/interrupt.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/regmap.h> 23 #include <linux/spi/spi.h> 24 #include <linux/sysfs.h> 25 #include <linux/regulator/consumer.h> 26 27 #include <linux/iio/iio.h> 28 #include <linux/iio/sysfs.h> 29 #include <linux/iio/buffer.h> 30 #include <linux/iio/trigger.h> 31 #include <linux/iio/triggered_buffer.h> 32 #include <linux/iio/trigger_consumer.h> 33 34 #include "afe440x.h" 35 36 #define AFE4403_DRIVER_NAME "afe4403" 37 38 /* AFE4403 Registers */ 39 #define AFE4403_TIAGAIN 0x20 40 #define AFE4403_TIA_AMB_GAIN 0x21 41 42 /* AFE4403 GAIN register fields */ 43 #define AFE4403_TIAGAIN_RES_MASK GENMASK(2, 0) 44 #define AFE4403_TIAGAIN_RES_SHIFT 0 45 #define AFE4403_TIAGAIN_CAP_MASK GENMASK(7, 3) 46 #define AFE4403_TIAGAIN_CAP_SHIFT 3 47 48 /* AFE4403 LEDCNTRL register fields */ 49 #define AFE440X_LEDCNTRL_LED1_MASK GENMASK(15, 8) 50 #define AFE440X_LEDCNTRL_LED1_SHIFT 8 51 #define AFE440X_LEDCNTRL_LED2_MASK GENMASK(7, 0) 52 #define AFE440X_LEDCNTRL_LED2_SHIFT 0 53 #define AFE440X_LEDCNTRL_LED_RANGE_MASK GENMASK(17, 16) 54 #define AFE440X_LEDCNTRL_LED_RANGE_SHIFT 16 55 56 /* AFE4403 CONTROL2 register fields */ 57 #define AFE440X_CONTROL2_PWR_DWN_TX BIT(2) 58 #define AFE440X_CONTROL2_EN_SLOW_DIAG BIT(8) 59 #define AFE440X_CONTROL2_DIAG_OUT_TRI BIT(10) 60 #define AFE440X_CONTROL2_TX_BRDG_MOD BIT(11) 61 #define AFE440X_CONTROL2_TX_REF_MASK GENMASK(18, 17) 62 #define AFE440X_CONTROL2_TX_REF_SHIFT 17 63 64 /* AFE4404 NULL fields */ 65 #define NULL_MASK 0 66 #define NULL_SHIFT 0 67 68 /* AFE4403 LEDCNTRL values */ 69 #define AFE440X_LEDCNTRL_RANGE_TX_HALF 0x1 70 #define AFE440X_LEDCNTRL_RANGE_TX_FULL 0x2 71 #define AFE440X_LEDCNTRL_RANGE_TX_OFF 0x3 72 73 /* AFE4403 CONTROL2 values */ 74 #define AFE440X_CONTROL2_TX_REF_025 0x0 75 #define AFE440X_CONTROL2_TX_REF_050 0x1 76 #define AFE440X_CONTROL2_TX_REF_100 0x2 77 #define AFE440X_CONTROL2_TX_REF_075 0x3 78 79 /* AFE4403 CONTROL3 values */ 80 #define AFE440X_CONTROL3_CLK_DIV_2 0x0 81 #define AFE440X_CONTROL3_CLK_DIV_4 0x2 82 #define AFE440X_CONTROL3_CLK_DIV_6 0x3 83 #define AFE440X_CONTROL3_CLK_DIV_8 0x4 84 #define AFE440X_CONTROL3_CLK_DIV_12 0x5 85 #define AFE440X_CONTROL3_CLK_DIV_1 0x7 86 87 /* AFE4403 TIAGAIN_CAP values */ 88 #define AFE4403_TIAGAIN_CAP_5_P 0x0 89 #define AFE4403_TIAGAIN_CAP_10_P 0x1 90 #define AFE4403_TIAGAIN_CAP_20_P 0x2 91 #define AFE4403_TIAGAIN_CAP_30_P 0x3 92 #define AFE4403_TIAGAIN_CAP_55_P 0x8 93 #define AFE4403_TIAGAIN_CAP_155_P 0x10 94 95 /* AFE4403 TIAGAIN_RES values */ 96 #define AFE4403_TIAGAIN_RES_500_K 0x0 97 #define AFE4403_TIAGAIN_RES_250_K 0x1 98 #define AFE4403_TIAGAIN_RES_100_K 0x2 99 #define AFE4403_TIAGAIN_RES_50_K 0x3 100 #define AFE4403_TIAGAIN_RES_25_K 0x4 101 #define AFE4403_TIAGAIN_RES_10_K 0x5 102 #define AFE4403_TIAGAIN_RES_1_M 0x6 103 #define AFE4403_TIAGAIN_RES_NONE 0x7 104 105 /** 106 * struct afe4403_data - AFE4403 device instance data 107 * @dev: Device structure 108 * @spi: SPI device handle 109 * @regmap: Register map of the device 110 * @regulator: Pointer to the regulator for the IC 111 * @trig: IIO trigger for this device 112 * @irq: ADC_RDY line interrupt number 113 */ 114 struct afe4403_data { 115 struct device *dev; 116 struct spi_device *spi; 117 struct regmap *regmap; 118 struct regulator *regulator; 119 struct iio_trigger *trig; 120 int irq; 121 }; 122 123 enum afe4403_chan_id { 124 LED1, 125 ALED1, 126 LED2, 127 ALED2, 128 LED1_ALED1, 129 LED2_ALED2, 130 ILED1, 131 ILED2, 132 }; 133 134 static const struct afe440x_reg_info afe4403_reg_info[] = { 135 [LED1] = AFE440X_REG_INFO(AFE440X_LED1VAL, 0, NULL), 136 [ALED1] = AFE440X_REG_INFO(AFE440X_ALED1VAL, 0, NULL), 137 [LED2] = AFE440X_REG_INFO(AFE440X_LED2VAL, 0, NULL), 138 [ALED2] = AFE440X_REG_INFO(AFE440X_ALED2VAL, 0, NULL), 139 [LED1_ALED1] = AFE440X_REG_INFO(AFE440X_LED1_ALED1VAL, 0, NULL), 140 [LED2_ALED2] = AFE440X_REG_INFO(AFE440X_LED2_ALED2VAL, 0, NULL), 141 [ILED1] = AFE440X_REG_INFO(AFE440X_LEDCNTRL, 0, AFE440X_LEDCNTRL_LED1), 142 [ILED2] = AFE440X_REG_INFO(AFE440X_LEDCNTRL, 0, AFE440X_LEDCNTRL_LED2), 143 }; 144 145 static const struct iio_chan_spec afe4403_channels[] = { 146 /* ADC values */ 147 AFE440X_INTENSITY_CHAN(LED1, "led1", 0), 148 AFE440X_INTENSITY_CHAN(ALED1, "led1_ambient", 0), 149 AFE440X_INTENSITY_CHAN(LED2, "led2", 0), 150 AFE440X_INTENSITY_CHAN(ALED2, "led2_ambient", 0), 151 AFE440X_INTENSITY_CHAN(LED1_ALED1, "led1-led1_ambient", 0), 152 AFE440X_INTENSITY_CHAN(LED2_ALED2, "led2-led2_ambient", 0), 153 /* LED current */ 154 AFE440X_CURRENT_CHAN(ILED1, "led1"), 155 AFE440X_CURRENT_CHAN(ILED2, "led2"), 156 }; 157 158 static const struct afe440x_val_table afe4403_res_table[] = { 159 { 500000 }, { 250000 }, { 100000 }, { 50000 }, 160 { 25000 }, { 10000 }, { 1000000 }, { 0 }, 161 }; 162 AFE440X_TABLE_ATTR(tia_resistance_available, afe4403_res_table); 163 164 static const struct afe440x_val_table afe4403_cap_table[] = { 165 { 0, 5000 }, { 0, 10000 }, { 0, 20000 }, { 0, 25000 }, 166 { 0, 30000 }, { 0, 35000 }, { 0, 45000 }, { 0, 50000 }, 167 { 0, 55000 }, { 0, 60000 }, { 0, 70000 }, { 0, 75000 }, 168 { 0, 80000 }, { 0, 85000 }, { 0, 95000 }, { 0, 100000 }, 169 { 0, 155000 }, { 0, 160000 }, { 0, 170000 }, { 0, 175000 }, 170 { 0, 180000 }, { 0, 185000 }, { 0, 195000 }, { 0, 200000 }, 171 { 0, 205000 }, { 0, 210000 }, { 0, 220000 }, { 0, 225000 }, 172 { 0, 230000 }, { 0, 235000 }, { 0, 245000 }, { 0, 250000 }, 173 }; 174 AFE440X_TABLE_ATTR(tia_capacitance_available, afe4403_cap_table); 175 176 static ssize_t afe440x_show_register(struct device *dev, 177 struct device_attribute *attr, 178 char *buf) 179 { 180 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 181 struct afe4403_data *afe = iio_priv(indio_dev); 182 struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr); 183 unsigned int reg_val; 184 int vals[2]; 185 int ret; 186 187 ret = regmap_read(afe->regmap, afe440x_attr->reg, ®_val); 188 if (ret) 189 return ret; 190 191 reg_val &= afe440x_attr->mask; 192 reg_val >>= afe440x_attr->shift; 193 194 if (reg_val >= afe440x_attr->table_size) 195 return -EINVAL; 196 197 vals[0] = afe440x_attr->val_table[reg_val].integer; 198 vals[1] = afe440x_attr->val_table[reg_val].fract; 199 200 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals); 201 } 202 203 static ssize_t afe440x_store_register(struct device *dev, 204 struct device_attribute *attr, 205 const char *buf, size_t count) 206 { 207 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 208 struct afe4403_data *afe = iio_priv(indio_dev); 209 struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr); 210 int val, integer, fract, ret; 211 212 ret = iio_str_to_fixpoint(buf, 100000, &integer, &fract); 213 if (ret) 214 return ret; 215 216 for (val = 0; val < afe440x_attr->table_size; val++) 217 if (afe440x_attr->val_table[val].integer == integer && 218 afe440x_attr->val_table[val].fract == fract) 219 break; 220 if (val == afe440x_attr->table_size) 221 return -EINVAL; 222 223 ret = regmap_update_bits(afe->regmap, afe440x_attr->reg, 224 afe440x_attr->mask, 225 (val << afe440x_attr->shift)); 226 if (ret) 227 return ret; 228 229 return count; 230 } 231 232 static AFE440X_ATTR(tia_resistance1, AFE4403_TIAGAIN, AFE4403_TIAGAIN_RES, afe4403_res_table); 233 static AFE440X_ATTR(tia_capacitance1, AFE4403_TIAGAIN, AFE4403_TIAGAIN_CAP, afe4403_cap_table); 234 235 static AFE440X_ATTR(tia_resistance2, AFE4403_TIA_AMB_GAIN, AFE4403_TIAGAIN_RES, afe4403_res_table); 236 static AFE440X_ATTR(tia_capacitance2, AFE4403_TIA_AMB_GAIN, AFE4403_TIAGAIN_RES, afe4403_cap_table); 237 238 static struct attribute *afe440x_attributes[] = { 239 &afe440x_attr_tia_resistance1.dev_attr.attr, 240 &afe440x_attr_tia_capacitance1.dev_attr.attr, 241 &afe440x_attr_tia_resistance2.dev_attr.attr, 242 &afe440x_attr_tia_capacitance2.dev_attr.attr, 243 &dev_attr_tia_resistance_available.attr, 244 &dev_attr_tia_capacitance_available.attr, 245 NULL 246 }; 247 248 static const struct attribute_group afe440x_attribute_group = { 249 .attrs = afe440x_attributes 250 }; 251 252 static int afe4403_read(struct afe4403_data *afe, unsigned int reg, u32 *val) 253 { 254 u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ}; 255 u8 rx[3]; 256 int ret; 257 258 /* Enable reading from the device */ 259 ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0); 260 if (ret) 261 return ret; 262 263 ret = spi_write_then_read(afe->spi, ®, 1, rx, 3); 264 if (ret) 265 return ret; 266 267 *val = (rx[0] << 16) | 268 (rx[1] << 8) | 269 (rx[2]); 270 271 /* Disable reading from the device */ 272 tx[3] = AFE440X_CONTROL0_WRITE; 273 ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0); 274 if (ret) 275 return ret; 276 277 return 0; 278 } 279 280 static int afe4403_read_raw(struct iio_dev *indio_dev, 281 struct iio_chan_spec const *chan, 282 int *val, int *val2, long mask) 283 { 284 struct afe4403_data *afe = iio_priv(indio_dev); 285 const struct afe440x_reg_info reg_info = afe4403_reg_info[chan->address]; 286 int ret; 287 288 switch (chan->type) { 289 case IIO_INTENSITY: 290 switch (mask) { 291 case IIO_CHAN_INFO_RAW: 292 ret = afe4403_read(afe, reg_info.reg, val); 293 if (ret) 294 return ret; 295 return IIO_VAL_INT; 296 case IIO_CHAN_INFO_OFFSET: 297 ret = regmap_read(afe->regmap, reg_info.offreg, 298 val); 299 if (ret) 300 return ret; 301 *val &= reg_info.mask; 302 *val >>= reg_info.shift; 303 return IIO_VAL_INT; 304 } 305 break; 306 case IIO_CURRENT: 307 switch (mask) { 308 case IIO_CHAN_INFO_RAW: 309 ret = regmap_read(afe->regmap, reg_info.reg, val); 310 if (ret) 311 return ret; 312 *val &= reg_info.mask; 313 *val >>= reg_info.shift; 314 return IIO_VAL_INT; 315 case IIO_CHAN_INFO_SCALE: 316 *val = 0; 317 *val2 = 800000; 318 return IIO_VAL_INT_PLUS_MICRO; 319 } 320 break; 321 default: 322 break; 323 } 324 325 return -EINVAL; 326 } 327 328 static int afe4403_write_raw(struct iio_dev *indio_dev, 329 struct iio_chan_spec const *chan, 330 int val, int val2, long mask) 331 { 332 struct afe4403_data *afe = iio_priv(indio_dev); 333 const struct afe440x_reg_info reg_info = afe4403_reg_info[chan->address]; 334 335 switch (chan->type) { 336 case IIO_INTENSITY: 337 switch (mask) { 338 case IIO_CHAN_INFO_OFFSET: 339 return regmap_update_bits(afe->regmap, 340 reg_info.offreg, 341 reg_info.mask, 342 (val << reg_info.shift)); 343 } 344 break; 345 case IIO_CURRENT: 346 switch (mask) { 347 case IIO_CHAN_INFO_RAW: 348 return regmap_update_bits(afe->regmap, 349 reg_info.reg, 350 reg_info.mask, 351 (val << reg_info.shift)); 352 } 353 break; 354 default: 355 break; 356 } 357 358 return -EINVAL; 359 } 360 361 static const struct iio_info afe4403_iio_info = { 362 .attrs = &afe440x_attribute_group, 363 .read_raw = afe4403_read_raw, 364 .write_raw = afe4403_write_raw, 365 .driver_module = THIS_MODULE, 366 }; 367 368 static irqreturn_t afe4403_trigger_handler(int irq, void *private) 369 { 370 struct iio_poll_func *pf = private; 371 struct iio_dev *indio_dev = pf->indio_dev; 372 struct afe4403_data *afe = iio_priv(indio_dev); 373 int ret, bit, i = 0; 374 s32 buffer[8]; 375 u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ}; 376 u8 rx[3]; 377 378 /* Enable reading from the device */ 379 ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0); 380 if (ret) 381 goto err; 382 383 for_each_set_bit(bit, indio_dev->active_scan_mask, 384 indio_dev->masklength) { 385 ret = spi_write_then_read(afe->spi, 386 &afe4403_reg_info[bit].reg, 1, 387 rx, 3); 388 if (ret) 389 goto err; 390 391 buffer[i++] = (rx[0] << 16) | 392 (rx[1] << 8) | 393 (rx[2]); 394 } 395 396 /* Disable reading from the device */ 397 tx[3] = AFE440X_CONTROL0_WRITE; 398 ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0); 399 if (ret) 400 goto err; 401 402 iio_push_to_buffers_with_timestamp(indio_dev, buffer, pf->timestamp); 403 err: 404 iio_trigger_notify_done(indio_dev->trig); 405 406 return IRQ_HANDLED; 407 } 408 409 static const struct iio_trigger_ops afe4403_trigger_ops = { 410 .owner = THIS_MODULE, 411 }; 412 413 #define AFE4403_TIMING_PAIRS \ 414 { AFE440X_LED2STC, 0x000050 }, \ 415 { AFE440X_LED2ENDC, 0x0003e7 }, \ 416 { AFE440X_LED1LEDSTC, 0x0007d0 }, \ 417 { AFE440X_LED1LEDENDC, 0x000bb7 }, \ 418 { AFE440X_ALED2STC, 0x000438 }, \ 419 { AFE440X_ALED2ENDC, 0x0007cf }, \ 420 { AFE440X_LED1STC, 0x000820 }, \ 421 { AFE440X_LED1ENDC, 0x000bb7 }, \ 422 { AFE440X_LED2LEDSTC, 0x000000 }, \ 423 { AFE440X_LED2LEDENDC, 0x0003e7 }, \ 424 { AFE440X_ALED1STC, 0x000c08 }, \ 425 { AFE440X_ALED1ENDC, 0x000f9f }, \ 426 { AFE440X_LED2CONVST, 0x0003ef }, \ 427 { AFE440X_LED2CONVEND, 0x0007cf }, \ 428 { AFE440X_ALED2CONVST, 0x0007d7 }, \ 429 { AFE440X_ALED2CONVEND, 0x000bb7 }, \ 430 { AFE440X_LED1CONVST, 0x000bbf }, \ 431 { AFE440X_LED1CONVEND, 0x009c3f }, \ 432 { AFE440X_ALED1CONVST, 0x000fa7 }, \ 433 { AFE440X_ALED1CONVEND, 0x001387 }, \ 434 { AFE440X_ADCRSTSTCT0, 0x0003e8 }, \ 435 { AFE440X_ADCRSTENDCT0, 0x0003eb }, \ 436 { AFE440X_ADCRSTSTCT1, 0x0007d0 }, \ 437 { AFE440X_ADCRSTENDCT1, 0x0007d3 }, \ 438 { AFE440X_ADCRSTSTCT2, 0x000bb8 }, \ 439 { AFE440X_ADCRSTENDCT2, 0x000bbb }, \ 440 { AFE440X_ADCRSTSTCT3, 0x000fa0 }, \ 441 { AFE440X_ADCRSTENDCT3, 0x000fa3 }, \ 442 { AFE440X_PRPCOUNT, 0x009c3f }, \ 443 { AFE440X_PDNCYCLESTC, 0x001518 }, \ 444 { AFE440X_PDNCYCLEENDC, 0x00991f } 445 446 static const struct reg_sequence afe4403_reg_sequences[] = { 447 AFE4403_TIMING_PAIRS, 448 { AFE440X_CONTROL1, AFE440X_CONTROL1_TIMEREN }, 449 { AFE4403_TIAGAIN, AFE440X_TIAGAIN_ENSEPGAIN }, 450 }; 451 452 static const struct regmap_range afe4403_yes_ranges[] = { 453 regmap_reg_range(AFE440X_LED2VAL, AFE440X_LED1_ALED1VAL), 454 }; 455 456 static const struct regmap_access_table afe4403_volatile_table = { 457 .yes_ranges = afe4403_yes_ranges, 458 .n_yes_ranges = ARRAY_SIZE(afe4403_yes_ranges), 459 }; 460 461 static const struct regmap_config afe4403_regmap_config = { 462 .reg_bits = 8, 463 .val_bits = 24, 464 465 .max_register = AFE440X_PDNCYCLEENDC, 466 .cache_type = REGCACHE_RBTREE, 467 .volatile_table = &afe4403_volatile_table, 468 }; 469 470 static const struct of_device_id afe4403_of_match[] = { 471 { .compatible = "ti,afe4403", }, 472 { /* sentinel */ } 473 }; 474 MODULE_DEVICE_TABLE(of, afe4403_of_match); 475 476 static int __maybe_unused afe4403_suspend(struct device *dev) 477 { 478 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 479 struct afe4403_data *afe = iio_priv(indio_dev); 480 int ret; 481 482 ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2, 483 AFE440X_CONTROL2_PDN_AFE, 484 AFE440X_CONTROL2_PDN_AFE); 485 if (ret) 486 return ret; 487 488 ret = regulator_disable(afe->regulator); 489 if (ret) { 490 dev_err(dev, "Unable to disable regulator\n"); 491 return ret; 492 } 493 494 return 0; 495 } 496 497 static int __maybe_unused afe4403_resume(struct device *dev) 498 { 499 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 500 struct afe4403_data *afe = iio_priv(indio_dev); 501 int ret; 502 503 ret = regulator_enable(afe->regulator); 504 if (ret) { 505 dev_err(dev, "Unable to enable regulator\n"); 506 return ret; 507 } 508 509 ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2, 510 AFE440X_CONTROL2_PDN_AFE, 0); 511 if (ret) 512 return ret; 513 514 return 0; 515 } 516 517 static SIMPLE_DEV_PM_OPS(afe4403_pm_ops, afe4403_suspend, afe4403_resume); 518 519 static int afe4403_probe(struct spi_device *spi) 520 { 521 struct iio_dev *indio_dev; 522 struct afe4403_data *afe; 523 int ret; 524 525 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*afe)); 526 if (!indio_dev) 527 return -ENOMEM; 528 529 afe = iio_priv(indio_dev); 530 spi_set_drvdata(spi, indio_dev); 531 532 afe->dev = &spi->dev; 533 afe->spi = spi; 534 afe->irq = spi->irq; 535 536 afe->regmap = devm_regmap_init_spi(spi, &afe4403_regmap_config); 537 if (IS_ERR(afe->regmap)) { 538 dev_err(afe->dev, "Unable to allocate register map\n"); 539 return PTR_ERR(afe->regmap); 540 } 541 542 afe->regulator = devm_regulator_get(afe->dev, "tx_sup"); 543 if (IS_ERR(afe->regulator)) { 544 dev_err(afe->dev, "Unable to get regulator\n"); 545 return PTR_ERR(afe->regulator); 546 } 547 ret = regulator_enable(afe->regulator); 548 if (ret) { 549 dev_err(afe->dev, "Unable to enable regulator\n"); 550 return ret; 551 } 552 553 ret = regmap_write(afe->regmap, AFE440X_CONTROL0, 554 AFE440X_CONTROL0_SW_RESET); 555 if (ret) { 556 dev_err(afe->dev, "Unable to reset device\n"); 557 goto err_disable_reg; 558 } 559 560 ret = regmap_multi_reg_write(afe->regmap, afe4403_reg_sequences, 561 ARRAY_SIZE(afe4403_reg_sequences)); 562 if (ret) { 563 dev_err(afe->dev, "Unable to set register defaults\n"); 564 goto err_disable_reg; 565 } 566 567 indio_dev->modes = INDIO_DIRECT_MODE; 568 indio_dev->dev.parent = afe->dev; 569 indio_dev->channels = afe4403_channels; 570 indio_dev->num_channels = ARRAY_SIZE(afe4403_channels); 571 indio_dev->name = AFE4403_DRIVER_NAME; 572 indio_dev->info = &afe4403_iio_info; 573 574 if (afe->irq > 0) { 575 afe->trig = devm_iio_trigger_alloc(afe->dev, 576 "%s-dev%d", 577 indio_dev->name, 578 indio_dev->id); 579 if (!afe->trig) { 580 dev_err(afe->dev, "Unable to allocate IIO trigger\n"); 581 ret = -ENOMEM; 582 goto err_disable_reg; 583 } 584 585 iio_trigger_set_drvdata(afe->trig, indio_dev); 586 587 afe->trig->ops = &afe4403_trigger_ops; 588 afe->trig->dev.parent = afe->dev; 589 590 ret = iio_trigger_register(afe->trig); 591 if (ret) { 592 dev_err(afe->dev, "Unable to register IIO trigger\n"); 593 goto err_disable_reg; 594 } 595 596 ret = devm_request_threaded_irq(afe->dev, afe->irq, 597 iio_trigger_generic_data_rdy_poll, 598 NULL, IRQF_ONESHOT, 599 AFE4403_DRIVER_NAME, 600 afe->trig); 601 if (ret) { 602 dev_err(afe->dev, "Unable to request IRQ\n"); 603 goto err_trig; 604 } 605 } 606 607 ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time, 608 afe4403_trigger_handler, NULL); 609 if (ret) { 610 dev_err(afe->dev, "Unable to setup buffer\n"); 611 goto err_trig; 612 } 613 614 ret = iio_device_register(indio_dev); 615 if (ret) { 616 dev_err(afe->dev, "Unable to register IIO device\n"); 617 goto err_buff; 618 } 619 620 return 0; 621 622 err_buff: 623 iio_triggered_buffer_cleanup(indio_dev); 624 err_trig: 625 if (afe->irq > 0) 626 iio_trigger_unregister(afe->trig); 627 err_disable_reg: 628 regulator_disable(afe->regulator); 629 630 return ret; 631 } 632 633 static int afe4403_remove(struct spi_device *spi) 634 { 635 struct iio_dev *indio_dev = spi_get_drvdata(spi); 636 struct afe4403_data *afe = iio_priv(indio_dev); 637 int ret; 638 639 iio_device_unregister(indio_dev); 640 641 iio_triggered_buffer_cleanup(indio_dev); 642 643 if (afe->irq > 0) 644 iio_trigger_unregister(afe->trig); 645 646 ret = regulator_disable(afe->regulator); 647 if (ret) { 648 dev_err(afe->dev, "Unable to disable regulator\n"); 649 return ret; 650 } 651 652 return 0; 653 } 654 655 static const struct spi_device_id afe4403_ids[] = { 656 { "afe4403", 0 }, 657 { /* sentinel */ } 658 }; 659 MODULE_DEVICE_TABLE(spi, afe4403_ids); 660 661 static struct spi_driver afe4403_spi_driver = { 662 .driver = { 663 .name = AFE4403_DRIVER_NAME, 664 .of_match_table = afe4403_of_match, 665 .pm = &afe4403_pm_ops, 666 }, 667 .probe = afe4403_probe, 668 .remove = afe4403_remove, 669 .id_table = afe4403_ids, 670 }; 671 module_spi_driver(afe4403_spi_driver); 672 673 MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>"); 674 MODULE_DESCRIPTION("TI AFE4403 Heart Rate Monitor and Pulse Oximeter AFE"); 675 MODULE_LICENSE("GPL v2"); 676