12985a5d8SStefan Popa // SPDX-License-Identifier: GPL-2.0
22985a5d8SStefan Popa /*
32985a5d8SStefan Popa * AD7606 SPI ADC driver
42985a5d8SStefan Popa *
52985a5d8SStefan Popa * Copyright 2011 Analog Devices Inc.
62985a5d8SStefan Popa */
72985a5d8SStefan Popa
82985a5d8SStefan Popa #include <linux/delay.h>
92985a5d8SStefan Popa #include <linux/device.h>
102985a5d8SStefan Popa #include <linux/err.h>
112985a5d8SStefan Popa #include <linux/gpio/consumer.h>
122985a5d8SStefan Popa #include <linux/interrupt.h>
132985a5d8SStefan Popa #include <linux/kernel.h>
142985a5d8SStefan Popa #include <linux/module.h>
15ae3babe1SNuno Sá #include <linux/property.h>
162985a5d8SStefan Popa #include <linux/regulator/consumer.h>
172985a5d8SStefan Popa #include <linux/sched.h>
182985a5d8SStefan Popa #include <linux/slab.h>
192985a5d8SStefan Popa #include <linux/sysfs.h>
202985a5d8SStefan Popa #include <linux/util_macros.h>
212985a5d8SStefan Popa
222985a5d8SStefan Popa #include <linux/iio/iio.h>
232985a5d8SStefan Popa #include <linux/iio/buffer.h>
242985a5d8SStefan Popa #include <linux/iio/sysfs.h>
252985a5d8SStefan Popa #include <linux/iio/trigger.h>
262985a5d8SStefan Popa #include <linux/iio/triggered_buffer.h>
272985a5d8SStefan Popa #include <linux/iio/trigger_consumer.h>
282985a5d8SStefan Popa
292985a5d8SStefan Popa #include "ad7606.h"
302985a5d8SStefan Popa
312985a5d8SStefan Popa /*
322985a5d8SStefan Popa * Scales are computed as 5000/32768 and 10000/32768 respectively,
332985a5d8SStefan Popa * so that when applied to the raw values they provide mV values
342985a5d8SStefan Popa */
356bf229abSStefan Popa static const unsigned int ad7606_scale_avail[2] = {
362985a5d8SStefan Popa 152588, 305176
372985a5d8SStefan Popa };
382985a5d8SStefan Popa
39f2a22e1eSBeniamin Bia
40f2a22e1eSBeniamin Bia static const unsigned int ad7616_sw_scale_avail[3] = {
41f2a22e1eSBeniamin Bia 76293, 152588, 305176
42f2a22e1eSBeniamin Bia };
43f2a22e1eSBeniamin Bia
442985a5d8SStefan Popa static const unsigned int ad7606_oversampling_avail[7] = {
452985a5d8SStefan Popa 1, 2, 4, 8, 16, 32, 64,
462985a5d8SStefan Popa };
472985a5d8SStefan Popa
487989b4bbSBeniamin Bia static const unsigned int ad7616_oversampling_avail[8] = {
497989b4bbSBeniamin Bia 1, 2, 4, 8, 16, 32, 64, 128,
507989b4bbSBeniamin Bia };
517989b4bbSBeniamin Bia
ad7606_reset(struct ad7606_state * st)5266d0d59aSGuillaume Stols int ad7606_reset(struct ad7606_state *st)
532985a5d8SStefan Popa {
542985a5d8SStefan Popa if (st->gpio_reset) {
552985a5d8SStefan Popa gpiod_set_value(st->gpio_reset, 1);
562985a5d8SStefan Popa ndelay(100); /* t_reset >= 100ns */
572985a5d8SStefan Popa gpiod_set_value(st->gpio_reset, 0);
582985a5d8SStefan Popa return 0;
592985a5d8SStefan Popa }
602985a5d8SStefan Popa
612985a5d8SStefan Popa return -ENODEV;
622985a5d8SStefan Popa }
6366d0d59aSGuillaume Stols EXPORT_SYMBOL_NS_GPL(ad7606_reset, IIO_AD7606);
642985a5d8SStefan Popa
ad7606_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)65a444fa59SBeniamin Bia static int ad7606_reg_access(struct iio_dev *indio_dev,
66a444fa59SBeniamin Bia unsigned int reg,
67a444fa59SBeniamin Bia unsigned int writeval,
68a444fa59SBeniamin Bia unsigned int *readval)
69a444fa59SBeniamin Bia {
70a444fa59SBeniamin Bia struct ad7606_state *st = iio_priv(indio_dev);
71a444fa59SBeniamin Bia int ret;
72a444fa59SBeniamin Bia
73a444fa59SBeniamin Bia mutex_lock(&st->lock);
74a444fa59SBeniamin Bia if (readval) {
75a444fa59SBeniamin Bia ret = st->bops->reg_read(st, reg);
76a444fa59SBeniamin Bia if (ret < 0)
77a444fa59SBeniamin Bia goto err_unlock;
78a444fa59SBeniamin Bia *readval = ret;
79a444fa59SBeniamin Bia ret = 0;
80a444fa59SBeniamin Bia } else {
81a444fa59SBeniamin Bia ret = st->bops->reg_write(st, reg, writeval);
82a444fa59SBeniamin Bia }
83a444fa59SBeniamin Bia err_unlock:
84a444fa59SBeniamin Bia mutex_unlock(&st->lock);
85a444fa59SBeniamin Bia return ret;
86a444fa59SBeniamin Bia }
87a444fa59SBeniamin Bia
ad7606_read_samples(struct ad7606_state * st)882985a5d8SStefan Popa static int ad7606_read_samples(struct ad7606_state *st)
892985a5d8SStefan Popa {
90341826a0SBeniamin Bia unsigned int num = st->chip_info->num_channels - 1;
912985a5d8SStefan Popa u16 *data = st->data;
922985a5d8SStefan Popa
932985a5d8SStefan Popa return st->bops->read_block(st->dev, num, data);
942985a5d8SStefan Popa }
952985a5d8SStefan Popa
ad7606_trigger_handler(int irq,void * p)962985a5d8SStefan Popa static irqreturn_t ad7606_trigger_handler(int irq, void *p)
972985a5d8SStefan Popa {
982985a5d8SStefan Popa struct iio_poll_func *pf = p;
992985a5d8SStefan Popa struct iio_dev *indio_dev = pf->indio_dev;
1002985a5d8SStefan Popa struct ad7606_state *st = iio_priv(indio_dev);
1012985a5d8SStefan Popa int ret;
1022985a5d8SStefan Popa
1032985a5d8SStefan Popa mutex_lock(&st->lock);
1042985a5d8SStefan Popa
1052985a5d8SStefan Popa ret = ad7606_read_samples(st);
1062985a5d8SStefan Popa if (ret == 0)
1072985a5d8SStefan Popa iio_push_to_buffers_with_timestamp(indio_dev, st->data,
1082985a5d8SStefan Popa iio_get_time_ns(indio_dev));
1092985a5d8SStefan Popa
1102985a5d8SStefan Popa iio_trigger_notify_done(indio_dev->trig);
1112985a5d8SStefan Popa /* The rising edge of the CONVST signal starts a new conversion. */
1122985a5d8SStefan Popa gpiod_set_value(st->gpio_convst, 1);
1132985a5d8SStefan Popa
1142985a5d8SStefan Popa mutex_unlock(&st->lock);
1152985a5d8SStefan Popa
1162985a5d8SStefan Popa return IRQ_HANDLED;
1172985a5d8SStefan Popa }
1182985a5d8SStefan Popa
ad7606_scan_direct(struct iio_dev * indio_dev,unsigned int ch)1192985a5d8SStefan Popa static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch)
1202985a5d8SStefan Popa {
1212985a5d8SStefan Popa struct ad7606_state *st = iio_priv(indio_dev);
1222985a5d8SStefan Popa int ret;
1232985a5d8SStefan Popa
1242985a5d8SStefan Popa gpiod_set_value(st->gpio_convst, 1);
1252985a5d8SStefan Popa ret = wait_for_completion_timeout(&st->completion,
1262985a5d8SStefan Popa msecs_to_jiffies(1000));
1272985a5d8SStefan Popa if (!ret) {
1282985a5d8SStefan Popa ret = -ETIMEDOUT;
1292985a5d8SStefan Popa goto error_ret;
1302985a5d8SStefan Popa }
1312985a5d8SStefan Popa
1322985a5d8SStefan Popa ret = ad7606_read_samples(st);
1332985a5d8SStefan Popa if (ret == 0)
1342985a5d8SStefan Popa ret = st->data[ch];
1352985a5d8SStefan Popa
1362985a5d8SStefan Popa error_ret:
1372985a5d8SStefan Popa gpiod_set_value(st->gpio_convst, 0);
1382985a5d8SStefan Popa
1392985a5d8SStefan Popa return ret;
1402985a5d8SStefan Popa }
1412985a5d8SStefan Popa
ad7606_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)1422985a5d8SStefan Popa static int ad7606_read_raw(struct iio_dev *indio_dev,
1432985a5d8SStefan Popa struct iio_chan_spec const *chan,
1442985a5d8SStefan Popa int *val,
1452985a5d8SStefan Popa int *val2,
1462985a5d8SStefan Popa long m)
1472985a5d8SStefan Popa {
1483c23e9e8SBeniamin Bia int ret, ch = 0;
1492985a5d8SStefan Popa struct ad7606_state *st = iio_priv(indio_dev);
1502985a5d8SStefan Popa
1512985a5d8SStefan Popa switch (m) {
1522985a5d8SStefan Popa case IIO_CHAN_INFO_RAW:
1532985a5d8SStefan Popa ret = iio_device_claim_direct_mode(indio_dev);
1542985a5d8SStefan Popa if (ret)
1552985a5d8SStefan Popa return ret;
1562985a5d8SStefan Popa
1572985a5d8SStefan Popa ret = ad7606_scan_direct(indio_dev, chan->address);
1582985a5d8SStefan Popa iio_device_release_direct_mode(indio_dev);
1592985a5d8SStefan Popa
1602985a5d8SStefan Popa if (ret < 0)
1612985a5d8SStefan Popa return ret;
1622985a5d8SStefan Popa *val = (short)ret;
1632985a5d8SStefan Popa return IIO_VAL_INT;
1642985a5d8SStefan Popa case IIO_CHAN_INFO_SCALE:
1653c23e9e8SBeniamin Bia if (st->sw_mode_en)
1663c23e9e8SBeniamin Bia ch = chan->address;
1672985a5d8SStefan Popa *val = 0;
1683c23e9e8SBeniamin Bia *val2 = st->scale_avail[st->range[ch]];
1692985a5d8SStefan Popa return IIO_VAL_INT_PLUS_MICRO;
1702985a5d8SStefan Popa case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1712985a5d8SStefan Popa *val = st->oversampling;
1722985a5d8SStefan Popa return IIO_VAL_INT;
1732985a5d8SStefan Popa }
1742985a5d8SStefan Popa return -EINVAL;
1752985a5d8SStefan Popa }
1762985a5d8SStefan Popa
ad7606_show_avail(char * buf,const unsigned int * vals,unsigned int n,bool micros)1776bf229abSStefan Popa static ssize_t ad7606_show_avail(char *buf, const unsigned int *vals,
1786bf229abSStefan Popa unsigned int n, bool micros)
1796bf229abSStefan Popa {
1806bf229abSStefan Popa size_t len = 0;
1816bf229abSStefan Popa int i;
1826bf229abSStefan Popa
1836bf229abSStefan Popa for (i = 0; i < n; i++) {
1846bf229abSStefan Popa len += scnprintf(buf + len, PAGE_SIZE - len,
1856bf229abSStefan Popa micros ? "0.%06u " : "%u ", vals[i]);
1866bf229abSStefan Popa }
1876bf229abSStefan Popa buf[len - 1] = '\n';
1886bf229abSStefan Popa
1896bf229abSStefan Popa return len;
1906bf229abSStefan Popa }
1916bf229abSStefan Popa
in_voltage_scale_available_show(struct device * dev,struct device_attribute * attr,char * buf)1922985a5d8SStefan Popa static ssize_t in_voltage_scale_available_show(struct device *dev,
1932985a5d8SStefan Popa struct device_attribute *attr,
1942985a5d8SStefan Popa char *buf)
1952985a5d8SStefan Popa {
1966bf229abSStefan Popa struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1976bf229abSStefan Popa struct ad7606_state *st = iio_priv(indio_dev);
1982985a5d8SStefan Popa
1996bf229abSStefan Popa return ad7606_show_avail(buf, st->scale_avail, st->num_scales, true);
2002985a5d8SStefan Popa }
2012985a5d8SStefan Popa
2022985a5d8SStefan Popa static IIO_DEVICE_ATTR_RO(in_voltage_scale_available, 0);
2032985a5d8SStefan Popa
ad7606_write_scale_hw(struct iio_dev * indio_dev,int ch,int val)20488dd0313SBeniamin Bia static int ad7606_write_scale_hw(struct iio_dev *indio_dev, int ch, int val)
20588dd0313SBeniamin Bia {
20688dd0313SBeniamin Bia struct ad7606_state *st = iio_priv(indio_dev);
20788dd0313SBeniamin Bia
20888dd0313SBeniamin Bia gpiod_set_value(st->gpio_range, val);
20988dd0313SBeniamin Bia
21088dd0313SBeniamin Bia return 0;
21188dd0313SBeniamin Bia }
21288dd0313SBeniamin Bia
ad7606_write_os_hw(struct iio_dev * indio_dev,int val)21388dd0313SBeniamin Bia static int ad7606_write_os_hw(struct iio_dev *indio_dev, int val)
21488dd0313SBeniamin Bia {
21588dd0313SBeniamin Bia struct ad7606_state *st = iio_priv(indio_dev);
21688dd0313SBeniamin Bia DECLARE_BITMAP(values, 3);
21788dd0313SBeniamin Bia
21848617707SGuillaume Stols values[0] = val & GENMASK(2, 0);
21988dd0313SBeniamin Bia
22048617707SGuillaume Stols gpiod_set_array_value(st->gpio_os->ndescs, st->gpio_os->desc,
22188dd0313SBeniamin Bia st->gpio_os->info, values);
22288dd0313SBeniamin Bia
22388dd0313SBeniamin Bia /* AD7616 requires a reset to update value */
22488dd0313SBeniamin Bia if (st->chip_info->os_req_reset)
22588dd0313SBeniamin Bia ad7606_reset(st);
22688dd0313SBeniamin Bia
22788dd0313SBeniamin Bia return 0;
22888dd0313SBeniamin Bia }
22988dd0313SBeniamin Bia
ad7606_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)2302985a5d8SStefan Popa static int ad7606_write_raw(struct iio_dev *indio_dev,
2312985a5d8SStefan Popa struct iio_chan_spec const *chan,
2322985a5d8SStefan Popa int val,
2332985a5d8SStefan Popa int val2,
2342985a5d8SStefan Popa long mask)
2352985a5d8SStefan Popa {
2362985a5d8SStefan Popa struct ad7606_state *st = iio_priv(indio_dev);
23788dd0313SBeniamin Bia int i, ret, ch = 0;
2382985a5d8SStefan Popa
2392985a5d8SStefan Popa switch (mask) {
2402985a5d8SStefan Popa case IIO_CHAN_INFO_SCALE:
2412985a5d8SStefan Popa mutex_lock(&st->lock);
2426bf229abSStefan Popa i = find_closest(val2, st->scale_avail, st->num_scales);
2433c23e9e8SBeniamin Bia if (st->sw_mode_en)
2443c23e9e8SBeniamin Bia ch = chan->address;
2453c23e9e8SBeniamin Bia ret = st->write_scale(indio_dev, ch, i);
24688dd0313SBeniamin Bia if (ret < 0) {
24788dd0313SBeniamin Bia mutex_unlock(&st->lock);
24888dd0313SBeniamin Bia return ret;
24988dd0313SBeniamin Bia }
25088dd0313SBeniamin Bia st->range[ch] = i;
2512985a5d8SStefan Popa mutex_unlock(&st->lock);
2522985a5d8SStefan Popa
2532985a5d8SStefan Popa return 0;
2542985a5d8SStefan Popa case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
2552985a5d8SStefan Popa if (val2)
2562985a5d8SStefan Popa return -EINVAL;
2576bf229abSStefan Popa i = find_closest(val, st->oversampling_avail,
2586bf229abSStefan Popa st->num_os_ratios);
2592985a5d8SStefan Popa mutex_lock(&st->lock);
26088dd0313SBeniamin Bia ret = st->write_os(indio_dev, i);
26188dd0313SBeniamin Bia if (ret < 0) {
26288dd0313SBeniamin Bia mutex_unlock(&st->lock);
26388dd0313SBeniamin Bia return ret;
26488dd0313SBeniamin Bia }
2656bf229abSStefan Popa st->oversampling = st->oversampling_avail[i];
2662985a5d8SStefan Popa mutex_unlock(&st->lock);
2672985a5d8SStefan Popa
2682985a5d8SStefan Popa return 0;
2692985a5d8SStefan Popa default:
2702985a5d8SStefan Popa return -EINVAL;
2712985a5d8SStefan Popa }
2722985a5d8SStefan Popa }
2732985a5d8SStefan Popa
ad7606_oversampling_ratio_avail(struct device * dev,struct device_attribute * attr,char * buf)2746bf229abSStefan Popa static ssize_t ad7606_oversampling_ratio_avail(struct device *dev,
2756bf229abSStefan Popa struct device_attribute *attr,
2766bf229abSStefan Popa char *buf)
2776bf229abSStefan Popa {
2786bf229abSStefan Popa struct iio_dev *indio_dev = dev_to_iio_dev(dev);
2796bf229abSStefan Popa struct ad7606_state *st = iio_priv(indio_dev);
2806bf229abSStefan Popa
2816bf229abSStefan Popa return ad7606_show_avail(buf, st->oversampling_avail,
2826bf229abSStefan Popa st->num_os_ratios, false);
2836bf229abSStefan Popa }
2846bf229abSStefan Popa
2856bf229abSStefan Popa static IIO_DEVICE_ATTR(oversampling_ratio_available, 0444,
2866bf229abSStefan Popa ad7606_oversampling_ratio_avail, NULL, 0);
2872985a5d8SStefan Popa
2882985a5d8SStefan Popa static struct attribute *ad7606_attributes_os_and_range[] = {
2892985a5d8SStefan Popa &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
2906bf229abSStefan Popa &iio_dev_attr_oversampling_ratio_available.dev_attr.attr,
2912985a5d8SStefan Popa NULL,
2922985a5d8SStefan Popa };
2932985a5d8SStefan Popa
2942985a5d8SStefan Popa static const struct attribute_group ad7606_attribute_group_os_and_range = {
2952985a5d8SStefan Popa .attrs = ad7606_attributes_os_and_range,
2962985a5d8SStefan Popa };
2972985a5d8SStefan Popa
2982985a5d8SStefan Popa static struct attribute *ad7606_attributes_os[] = {
2996bf229abSStefan Popa &iio_dev_attr_oversampling_ratio_available.dev_attr.attr,
3002985a5d8SStefan Popa NULL,
3012985a5d8SStefan Popa };
3022985a5d8SStefan Popa
3032985a5d8SStefan Popa static const struct attribute_group ad7606_attribute_group_os = {
3042985a5d8SStefan Popa .attrs = ad7606_attributes_os,
3052985a5d8SStefan Popa };
3062985a5d8SStefan Popa
3072985a5d8SStefan Popa static struct attribute *ad7606_attributes_range[] = {
3082985a5d8SStefan Popa &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
3092985a5d8SStefan Popa NULL,
3102985a5d8SStefan Popa };
3112985a5d8SStefan Popa
3122985a5d8SStefan Popa static const struct attribute_group ad7606_attribute_group_range = {
3132985a5d8SStefan Popa .attrs = ad7606_attributes_range,
3142985a5d8SStefan Popa };
3152985a5d8SStefan Popa
3162985a5d8SStefan Popa static const struct iio_chan_spec ad7605_channels[] = {
3172985a5d8SStefan Popa IIO_CHAN_SOFT_TIMESTAMP(4),
3182985a5d8SStefan Popa AD7605_CHANNEL(0),
3192985a5d8SStefan Popa AD7605_CHANNEL(1),
3202985a5d8SStefan Popa AD7605_CHANNEL(2),
3212985a5d8SStefan Popa AD7605_CHANNEL(3),
3222985a5d8SStefan Popa };
3232985a5d8SStefan Popa
3242985a5d8SStefan Popa static const struct iio_chan_spec ad7606_channels[] = {
3252985a5d8SStefan Popa IIO_CHAN_SOFT_TIMESTAMP(8),
3262985a5d8SStefan Popa AD7606_CHANNEL(0),
3272985a5d8SStefan Popa AD7606_CHANNEL(1),
3282985a5d8SStefan Popa AD7606_CHANNEL(2),
3292985a5d8SStefan Popa AD7606_CHANNEL(3),
3302985a5d8SStefan Popa AD7606_CHANNEL(4),
3312985a5d8SStefan Popa AD7606_CHANNEL(5),
3322985a5d8SStefan Popa AD7606_CHANNEL(6),
3332985a5d8SStefan Popa AD7606_CHANNEL(7),
3342985a5d8SStefan Popa };
3352985a5d8SStefan Popa
3367989b4bbSBeniamin Bia /*
3377989b4bbSBeniamin Bia * The current assumption that this driver makes for AD7616, is that it's
3387989b4bbSBeniamin Bia * working in Hardware Mode with Serial, Burst and Sequencer modes activated.
3397989b4bbSBeniamin Bia * To activate them, following pins must be pulled high:
3407989b4bbSBeniamin Bia * -SER/PAR
3417989b4bbSBeniamin Bia * -SEQEN
3427989b4bbSBeniamin Bia * And following pins must be pulled low:
3437989b4bbSBeniamin Bia * -WR/BURST
3447989b4bbSBeniamin Bia * -DB4/SER1W
3457989b4bbSBeniamin Bia */
3467989b4bbSBeniamin Bia static const struct iio_chan_spec ad7616_channels[] = {
3477989b4bbSBeniamin Bia IIO_CHAN_SOFT_TIMESTAMP(16),
3487989b4bbSBeniamin Bia AD7606_CHANNEL(0),
3497989b4bbSBeniamin Bia AD7606_CHANNEL(1),
3507989b4bbSBeniamin Bia AD7606_CHANNEL(2),
3517989b4bbSBeniamin Bia AD7606_CHANNEL(3),
3527989b4bbSBeniamin Bia AD7606_CHANNEL(4),
3537989b4bbSBeniamin Bia AD7606_CHANNEL(5),
3547989b4bbSBeniamin Bia AD7606_CHANNEL(6),
3557989b4bbSBeniamin Bia AD7606_CHANNEL(7),
3567989b4bbSBeniamin Bia AD7606_CHANNEL(8),
3577989b4bbSBeniamin Bia AD7606_CHANNEL(9),
3587989b4bbSBeniamin Bia AD7606_CHANNEL(10),
3597989b4bbSBeniamin Bia AD7606_CHANNEL(11),
3607989b4bbSBeniamin Bia AD7606_CHANNEL(12),
3617989b4bbSBeniamin Bia AD7606_CHANNEL(13),
3627989b4bbSBeniamin Bia AD7606_CHANNEL(14),
3637989b4bbSBeniamin Bia AD7606_CHANNEL(15),
3647989b4bbSBeniamin Bia };
3657989b4bbSBeniamin Bia
3662985a5d8SStefan Popa static const struct ad7606_chip_info ad7606_chip_info_tbl[] = {
3672985a5d8SStefan Popa /* More devices added in future */
3682985a5d8SStefan Popa [ID_AD7605_4] = {
3692985a5d8SStefan Popa .channels = ad7605_channels,
3702985a5d8SStefan Popa .num_channels = 5,
3712985a5d8SStefan Popa },
3722985a5d8SStefan Popa [ID_AD7606_8] = {
3732985a5d8SStefan Popa .channels = ad7606_channels,
3742985a5d8SStefan Popa .num_channels = 9,
3756bf229abSStefan Popa .oversampling_avail = ad7606_oversampling_avail,
3766bf229abSStefan Popa .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
3772985a5d8SStefan Popa },
3782985a5d8SStefan Popa [ID_AD7606_6] = {
3792985a5d8SStefan Popa .channels = ad7606_channels,
3802985a5d8SStefan Popa .num_channels = 7,
3816bf229abSStefan Popa .oversampling_avail = ad7606_oversampling_avail,
3826bf229abSStefan Popa .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
3832985a5d8SStefan Popa },
3842985a5d8SStefan Popa [ID_AD7606_4] = {
3852985a5d8SStefan Popa .channels = ad7606_channels,
3862985a5d8SStefan Popa .num_channels = 5,
3876bf229abSStefan Popa .oversampling_avail = ad7606_oversampling_avail,
3886bf229abSStefan Popa .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
3892985a5d8SStefan Popa },
390d2a415c8SStefan Popa [ID_AD7606B] = {
391d2a415c8SStefan Popa .channels = ad7606_channels,
392d2a415c8SStefan Popa .num_channels = 9,
393d2a415c8SStefan Popa .oversampling_avail = ad7606_oversampling_avail,
394d2a415c8SStefan Popa .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
395d2a415c8SStefan Popa },
3967989b4bbSBeniamin Bia [ID_AD7616] = {
3977989b4bbSBeniamin Bia .channels = ad7616_channels,
3987989b4bbSBeniamin Bia .num_channels = 17,
3997989b4bbSBeniamin Bia .oversampling_avail = ad7616_oversampling_avail,
4007989b4bbSBeniamin Bia .oversampling_num = ARRAY_SIZE(ad7616_oversampling_avail),
4017989b4bbSBeniamin Bia .os_req_reset = true,
402d2a415c8SStefan Popa .init_delay_ms = 15,
4037989b4bbSBeniamin Bia },
4042985a5d8SStefan Popa };
4052985a5d8SStefan Popa
ad7606_request_gpios(struct ad7606_state * st)4062985a5d8SStefan Popa static int ad7606_request_gpios(struct ad7606_state *st)
4072985a5d8SStefan Popa {
4082985a5d8SStefan Popa struct device *dev = st->dev;
4092985a5d8SStefan Popa
4102985a5d8SStefan Popa st->gpio_convst = devm_gpiod_get(dev, "adi,conversion-start",
4112985a5d8SStefan Popa GPIOD_OUT_LOW);
4122985a5d8SStefan Popa if (IS_ERR(st->gpio_convst))
4132985a5d8SStefan Popa return PTR_ERR(st->gpio_convst);
4142985a5d8SStefan Popa
4152985a5d8SStefan Popa st->gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4162985a5d8SStefan Popa if (IS_ERR(st->gpio_reset))
4172985a5d8SStefan Popa return PTR_ERR(st->gpio_reset);
4182985a5d8SStefan Popa
4192985a5d8SStefan Popa st->gpio_range = devm_gpiod_get_optional(dev, "adi,range",
4202985a5d8SStefan Popa GPIOD_OUT_LOW);
4212985a5d8SStefan Popa if (IS_ERR(st->gpio_range))
4222985a5d8SStefan Popa return PTR_ERR(st->gpio_range);
4232985a5d8SStefan Popa
4242985a5d8SStefan Popa st->gpio_standby = devm_gpiod_get_optional(dev, "standby",
425*0f115888SGuillaume Stols GPIOD_OUT_LOW);
4262985a5d8SStefan Popa if (IS_ERR(st->gpio_standby))
4272985a5d8SStefan Popa return PTR_ERR(st->gpio_standby);
4282985a5d8SStefan Popa
4292985a5d8SStefan Popa st->gpio_frstdata = devm_gpiod_get_optional(dev, "adi,first-data",
4302985a5d8SStefan Popa GPIOD_IN);
4312985a5d8SStefan Popa if (IS_ERR(st->gpio_frstdata))
4322985a5d8SStefan Popa return PTR_ERR(st->gpio_frstdata);
4332985a5d8SStefan Popa
4346bf229abSStefan Popa if (!st->chip_info->oversampling_num)
4352985a5d8SStefan Popa return 0;
4362985a5d8SStefan Popa
4372985a5d8SStefan Popa st->gpio_os = devm_gpiod_get_array_optional(dev,
4382985a5d8SStefan Popa "adi,oversampling-ratio",
4392985a5d8SStefan Popa GPIOD_OUT_LOW);
4402985a5d8SStefan Popa return PTR_ERR_OR_ZERO(st->gpio_os);
4412985a5d8SStefan Popa }
4422985a5d8SStefan Popa
4432985a5d8SStefan Popa /*
4442985a5d8SStefan Popa * The BUSY signal indicates when conversions are in progress, so when a rising
4452985a5d8SStefan Popa * edge of CONVST is applied, BUSY goes logic high and transitions low at the
4462985a5d8SStefan Popa * end of the entire conversion process. The falling edge of the BUSY signal
4472985a5d8SStefan Popa * triggers this interrupt.
4482985a5d8SStefan Popa */
ad7606_interrupt(int irq,void * dev_id)4492985a5d8SStefan Popa static irqreturn_t ad7606_interrupt(int irq, void *dev_id)
4502985a5d8SStefan Popa {
4512985a5d8SStefan Popa struct iio_dev *indio_dev = dev_id;
4522985a5d8SStefan Popa struct ad7606_state *st = iio_priv(indio_dev);
4532985a5d8SStefan Popa
4542985a5d8SStefan Popa if (iio_buffer_enabled(indio_dev)) {
4552985a5d8SStefan Popa gpiod_set_value(st->gpio_convst, 0);
456f700e55eSMehdi Djait iio_trigger_poll_nested(st->trig);
4572985a5d8SStefan Popa } else {
4582985a5d8SStefan Popa complete(&st->completion);
4592985a5d8SStefan Popa }
4602985a5d8SStefan Popa
4612985a5d8SStefan Popa return IRQ_HANDLED;
4622985a5d8SStefan Popa };
4632985a5d8SStefan Popa
ad7606_validate_trigger(struct iio_dev * indio_dev,struct iio_trigger * trig)4642985a5d8SStefan Popa static int ad7606_validate_trigger(struct iio_dev *indio_dev,
4652985a5d8SStefan Popa struct iio_trigger *trig)
4662985a5d8SStefan Popa {
4672985a5d8SStefan Popa struct ad7606_state *st = iio_priv(indio_dev);
4682985a5d8SStefan Popa
4692985a5d8SStefan Popa if (st->trig != trig)
4702985a5d8SStefan Popa return -EINVAL;
4712985a5d8SStefan Popa
4722985a5d8SStefan Popa return 0;
4732985a5d8SStefan Popa }
4742985a5d8SStefan Popa
ad7606_buffer_postenable(struct iio_dev * indio_dev)4752985a5d8SStefan Popa static int ad7606_buffer_postenable(struct iio_dev *indio_dev)
4762985a5d8SStefan Popa {
4772985a5d8SStefan Popa struct ad7606_state *st = iio_priv(indio_dev);
4782985a5d8SStefan Popa
4792985a5d8SStefan Popa gpiod_set_value(st->gpio_convst, 1);
4802985a5d8SStefan Popa
4812985a5d8SStefan Popa return 0;
4822985a5d8SStefan Popa }
4832985a5d8SStefan Popa
ad7606_buffer_predisable(struct iio_dev * indio_dev)4842985a5d8SStefan Popa static int ad7606_buffer_predisable(struct iio_dev *indio_dev)
4852985a5d8SStefan Popa {
4862985a5d8SStefan Popa struct ad7606_state *st = iio_priv(indio_dev);
4872985a5d8SStefan Popa
4882985a5d8SStefan Popa gpiod_set_value(st->gpio_convst, 0);
4892985a5d8SStefan Popa
490f11d59d8SLars-Peter Clausen return 0;
4912985a5d8SStefan Popa }
4922985a5d8SStefan Popa
4932985a5d8SStefan Popa static const struct iio_buffer_setup_ops ad7606_buffer_ops = {
4942985a5d8SStefan Popa .postenable = &ad7606_buffer_postenable,
4952985a5d8SStefan Popa .predisable = &ad7606_buffer_predisable,
4962985a5d8SStefan Popa };
4972985a5d8SStefan Popa
4982985a5d8SStefan Popa static const struct iio_info ad7606_info_no_os_or_range = {
4992985a5d8SStefan Popa .read_raw = &ad7606_read_raw,
5002985a5d8SStefan Popa .validate_trigger = &ad7606_validate_trigger,
5012985a5d8SStefan Popa };
5022985a5d8SStefan Popa
5032985a5d8SStefan Popa static const struct iio_info ad7606_info_os_and_range = {
5042985a5d8SStefan Popa .read_raw = &ad7606_read_raw,
5052985a5d8SStefan Popa .write_raw = &ad7606_write_raw,
5062985a5d8SStefan Popa .attrs = &ad7606_attribute_group_os_and_range,
5072985a5d8SStefan Popa .validate_trigger = &ad7606_validate_trigger,
5082985a5d8SStefan Popa };
5092985a5d8SStefan Popa
510a444fa59SBeniamin Bia static const struct iio_info ad7606_info_os_range_and_debug = {
511a444fa59SBeniamin Bia .read_raw = &ad7606_read_raw,
512a444fa59SBeniamin Bia .write_raw = &ad7606_write_raw,
513a444fa59SBeniamin Bia .debugfs_reg_access = &ad7606_reg_access,
514a444fa59SBeniamin Bia .attrs = &ad7606_attribute_group_os_and_range,
515a444fa59SBeniamin Bia .validate_trigger = &ad7606_validate_trigger,
516a444fa59SBeniamin Bia };
517a444fa59SBeniamin Bia
5182985a5d8SStefan Popa static const struct iio_info ad7606_info_os = {
5192985a5d8SStefan Popa .read_raw = &ad7606_read_raw,
5202985a5d8SStefan Popa .write_raw = &ad7606_write_raw,
5212985a5d8SStefan Popa .attrs = &ad7606_attribute_group_os,
5222985a5d8SStefan Popa .validate_trigger = &ad7606_validate_trigger,
5232985a5d8SStefan Popa };
5242985a5d8SStefan Popa
5252985a5d8SStefan Popa static const struct iio_info ad7606_info_range = {
5262985a5d8SStefan Popa .read_raw = &ad7606_read_raw,
5272985a5d8SStefan Popa .write_raw = &ad7606_write_raw,
5282985a5d8SStefan Popa .attrs = &ad7606_attribute_group_range,
5292985a5d8SStefan Popa .validate_trigger = &ad7606_validate_trigger,
5302985a5d8SStefan Popa };
5312985a5d8SStefan Popa
5322985a5d8SStefan Popa static const struct iio_trigger_ops ad7606_trigger_ops = {
5332985a5d8SStefan Popa .validate_device = iio_trigger_validate_own_device,
5342985a5d8SStefan Popa };
5352985a5d8SStefan Popa
ad7606_probe(struct device * dev,int irq,void __iomem * base_address,const char * name,unsigned int id,const struct ad7606_bus_ops * bops)5362985a5d8SStefan Popa int ad7606_probe(struct device *dev, int irq, void __iomem *base_address,
5372985a5d8SStefan Popa const char *name, unsigned int id,
5382985a5d8SStefan Popa const struct ad7606_bus_ops *bops)
5392985a5d8SStefan Popa {
5402985a5d8SStefan Popa struct ad7606_state *st;
5412985a5d8SStefan Popa int ret;
5422985a5d8SStefan Popa struct iio_dev *indio_dev;
5432985a5d8SStefan Popa
5442985a5d8SStefan Popa indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
5452985a5d8SStefan Popa if (!indio_dev)
5462985a5d8SStefan Popa return -ENOMEM;
5472985a5d8SStefan Popa
5482985a5d8SStefan Popa st = iio_priv(indio_dev);
5492985a5d8SStefan Popa dev_set_drvdata(dev, indio_dev);
5502985a5d8SStefan Popa
5512985a5d8SStefan Popa st->dev = dev;
5522985a5d8SStefan Popa mutex_init(&st->lock);
5532985a5d8SStefan Popa st->bops = bops;
5542985a5d8SStefan Popa st->base_address = base_address;
5552985a5d8SStefan Popa /* tied to logic low, analog input range is +/- 5V */
55688dd0313SBeniamin Bia st->range[0] = 0;
5572985a5d8SStefan Popa st->oversampling = 1;
5586bf229abSStefan Popa st->scale_avail = ad7606_scale_avail;
5596bf229abSStefan Popa st->num_scales = ARRAY_SIZE(ad7606_scale_avail);
5602985a5d8SStefan Popa
561fd5b6c48SMatti Vaittinen ret = devm_regulator_get_enable(dev, "avcc");
5622985a5d8SStefan Popa if (ret)
563fd5b6c48SMatti Vaittinen return dev_err_probe(dev, ret,
564fd5b6c48SMatti Vaittinen "Failed to enable specified AVcc supply\n");
5652985a5d8SStefan Popa
5662985a5d8SStefan Popa st->chip_info = &ad7606_chip_info_tbl[id];
5672985a5d8SStefan Popa
5686bf229abSStefan Popa if (st->chip_info->oversampling_num) {
5696bf229abSStefan Popa st->oversampling_avail = st->chip_info->oversampling_avail;
5706bf229abSStefan Popa st->num_os_ratios = st->chip_info->oversampling_num;
5716bf229abSStefan Popa }
5726bf229abSStefan Popa
5732985a5d8SStefan Popa ret = ad7606_request_gpios(st);
5742985a5d8SStefan Popa if (ret)
5752985a5d8SStefan Popa return ret;
5762985a5d8SStefan Popa
5772985a5d8SStefan Popa if (st->gpio_os) {
5782985a5d8SStefan Popa if (st->gpio_range)
5792985a5d8SStefan Popa indio_dev->info = &ad7606_info_os_and_range;
5802985a5d8SStefan Popa else
5812985a5d8SStefan Popa indio_dev->info = &ad7606_info_os;
5822985a5d8SStefan Popa } else {
5832985a5d8SStefan Popa if (st->gpio_range)
5842985a5d8SStefan Popa indio_dev->info = &ad7606_info_range;
5852985a5d8SStefan Popa else
5862985a5d8SStefan Popa indio_dev->info = &ad7606_info_no_os_or_range;
5872985a5d8SStefan Popa }
5882985a5d8SStefan Popa indio_dev->modes = INDIO_DIRECT_MODE;
5892985a5d8SStefan Popa indio_dev->name = name;
5902985a5d8SStefan Popa indio_dev->channels = st->chip_info->channels;
5912985a5d8SStefan Popa indio_dev->num_channels = st->chip_info->num_channels;
5922985a5d8SStefan Popa
5932985a5d8SStefan Popa init_completion(&st->completion);
5942985a5d8SStefan Popa
5952985a5d8SStefan Popa ret = ad7606_reset(st);
5962985a5d8SStefan Popa if (ret)
5972985a5d8SStefan Popa dev_warn(st->dev, "failed to RESET: no RESET GPIO specified\n");
5982985a5d8SStefan Popa
599c5d93137SBeniamin Bia /* AD7616 requires al least 15ms to reconfigure after a reset */
600d2a415c8SStefan Popa if (st->chip_info->init_delay_ms) {
601d2a415c8SStefan Popa if (msleep_interruptible(st->chip_info->init_delay_ms))
602c5d93137SBeniamin Bia return -ERESTARTSYS;
603d2a415c8SStefan Popa }
604c5d93137SBeniamin Bia
60588dd0313SBeniamin Bia st->write_scale = ad7606_write_scale_hw;
60688dd0313SBeniamin Bia st->write_os = ad7606_write_os_hw;
60788dd0313SBeniamin Bia
608a0c648c0SBeniamin Bia if (st->bops->sw_mode_config)
6093c23e9e8SBeniamin Bia st->sw_mode_en = device_property_present(st->dev,
6103c23e9e8SBeniamin Bia "adi,sw-mode");
6113c23e9e8SBeniamin Bia
6123c23e9e8SBeniamin Bia if (st->sw_mode_en) {
613f2a22e1eSBeniamin Bia /* Scale of 0.076293 is only available in sw mode */
614f2a22e1eSBeniamin Bia st->scale_avail = ad7616_sw_scale_avail;
615f2a22e1eSBeniamin Bia st->num_scales = ARRAY_SIZE(ad7616_sw_scale_avail);
616f2a22e1eSBeniamin Bia
6173c23e9e8SBeniamin Bia /* After reset, in software mode, ±10 V is set by default */
6183c23e9e8SBeniamin Bia memset32(st->range, 2, ARRAY_SIZE(st->range));
619a444fa59SBeniamin Bia indio_dev->info = &ad7606_info_os_range_and_debug;
6203c23e9e8SBeniamin Bia
621a0c648c0SBeniamin Bia ret = st->bops->sw_mode_config(indio_dev);
6223c23e9e8SBeniamin Bia if (ret < 0)
6233c23e9e8SBeniamin Bia return ret;
6243c23e9e8SBeniamin Bia }
6253c23e9e8SBeniamin Bia
6262985a5d8SStefan Popa st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
62715ea2878SJonathan Cameron indio_dev->name,
62815ea2878SJonathan Cameron iio_device_id(indio_dev));
6292985a5d8SStefan Popa if (!st->trig)
6302985a5d8SStefan Popa return -ENOMEM;
6312985a5d8SStefan Popa
6322985a5d8SStefan Popa st->trig->ops = &ad7606_trigger_ops;
6332985a5d8SStefan Popa iio_trigger_set_drvdata(st->trig, indio_dev);
6342985a5d8SStefan Popa ret = devm_iio_trigger_register(dev, st->trig);
6352985a5d8SStefan Popa if (ret)
6362985a5d8SStefan Popa return ret;
6372985a5d8SStefan Popa
6382985a5d8SStefan Popa indio_dev->trig = iio_trigger_get(st->trig);
6392985a5d8SStefan Popa
6402985a5d8SStefan Popa ret = devm_request_threaded_irq(dev, irq,
6412985a5d8SStefan Popa NULL,
6422985a5d8SStefan Popa &ad7606_interrupt,
6432985a5d8SStefan Popa IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
6442985a5d8SStefan Popa name, indio_dev);
6452985a5d8SStefan Popa if (ret)
6462985a5d8SStefan Popa return ret;
6472985a5d8SStefan Popa
6482985a5d8SStefan Popa ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
6492985a5d8SStefan Popa &iio_pollfunc_store_time,
6502985a5d8SStefan Popa &ad7606_trigger_handler,
6512985a5d8SStefan Popa &ad7606_buffer_ops);
6522985a5d8SStefan Popa if (ret)
6532985a5d8SStefan Popa return ret;
6542985a5d8SStefan Popa
6552985a5d8SStefan Popa return devm_iio_device_register(dev, indio_dev);
6562985a5d8SStefan Popa }
65759cea5bcSJonathan Cameron EXPORT_SYMBOL_NS_GPL(ad7606_probe, IIO_AD7606);
6582985a5d8SStefan Popa
6592985a5d8SStefan Popa #ifdef CONFIG_PM_SLEEP
6602985a5d8SStefan Popa
ad7606_suspend(struct device * dev)6612985a5d8SStefan Popa static int ad7606_suspend(struct device *dev)
6622985a5d8SStefan Popa {
6632985a5d8SStefan Popa struct iio_dev *indio_dev = dev_get_drvdata(dev);
6642985a5d8SStefan Popa struct ad7606_state *st = iio_priv(indio_dev);
6652985a5d8SStefan Popa
6662985a5d8SStefan Popa if (st->gpio_standby) {
6672985a5d8SStefan Popa gpiod_set_value(st->gpio_range, 1);
668*0f115888SGuillaume Stols gpiod_set_value(st->gpio_standby, 1);
6692985a5d8SStefan Popa }
6702985a5d8SStefan Popa
6712985a5d8SStefan Popa return 0;
6722985a5d8SStefan Popa }
6732985a5d8SStefan Popa
ad7606_resume(struct device * dev)6742985a5d8SStefan Popa static int ad7606_resume(struct device *dev)
6752985a5d8SStefan Popa {
6762985a5d8SStefan Popa struct iio_dev *indio_dev = dev_get_drvdata(dev);
6772985a5d8SStefan Popa struct ad7606_state *st = iio_priv(indio_dev);
6782985a5d8SStefan Popa
6792985a5d8SStefan Popa if (st->gpio_standby) {
68088dd0313SBeniamin Bia gpiod_set_value(st->gpio_range, st->range[0]);
6812985a5d8SStefan Popa gpiod_set_value(st->gpio_standby, 1);
6822985a5d8SStefan Popa ad7606_reset(st);
6832985a5d8SStefan Popa }
6842985a5d8SStefan Popa
6852985a5d8SStefan Popa return 0;
6862985a5d8SStefan Popa }
6872985a5d8SStefan Popa
6882985a5d8SStefan Popa SIMPLE_DEV_PM_OPS(ad7606_pm_ops, ad7606_suspend, ad7606_resume);
68959cea5bcSJonathan Cameron EXPORT_SYMBOL_NS_GPL(ad7606_pm_ops, IIO_AD7606);
6902985a5d8SStefan Popa
6912985a5d8SStefan Popa #endif
6922985a5d8SStefan Popa
6932985a5d8SStefan Popa MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
6942985a5d8SStefan Popa MODULE_DESCRIPTION("Analog Devices AD7606 ADC");
6952985a5d8SStefan Popa MODULE_LICENSE("GPL v2");
696