1*2025cf9eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2d5b97f5cSIrina Tirdea /* 3d5b97f5cSIrina Tirdea * Common code for Freescale MMA955x Intelligent Sensor Platform drivers 4d5b97f5cSIrina Tirdea * Copyright (c) 2014, Intel Corporation. 5d5b97f5cSIrina Tirdea */ 6d5b97f5cSIrina Tirdea 7d5b97f5cSIrina Tirdea #ifndef _MMA9551_CORE_H_ 8d5b97f5cSIrina Tirdea #define _MMA9551_CORE_H_ 9d5b97f5cSIrina Tirdea 10d5b97f5cSIrina Tirdea /* Applications IDs */ 11d5b97f5cSIrina Tirdea #define MMA9551_APPID_VERSION 0x00 12d5b97f5cSIrina Tirdea #define MMA9551_APPID_GPIO 0x03 13d5b97f5cSIrina Tirdea #define MMA9551_APPID_AFE 0x06 14d5b97f5cSIrina Tirdea #define MMA9551_APPID_TILT 0x0B 15d5b97f5cSIrina Tirdea #define MMA9551_APPID_SLEEP_WAKE 0x12 1640cb7613SIrina Tirdea #define MMA9551_APPID_PEDOMETER 0x15 17476c41a7SIrina Tirdea #define MMA9551_APPID_RSC 0x17 18d5b97f5cSIrina Tirdea #define MMA9551_APPID_NONE 0xff 19d5b97f5cSIrina Tirdea 2040cb7613SIrina Tirdea /* Reset/Suspend/Clear application app masks */ 2140cb7613SIrina Tirdea #define MMA9551_RSC_PED BIT(21) 2240cb7613SIrina Tirdea 23d5b97f5cSIrina Tirdea #define MMA9551_AUTO_SUSPEND_DELAY_MS 2000 24d5b97f5cSIrina Tirdea 25d5b97f5cSIrina Tirdea enum mma9551_gpio_pin { 26d5b97f5cSIrina Tirdea mma9551_gpio6 = 0, 27d5b97f5cSIrina Tirdea mma9551_gpio7, 28d5b97f5cSIrina Tirdea mma9551_gpio8, 29d5b97f5cSIrina Tirdea mma9551_gpio9, 30d5b97f5cSIrina Tirdea mma9551_gpio_max = mma9551_gpio9, 31d5b97f5cSIrina Tirdea }; 32d5b97f5cSIrina Tirdea 33d5b97f5cSIrina Tirdea #define MMA9551_ACCEL_CHANNEL(axis) { \ 34d5b97f5cSIrina Tirdea .type = IIO_ACCEL, \ 35d5b97f5cSIrina Tirdea .modified = 1, \ 36d5b97f5cSIrina Tirdea .channel2 = axis, \ 37d5b97f5cSIrina Tirdea .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 38d5b97f5cSIrina Tirdea .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 39d5b97f5cSIrina Tirdea } 40d5b97f5cSIrina Tirdea 41d5b97f5cSIrina Tirdea int mma9551_read_config_byte(struct i2c_client *client, u8 app_id, 42d5b97f5cSIrina Tirdea u16 reg, u8 *val); 43d5b97f5cSIrina Tirdea int mma9551_write_config_byte(struct i2c_client *client, u8 app_id, 44d5b97f5cSIrina Tirdea u16 reg, u8 val); 45d5b97f5cSIrina Tirdea int mma9551_read_status_byte(struct i2c_client *client, u8 app_id, 46d5b97f5cSIrina Tirdea u16 reg, u8 *val); 4740cb7613SIrina Tirdea int mma9551_read_config_word(struct i2c_client *client, u8 app_id, 4840cb7613SIrina Tirdea u16 reg, u16 *val); 4940cb7613SIrina Tirdea int mma9551_write_config_word(struct i2c_client *client, u8 app_id, 5040cb7613SIrina Tirdea u16 reg, u16 val); 51d5b97f5cSIrina Tirdea int mma9551_read_status_word(struct i2c_client *client, u8 app_id, 52d5b97f5cSIrina Tirdea u16 reg, u16 *val); 5340cb7613SIrina Tirdea int mma9551_read_config_words(struct i2c_client *client, u8 app_id, 5440cb7613SIrina Tirdea u16 reg, u8 len, u16 *buf); 5540cb7613SIrina Tirdea int mma9551_read_status_words(struct i2c_client *client, u8 app_id, 5640cb7613SIrina Tirdea u16 reg, u8 len, u16 *buf); 5740cb7613SIrina Tirdea int mma9551_write_config_words(struct i2c_client *client, u8 app_id, 5840cb7613SIrina Tirdea u16 reg, u8 len, u16 *buf); 59d5b97f5cSIrina Tirdea int mma9551_update_config_bits(struct i2c_client *client, u8 app_id, 60d5b97f5cSIrina Tirdea u16 reg, u8 mask, u8 val); 61d5b97f5cSIrina Tirdea int mma9551_gpio_config(struct i2c_client *client, enum mma9551_gpio_pin pin, 62d5b97f5cSIrina Tirdea u8 app_id, u8 bitnum, int polarity); 63d5b97f5cSIrina Tirdea int mma9551_read_version(struct i2c_client *client); 64d5b97f5cSIrina Tirdea int mma9551_set_device_state(struct i2c_client *client, bool enable); 65d5b97f5cSIrina Tirdea int mma9551_set_power_state(struct i2c_client *client, bool on); 66d5b97f5cSIrina Tirdea void mma9551_sleep(int freq); 67d5b97f5cSIrina Tirdea int mma9551_read_accel_chan(struct i2c_client *client, 68d5b97f5cSIrina Tirdea const struct iio_chan_spec *chan, 69d5b97f5cSIrina Tirdea int *val, int *val2); 70d5b97f5cSIrina Tirdea int mma9551_read_accel_scale(int *val, int *val2); 7140cb7613SIrina Tirdea int mma9551_app_reset(struct i2c_client *client, u32 app_mask); 72d5b97f5cSIrina Tirdea 73d5b97f5cSIrina Tirdea #endif /* _MMA9551_CORE_H_ */ 74