1 /* 2 * SuperH Mobile I2C Controller 3 * 4 * Copyright (C) 2008 Magnus Damm 5 * 6 * Portions of the code based on out-of-tree driver i2c-sh7343.c 7 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/init.h> 22 #include <linux/delay.h> 23 #include <linux/platform_device.h> 24 #include <linux/interrupt.h> 25 #include <linux/i2c.h> 26 #include <linux/err.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/clk.h> 29 #include <linux/io.h> 30 #include <linux/slab.h> 31 #include <linux/of_device.h> 32 #include <linux/i2c/i2c-sh_mobile.h> 33 34 /* Transmit operation: */ 35 /* */ 36 /* 0 byte transmit */ 37 /* BUS: S A8 ACK P(*) */ 38 /* IRQ: DTE WAIT */ 39 /* ICIC: */ 40 /* ICCR: 0x94 0x90 */ 41 /* ICDR: A8 */ 42 /* */ 43 /* 1 byte transmit */ 44 /* BUS: S A8 ACK D8(1) ACK P(*) */ 45 /* IRQ: DTE WAIT WAIT */ 46 /* ICIC: -DTE */ 47 /* ICCR: 0x94 0x90 */ 48 /* ICDR: A8 D8(1) */ 49 /* */ 50 /* 2 byte transmit */ 51 /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */ 52 /* IRQ: DTE WAIT WAIT WAIT */ 53 /* ICIC: -DTE */ 54 /* ICCR: 0x94 0x90 */ 55 /* ICDR: A8 D8(1) D8(2) */ 56 /* */ 57 /* 3 bytes or more, +---------+ gets repeated */ 58 /* */ 59 /* */ 60 /* Receive operation: */ 61 /* */ 62 /* 0 byte receive - not supported since slave may hold SDA low */ 63 /* */ 64 /* 1 byte receive [TX] | [RX] */ 65 /* BUS: S A8 ACK | D8(1) ACK P(*) */ 66 /* IRQ: DTE WAIT | WAIT DTE */ 67 /* ICIC: -DTE | +DTE */ 68 /* ICCR: 0x94 0x81 | 0xc0 */ 69 /* ICDR: A8 | D8(1) */ 70 /* */ 71 /* 2 byte receive [TX]| [RX] */ 72 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */ 73 /* IRQ: DTE WAIT | WAIT WAIT DTE */ 74 /* ICIC: -DTE | +DTE */ 75 /* ICCR: 0x94 0x81 | 0xc0 */ 76 /* ICDR: A8 | D8(1) D8(2) */ 77 /* */ 78 /* 3 byte receive [TX] | [RX] (*) */ 79 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */ 80 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */ 81 /* ICIC: -DTE | +DTE */ 82 /* ICCR: 0x94 0x81 | 0xc0 */ 83 /* ICDR: A8 | D8(1) D8(2) D8(3) */ 84 /* */ 85 /* 4 bytes or more, this part is repeated +---------+ */ 86 /* */ 87 /* */ 88 /* Interrupt order and BUSY flag */ 89 /* ___ _ */ 90 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */ 91 /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */ 92 /* */ 93 /* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */ 94 /* ___ */ 95 /* WAIT IRQ ________________________________/ \___________ */ 96 /* TACK IRQ ____________________________________/ \_______ */ 97 /* DTE IRQ __________________________________________/ \_ */ 98 /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 99 /* _______________________________________________ */ 100 /* BUSY __/ \_ */ 101 /* */ 102 /* (*) The STOP condition is only sent by the master at the end of the last */ 103 /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */ 104 /* only cleared after the STOP condition, so, between messages we have to */ 105 /* poll for the DTE bit. */ 106 /* */ 107 108 enum sh_mobile_i2c_op { 109 OP_START = 0, 110 OP_TX_FIRST, 111 OP_TX, 112 OP_TX_STOP, 113 OP_TX_TO_RX, 114 OP_RX, 115 OP_RX_STOP, 116 OP_RX_STOP_DATA, 117 }; 118 119 struct sh_mobile_i2c_data { 120 struct device *dev; 121 void __iomem *reg; 122 struct i2c_adapter adap; 123 unsigned long bus_speed; 124 unsigned int clks_per_count; 125 struct clk *clk; 126 u_int8_t icic; 127 u_int8_t flags; 128 u_int16_t iccl; 129 u_int16_t icch; 130 131 spinlock_t lock; 132 wait_queue_head_t wait; 133 struct i2c_msg *msg; 134 int pos; 135 int sr; 136 bool send_stop; 137 }; 138 139 struct sh_mobile_dt_config { 140 int clks_per_count; 141 }; 142 143 #define IIC_FLAG_HAS_ICIC67 (1 << 0) 144 145 #define STANDARD_MODE 100000 146 #define FAST_MODE 400000 147 148 /* Register offsets */ 149 #define ICDR 0x00 150 #define ICCR 0x04 151 #define ICSR 0x08 152 #define ICIC 0x0c 153 #define ICCL 0x10 154 #define ICCH 0x14 155 156 /* Register bits */ 157 #define ICCR_ICE 0x80 158 #define ICCR_RACK 0x40 159 #define ICCR_TRS 0x10 160 #define ICCR_BBSY 0x04 161 #define ICCR_SCP 0x01 162 163 #define ICSR_SCLM 0x80 164 #define ICSR_SDAM 0x40 165 #define SW_DONE 0x20 166 #define ICSR_BUSY 0x10 167 #define ICSR_AL 0x08 168 #define ICSR_TACK 0x04 169 #define ICSR_WAIT 0x02 170 #define ICSR_DTE 0x01 171 172 #define ICIC_ICCLB8 0x80 173 #define ICIC_ICCHB8 0x40 174 #define ICIC_ALE 0x08 175 #define ICIC_TACKE 0x04 176 #define ICIC_WAITE 0x02 177 #define ICIC_DTEE 0x01 178 179 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data) 180 { 181 if (offs == ICIC) 182 data |= pd->icic; 183 184 iowrite8(data, pd->reg + offs); 185 } 186 187 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs) 188 { 189 return ioread8(pd->reg + offs); 190 } 191 192 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs, 193 unsigned char set, unsigned char clr) 194 { 195 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr); 196 } 197 198 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf) 199 { 200 /* 201 * Conditional expression: 202 * ICCL >= COUNT_CLK * (tLOW + tf) 203 * 204 * SH-Mobile IIC hardware starts counting the LOW period of 205 * the SCL signal (tLOW) as soon as it pulls the SCL line. 206 * In order to meet the tLOW timing spec, we need to take into 207 * account the fall time of SCL signal (tf). Default tf value 208 * should be 0.3 us, for safety. 209 */ 210 return (((count_khz * (tLOW + tf)) + 5000) / 10000); 211 } 212 213 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf) 214 { 215 /* 216 * Conditional expression: 217 * ICCH >= COUNT_CLK * (tHIGH + tf) 218 * 219 * SH-Mobile IIC hardware is aware of SCL transition period 'tr', 220 * and can ignore it. SH-Mobile IIC controller starts counting 221 * the HIGH period of the SCL signal (tHIGH) after the SCL input 222 * voltage increases at VIH. 223 * 224 * Afterward it turned out calculating ICCH using only tHIGH spec 225 * will result in violation of the tHD;STA timing spec. We need 226 * to take into account the fall time of SDA signal (tf) at START 227 * condition, in order to meet both tHIGH and tHD;STA specs. 228 */ 229 return (((count_khz * (tHIGH + tf)) + 5000) / 10000); 230 } 231 232 static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd) 233 { 234 unsigned long i2c_clk_khz; 235 u32 tHIGH, tLOW, tf; 236 uint16_t max_val; 237 238 /* Get clock rate after clock is enabled */ 239 clk_prepare_enable(pd->clk); 240 i2c_clk_khz = clk_get_rate(pd->clk) / 1000; 241 clk_disable_unprepare(pd->clk); 242 i2c_clk_khz /= pd->clks_per_count; 243 244 if (pd->bus_speed == STANDARD_MODE) { 245 tLOW = 47; /* tLOW = 4.7 us */ 246 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */ 247 tf = 3; /* tf = 0.3 us */ 248 } else if (pd->bus_speed == FAST_MODE) { 249 tLOW = 13; /* tLOW = 1.3 us */ 250 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */ 251 tf = 3; /* tf = 0.3 us */ 252 } else { 253 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n", 254 pd->bus_speed); 255 return -EINVAL; 256 } 257 258 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf); 259 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf); 260 261 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff; 262 if (pd->iccl > max_val || pd->icch > max_val) { 263 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n", 264 pd->iccl, pd->icch); 265 return -EINVAL; 266 } 267 268 /* one more bit of ICCL in ICIC */ 269 if (pd->iccl & 0x100) 270 pd->icic |= ICIC_ICCLB8; 271 else 272 pd->icic &= ~ICIC_ICCLB8; 273 274 /* one more bit of ICCH in ICIC */ 275 if (pd->icch & 0x100) 276 pd->icic |= ICIC_ICCHB8; 277 else 278 pd->icic &= ~ICIC_ICCHB8; 279 280 return 0; 281 } 282 283 static void activate_ch(struct sh_mobile_i2c_data *pd) 284 { 285 /* Wake up device and enable clock */ 286 pm_runtime_get_sync(pd->dev); 287 clk_prepare_enable(pd->clk); 288 289 /* Enable channel and configure rx ack */ 290 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 291 292 /* Mask all interrupts */ 293 iic_wr(pd, ICIC, 0); 294 295 /* Set the clock */ 296 iic_wr(pd, ICCL, pd->iccl & 0xff); 297 iic_wr(pd, ICCH, pd->icch & 0xff); 298 } 299 300 static void deactivate_ch(struct sh_mobile_i2c_data *pd) 301 { 302 /* Clear/disable interrupts */ 303 iic_wr(pd, ICSR, 0); 304 iic_wr(pd, ICIC, 0); 305 306 /* Disable channel */ 307 iic_set_clr(pd, ICCR, 0, ICCR_ICE); 308 309 /* Disable clock and mark device as idle */ 310 clk_disable_unprepare(pd->clk); 311 pm_runtime_put_sync(pd->dev); 312 } 313 314 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, 315 enum sh_mobile_i2c_op op, unsigned char data) 316 { 317 unsigned char ret = 0; 318 unsigned long flags; 319 320 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data); 321 322 spin_lock_irqsave(&pd->lock, flags); 323 324 switch (op) { 325 case OP_START: /* issue start and trigger DTE interrupt */ 326 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY); 327 break; 328 case OP_TX_FIRST: /* disable DTE interrupt and write data */ 329 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 330 iic_wr(pd, ICDR, data); 331 break; 332 case OP_TX: /* write data */ 333 iic_wr(pd, ICDR, data); 334 break; 335 case OP_TX_STOP: /* write data and issue a stop afterwards */ 336 iic_wr(pd, ICDR, data); 337 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS 338 : ICCR_ICE | ICCR_TRS | ICCR_BBSY); 339 break; 340 case OP_TX_TO_RX: /* select read mode */ 341 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP); 342 break; 343 case OP_RX: /* just read data */ 344 ret = iic_rd(pd, ICDR); 345 break; 346 case OP_RX_STOP: /* enable DTE interrupt, issue stop */ 347 iic_wr(pd, ICIC, 348 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 349 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); 350 break; 351 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */ 352 iic_wr(pd, ICIC, 353 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 354 ret = iic_rd(pd, ICDR); 355 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); 356 break; 357 } 358 359 spin_unlock_irqrestore(&pd->lock, flags); 360 361 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret); 362 return ret; 363 } 364 365 static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd) 366 { 367 return pd->pos == -1; 368 } 369 370 static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd) 371 { 372 return pd->pos == pd->msg->len - 1; 373 } 374 375 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd, 376 unsigned char *buf) 377 { 378 switch (pd->pos) { 379 case -1: 380 *buf = (pd->msg->addr & 0x7f) << 1; 381 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0; 382 break; 383 default: 384 *buf = pd->msg->buf[pd->pos]; 385 } 386 } 387 388 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd) 389 { 390 unsigned char data; 391 392 if (pd->pos == pd->msg->len) 393 return 1; 394 395 sh_mobile_i2c_get_data(pd, &data); 396 397 if (sh_mobile_i2c_is_last_byte(pd)) 398 i2c_op(pd, OP_TX_STOP, data); 399 else if (sh_mobile_i2c_is_first_byte(pd)) 400 i2c_op(pd, OP_TX_FIRST, data); 401 else 402 i2c_op(pd, OP_TX, data); 403 404 pd->pos++; 405 return 0; 406 } 407 408 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd) 409 { 410 unsigned char data; 411 int real_pos; 412 413 do { 414 if (pd->pos <= -1) { 415 sh_mobile_i2c_get_data(pd, &data); 416 417 if (sh_mobile_i2c_is_first_byte(pd)) 418 i2c_op(pd, OP_TX_FIRST, data); 419 else 420 i2c_op(pd, OP_TX, data); 421 break; 422 } 423 424 if (pd->pos == 0) { 425 i2c_op(pd, OP_TX_TO_RX, 0); 426 break; 427 } 428 429 real_pos = pd->pos - 2; 430 431 if (pd->pos == pd->msg->len) { 432 if (real_pos < 0) { 433 i2c_op(pd, OP_RX_STOP, 0); 434 break; 435 } 436 data = i2c_op(pd, OP_RX_STOP_DATA, 0); 437 } else 438 data = i2c_op(pd, OP_RX, 0); 439 440 if (real_pos >= 0) 441 pd->msg->buf[real_pos] = data; 442 } while (0); 443 444 pd->pos++; 445 return pd->pos == (pd->msg->len + 2); 446 } 447 448 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) 449 { 450 struct platform_device *dev = dev_id; 451 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 452 unsigned char sr; 453 int wakeup; 454 455 sr = iic_rd(pd, ICSR); 456 pd->sr |= sr; /* remember state */ 457 458 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr, 459 (pd->msg->flags & I2C_M_RD) ? "read" : "write", 460 pd->pos, pd->msg->len); 461 462 if (sr & (ICSR_AL | ICSR_TACK)) { 463 /* don't interrupt transaction - continue to issue stop */ 464 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK)); 465 wakeup = 0; 466 } else if (pd->msg->flags & I2C_M_RD) 467 wakeup = sh_mobile_i2c_isr_rx(pd); 468 else 469 wakeup = sh_mobile_i2c_isr_tx(pd); 470 471 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */ 472 iic_wr(pd, ICSR, sr & ~ICSR_WAIT); 473 474 if (wakeup) { 475 pd->sr |= SW_DONE; 476 wake_up(&pd->wait); 477 } 478 479 /* defeat write posting to avoid spurious WAIT interrupts */ 480 iic_rd(pd, ICSR); 481 482 return IRQ_HANDLED; 483 } 484 485 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg, 486 bool do_init) 487 { 488 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) { 489 dev_err(pd->dev, "Unsupported zero length i2c read\n"); 490 return -EOPNOTSUPP; 491 } 492 493 if (do_init) { 494 /* Initialize channel registers */ 495 iic_set_clr(pd, ICCR, 0, ICCR_ICE); 496 497 /* Enable channel and configure rx ack */ 498 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 499 500 /* Set the clock */ 501 iic_wr(pd, ICCL, pd->iccl & 0xff); 502 iic_wr(pd, ICCH, pd->icch & 0xff); 503 } 504 505 pd->msg = usr_msg; 506 pd->pos = -1; 507 pd->sr = 0; 508 509 /* Enable all interrupts to begin with */ 510 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 511 return 0; 512 } 513 514 static int poll_dte(struct sh_mobile_i2c_data *pd) 515 { 516 int i; 517 518 for (i = 1000; i; i--) { 519 u_int8_t val = iic_rd(pd, ICSR); 520 521 if (val & ICSR_DTE) 522 break; 523 524 if (val & ICSR_TACK) 525 return -ENXIO; 526 527 udelay(10); 528 } 529 530 return i ? 0 : -ETIMEDOUT; 531 } 532 533 static int poll_busy(struct sh_mobile_i2c_data *pd) 534 { 535 int i; 536 537 for (i = 1000; i; i--) { 538 u_int8_t val = iic_rd(pd, ICSR); 539 540 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); 541 542 /* the interrupt handler may wake us up before the 543 * transfer is finished, so poll the hardware 544 * until we're done. 545 */ 546 if (!(val & ICSR_BUSY)) { 547 /* handle missing acknowledge and arbitration lost */ 548 val |= pd->sr; 549 if (val & ICSR_TACK) 550 return -ENXIO; 551 if (val & ICSR_AL) 552 return -EAGAIN; 553 break; 554 } 555 556 udelay(10); 557 } 558 559 return i ? 0 : -ETIMEDOUT; 560 } 561 562 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter, 563 struct i2c_msg *msgs, 564 int num) 565 { 566 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter); 567 struct i2c_msg *msg; 568 int err = 0; 569 int i, k; 570 571 activate_ch(pd); 572 573 /* Process all messages */ 574 for (i = 0; i < num; i++) { 575 bool do_start = pd->send_stop || !i; 576 msg = &msgs[i]; 577 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP; 578 579 err = start_ch(pd, msg, do_start); 580 if (err) 581 break; 582 583 if (do_start) 584 i2c_op(pd, OP_START, 0); 585 586 /* The interrupt handler takes care of the rest... */ 587 k = wait_event_timeout(pd->wait, 588 pd->sr & (ICSR_TACK | SW_DONE), 589 5 * HZ); 590 if (!k) { 591 dev_err(pd->dev, "Transfer request timed out\n"); 592 err = -ETIMEDOUT; 593 break; 594 } 595 596 if (pd->send_stop) 597 err = poll_busy(pd); 598 else 599 err = poll_dte(pd); 600 if (err < 0) 601 break; 602 } 603 604 deactivate_ch(pd); 605 606 if (!err) 607 err = num; 608 return err; 609 } 610 611 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter) 612 { 613 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 614 } 615 616 static struct i2c_algorithm sh_mobile_i2c_algorithm = { 617 .functionality = sh_mobile_i2c_func, 618 .master_xfer = sh_mobile_i2c_xfer, 619 }; 620 621 static const struct sh_mobile_dt_config default_dt_config = { 622 .clks_per_count = 1, 623 }; 624 625 static const struct sh_mobile_dt_config rcar_gen2_dt_config = { 626 .clks_per_count = 2, 627 }; 628 629 static const struct of_device_id sh_mobile_i2c_dt_ids[] = { 630 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config }, 631 { .compatible = "renesas,iic-r8a7790", .data = &rcar_gen2_dt_config }, 632 { .compatible = "renesas,iic-r8a7791", .data = &rcar_gen2_dt_config }, 633 { .compatible = "renesas,iic-r8a7792", .data = &rcar_gen2_dt_config }, 634 { .compatible = "renesas,iic-r8a7793", .data = &rcar_gen2_dt_config }, 635 { .compatible = "renesas,iic-r8a7794", .data = &rcar_gen2_dt_config }, 636 {}, 637 }; 638 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids); 639 640 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev) 641 { 642 struct resource *res; 643 resource_size_t n; 644 int k = 0, ret; 645 646 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) { 647 for (n = res->start; n <= res->end; n++) { 648 ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr, 649 0, dev_name(&dev->dev), dev); 650 if (ret) { 651 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n); 652 return ret; 653 } 654 } 655 k++; 656 } 657 658 return k > 0 ? 0 : -ENOENT; 659 } 660 661 static int sh_mobile_i2c_probe(struct platform_device *dev) 662 { 663 struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev); 664 struct sh_mobile_i2c_data *pd; 665 struct i2c_adapter *adap; 666 struct resource *res; 667 int ret; 668 u32 bus_speed; 669 670 pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL); 671 if (!pd) 672 return -ENOMEM; 673 674 pd->clk = devm_clk_get(&dev->dev, NULL); 675 if (IS_ERR(pd->clk)) { 676 dev_err(&dev->dev, "cannot get clock\n"); 677 return PTR_ERR(pd->clk); 678 } 679 680 ret = sh_mobile_i2c_hook_irqs(dev); 681 if (ret) 682 return ret; 683 684 pd->dev = &dev->dev; 685 platform_set_drvdata(dev, pd); 686 687 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 688 689 pd->reg = devm_ioremap_resource(&dev->dev, res); 690 if (IS_ERR(pd->reg)) 691 return PTR_ERR(pd->reg); 692 693 /* Use platform data bus speed or STANDARD_MODE */ 694 ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed); 695 pd->bus_speed = ret ? STANDARD_MODE : bus_speed; 696 697 pd->clks_per_count = 1; 698 699 if (dev->dev.of_node) { 700 const struct of_device_id *match; 701 702 match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev); 703 if (match) { 704 const struct sh_mobile_dt_config *config; 705 706 config = match->data; 707 pd->clks_per_count = config->clks_per_count; 708 } 709 } else { 710 if (pdata && pdata->bus_speed) 711 pd->bus_speed = pdata->bus_speed; 712 if (pdata && pdata->clks_per_count) 713 pd->clks_per_count = pdata->clks_per_count; 714 } 715 716 /* The IIC blocks on SH-Mobile ARM processors 717 * come with two new bits in ICIC. 718 */ 719 if (resource_size(res) > 0x17) 720 pd->flags |= IIC_FLAG_HAS_ICIC67; 721 722 ret = sh_mobile_i2c_init(pd); 723 if (ret) 724 return ret; 725 726 /* Enable Runtime PM for this device. 727 * 728 * Also tell the Runtime PM core to ignore children 729 * for this device since it is valid for us to suspend 730 * this I2C master driver even though the slave devices 731 * on the I2C bus may not be suspended. 732 * 733 * The state of the I2C hardware bus is unaffected by 734 * the Runtime PM state. 735 */ 736 pm_suspend_ignore_children(&dev->dev, true); 737 pm_runtime_enable(&dev->dev); 738 739 /* setup the private data */ 740 adap = &pd->adap; 741 i2c_set_adapdata(adap, pd); 742 743 adap->owner = THIS_MODULE; 744 adap->algo = &sh_mobile_i2c_algorithm; 745 adap->dev.parent = &dev->dev; 746 adap->retries = 5; 747 adap->nr = dev->id; 748 adap->dev.of_node = dev->dev.of_node; 749 750 strlcpy(adap->name, dev->name, sizeof(adap->name)); 751 752 spin_lock_init(&pd->lock); 753 init_waitqueue_head(&pd->wait); 754 755 ret = i2c_add_numbered_adapter(adap); 756 if (ret < 0) { 757 dev_err(&dev->dev, "cannot add numbered adapter\n"); 758 return ret; 759 } 760 761 dev_info(&dev->dev, 762 "I2C adapter %d with bus speed %lu Hz (L/H=0x%x/0x%x)\n", 763 adap->nr, pd->bus_speed, pd->iccl, pd->icch); 764 765 return 0; 766 } 767 768 static int sh_mobile_i2c_remove(struct platform_device *dev) 769 { 770 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 771 772 i2c_del_adapter(&pd->adap); 773 pm_runtime_disable(&dev->dev); 774 return 0; 775 } 776 777 static int sh_mobile_i2c_runtime_nop(struct device *dev) 778 { 779 /* Runtime PM callback shared between ->runtime_suspend() 780 * and ->runtime_resume(). Simply returns success. 781 * 782 * This driver re-initializes all registers after 783 * pm_runtime_get_sync() anyway so there is no need 784 * to save and restore registers here. 785 */ 786 return 0; 787 } 788 789 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = { 790 .runtime_suspend = sh_mobile_i2c_runtime_nop, 791 .runtime_resume = sh_mobile_i2c_runtime_nop, 792 }; 793 794 static struct platform_driver sh_mobile_i2c_driver = { 795 .driver = { 796 .name = "i2c-sh_mobile", 797 .owner = THIS_MODULE, 798 .pm = &sh_mobile_i2c_dev_pm_ops, 799 .of_match_table = sh_mobile_i2c_dt_ids, 800 }, 801 .probe = sh_mobile_i2c_probe, 802 .remove = sh_mobile_i2c_remove, 803 }; 804 805 static int __init sh_mobile_i2c_adap_init(void) 806 { 807 return platform_driver_register(&sh_mobile_i2c_driver); 808 } 809 810 static void __exit sh_mobile_i2c_adap_exit(void) 811 { 812 platform_driver_unregister(&sh_mobile_i2c_driver); 813 } 814 815 subsys_initcall(sh_mobile_i2c_adap_init); 816 module_exit(sh_mobile_i2c_adap_exit); 817 818 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver"); 819 MODULE_AUTHOR("Magnus Damm"); 820 MODULE_LICENSE("GPL v2"); 821 MODULE_ALIAS("platform:i2c-sh_mobile"); 822