1 /* 2 * TI DAVINCI I2C adapter driver. 3 * 4 * Copyright (C) 2006 Texas Instruments. 5 * Copyright (C) 2007 MontaVista Software Inc. 6 * 7 * Updated by Vinod & Sudhakar Feb 2005 8 * 9 * ---------------------------------------------------------------------------- 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 * ---------------------------------------------------------------------------- 25 * 26 */ 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/delay.h> 30 #include <linux/i2c.h> 31 #include <linux/clk.h> 32 #include <linux/errno.h> 33 #include <linux/sched.h> 34 #include <linux/err.h> 35 #include <linux/interrupt.h> 36 #include <linux/platform_device.h> 37 #include <linux/io.h> 38 #include <linux/slab.h> 39 40 #include <mach/hardware.h> 41 #include <mach/i2c.h> 42 43 /* ----- global defines ----------------------------------------------- */ 44 45 #define DAVINCI_I2C_TIMEOUT (1*HZ) 46 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \ 47 DAVINCI_I2C_IMR_SCD | \ 48 DAVINCI_I2C_IMR_ARDY | \ 49 DAVINCI_I2C_IMR_NACK | \ 50 DAVINCI_I2C_IMR_AL) 51 52 #define DAVINCI_I2C_OAR_REG 0x00 53 #define DAVINCI_I2C_IMR_REG 0x04 54 #define DAVINCI_I2C_STR_REG 0x08 55 #define DAVINCI_I2C_CLKL_REG 0x0c 56 #define DAVINCI_I2C_CLKH_REG 0x10 57 #define DAVINCI_I2C_CNT_REG 0x14 58 #define DAVINCI_I2C_DRR_REG 0x18 59 #define DAVINCI_I2C_SAR_REG 0x1c 60 #define DAVINCI_I2C_DXR_REG 0x20 61 #define DAVINCI_I2C_MDR_REG 0x24 62 #define DAVINCI_I2C_IVR_REG 0x28 63 #define DAVINCI_I2C_EMDR_REG 0x2c 64 #define DAVINCI_I2C_PSC_REG 0x30 65 66 #define DAVINCI_I2C_IVR_AAS 0x07 67 #define DAVINCI_I2C_IVR_SCD 0x06 68 #define DAVINCI_I2C_IVR_XRDY 0x05 69 #define DAVINCI_I2C_IVR_RDR 0x04 70 #define DAVINCI_I2C_IVR_ARDY 0x03 71 #define DAVINCI_I2C_IVR_NACK 0x02 72 #define DAVINCI_I2C_IVR_AL 0x01 73 74 #define DAVINCI_I2C_STR_BB BIT(12) 75 #define DAVINCI_I2C_STR_RSFULL BIT(11) 76 #define DAVINCI_I2C_STR_SCD BIT(5) 77 #define DAVINCI_I2C_STR_ARDY BIT(2) 78 #define DAVINCI_I2C_STR_NACK BIT(1) 79 #define DAVINCI_I2C_STR_AL BIT(0) 80 81 #define DAVINCI_I2C_MDR_NACK BIT(15) 82 #define DAVINCI_I2C_MDR_STT BIT(13) 83 #define DAVINCI_I2C_MDR_STP BIT(11) 84 #define DAVINCI_I2C_MDR_MST BIT(10) 85 #define DAVINCI_I2C_MDR_TRX BIT(9) 86 #define DAVINCI_I2C_MDR_XA BIT(8) 87 #define DAVINCI_I2C_MDR_RM BIT(7) 88 #define DAVINCI_I2C_MDR_IRS BIT(5) 89 90 #define DAVINCI_I2C_IMR_AAS BIT(6) 91 #define DAVINCI_I2C_IMR_SCD BIT(5) 92 #define DAVINCI_I2C_IMR_XRDY BIT(4) 93 #define DAVINCI_I2C_IMR_RRDY BIT(3) 94 #define DAVINCI_I2C_IMR_ARDY BIT(2) 95 #define DAVINCI_I2C_IMR_NACK BIT(1) 96 #define DAVINCI_I2C_IMR_AL BIT(0) 97 98 struct davinci_i2c_dev { 99 struct device *dev; 100 void __iomem *base; 101 struct completion cmd_complete; 102 struct clk *clk; 103 int cmd_err; 104 u8 *buf; 105 size_t buf_len; 106 int irq; 107 int stop; 108 u8 terminate; 109 struct i2c_adapter adapter; 110 }; 111 112 /* default platform data to use if not supplied in the platform_device */ 113 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = { 114 .bus_freq = 100, 115 .bus_delay = 0, 116 }; 117 118 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev, 119 int reg, u16 val) 120 { 121 __raw_writew(val, i2c_dev->base + reg); 122 } 123 124 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg) 125 { 126 return __raw_readw(i2c_dev->base + reg); 127 } 128 129 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev, 130 int val) 131 { 132 u16 w; 133 134 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG); 135 if (!val) /* put I2C into reset */ 136 w &= ~DAVINCI_I2C_MDR_IRS; 137 else /* take I2C out of reset */ 138 w |= DAVINCI_I2C_MDR_IRS; 139 140 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w); 141 } 142 143 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) 144 { 145 struct davinci_i2c_platform_data *pdata = dev->dev->platform_data; 146 u16 psc; 147 u32 clk; 148 u32 d; 149 u32 clkh; 150 u32 clkl; 151 u32 input_clock = clk_get_rate(dev->clk); 152 153 /* NOTE: I2C Clock divider programming info 154 * As per I2C specs the following formulas provide prescaler 155 * and low/high divider values 156 * input clk --> PSC Div -----------> ICCL/H Div --> output clock 157 * module clk 158 * 159 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ] 160 * 161 * Thus, 162 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d; 163 * 164 * where if PSC == 0, d = 7, 165 * if PSC == 1, d = 6 166 * if PSC > 1 , d = 5 167 */ 168 169 /* get minimum of 7 MHz clock, but max of 12 MHz */ 170 psc = (input_clock / 7000000) - 1; 171 if ((input_clock / (psc + 1)) > 12000000) 172 psc++; /* better to run under spec than over */ 173 d = (psc >= 2) ? 5 : 7 - psc; 174 175 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1); 176 clkh = clk >> 1; 177 clkl = clk - clkh; 178 179 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc); 180 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); 181 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl); 182 183 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk); 184 } 185 186 /* 187 * This function configures I2C and brings I2C out of reset. 188 * This function is called during I2C init function. This function 189 * also gets called if I2C encounters any errors. 190 */ 191 static int i2c_davinci_init(struct davinci_i2c_dev *dev) 192 { 193 struct davinci_i2c_platform_data *pdata = dev->dev->platform_data; 194 195 if (!pdata) 196 pdata = &davinci_i2c_platform_data_default; 197 198 /* put I2C into reset */ 199 davinci_i2c_reset_ctrl(dev, 0); 200 201 /* compute clock dividers */ 202 i2c_davinci_calc_clk_dividers(dev); 203 204 /* Respond at reserved "SMBus Host" slave address" (and zero); 205 * we seem to have no option to not respond... 206 */ 207 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08); 208 209 dev_dbg(dev->dev, "PSC = %d\n", 210 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG)); 211 dev_dbg(dev->dev, "CLKL = %d\n", 212 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); 213 dev_dbg(dev->dev, "CLKH = %d\n", 214 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); 215 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n", 216 pdata->bus_freq, pdata->bus_delay); 217 218 /* Take the I2C module out of reset: */ 219 davinci_i2c_reset_ctrl(dev, 1); 220 221 /* Enable interrupts */ 222 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL); 223 224 return 0; 225 } 226 227 /* 228 * Waiting for bus not busy 229 */ 230 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev, 231 char allow_sleep) 232 { 233 unsigned long timeout; 234 235 timeout = jiffies + dev->adapter.timeout; 236 while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) 237 & DAVINCI_I2C_STR_BB) { 238 if (time_after(jiffies, timeout)) { 239 dev_warn(dev->dev, 240 "timeout waiting for bus ready\n"); 241 return -ETIMEDOUT; 242 } 243 if (allow_sleep) 244 schedule_timeout(1); 245 } 246 247 return 0; 248 } 249 250 /* 251 * Low level master read/write transaction. This function is called 252 * from i2c_davinci_xfer. 253 */ 254 static int 255 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop) 256 { 257 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 258 struct davinci_i2c_platform_data *pdata = dev->dev->platform_data; 259 u32 flag; 260 u16 w; 261 int r; 262 263 if (!pdata) 264 pdata = &davinci_i2c_platform_data_default; 265 /* Introduce a delay, required for some boards (e.g Davinci EVM) */ 266 if (pdata->bus_delay) 267 udelay(pdata->bus_delay); 268 269 /* set the slave address */ 270 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr); 271 272 dev->buf = msg->buf; 273 dev->buf_len = msg->len; 274 dev->stop = stop; 275 276 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len); 277 278 INIT_COMPLETION(dev->cmd_complete); 279 dev->cmd_err = 0; 280 281 /* Take I2C out of reset, configure it as master and set the 282 * start bit */ 283 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST | DAVINCI_I2C_MDR_STT; 284 285 /* if the slave address is ten bit address, enable XA bit */ 286 if (msg->flags & I2C_M_TEN) 287 flag |= DAVINCI_I2C_MDR_XA; 288 if (!(msg->flags & I2C_M_RD)) 289 flag |= DAVINCI_I2C_MDR_TRX; 290 if (stop) 291 flag |= DAVINCI_I2C_MDR_STP; 292 if (msg->len == 0) { 293 flag |= DAVINCI_I2C_MDR_RM; 294 flag &= ~DAVINCI_I2C_MDR_STP; 295 } 296 297 /* Enable receive or transmit interrupts */ 298 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG); 299 if (msg->flags & I2C_M_RD) 300 w |= DAVINCI_I2C_IMR_RRDY; 301 else 302 w |= DAVINCI_I2C_IMR_XRDY; 303 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w); 304 305 dev->terminate = 0; 306 307 /* write the data into mode register */ 308 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 309 310 /* 311 * First byte should be set here, not after interrupt, 312 * because transmit-data-ready interrupt can come before 313 * NACK-interrupt during sending of previous message and 314 * ICDXR may have wrong data 315 */ 316 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) { 317 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++); 318 dev->buf_len--; 319 } 320 321 r = wait_for_completion_interruptible_timeout(&dev->cmd_complete, 322 dev->adapter.timeout); 323 if (r == 0) { 324 dev_err(dev->dev, "controller timed out\n"); 325 i2c_davinci_init(dev); 326 dev->buf_len = 0; 327 return -ETIMEDOUT; 328 } 329 if (dev->buf_len) { 330 /* This should be 0 if all bytes were transferred 331 * or dev->cmd_err denotes an error. 332 * A signal may have aborted the transfer. 333 */ 334 if (r >= 0) { 335 dev_err(dev->dev, "abnormal termination buf_len=%i\n", 336 dev->buf_len); 337 r = -EREMOTEIO; 338 } 339 dev->terminate = 1; 340 wmb(); 341 dev->buf_len = 0; 342 } 343 if (r < 0) 344 return r; 345 346 /* no error */ 347 if (likely(!dev->cmd_err)) 348 return msg->len; 349 350 /* We have an error */ 351 if (dev->cmd_err & DAVINCI_I2C_STR_AL) { 352 i2c_davinci_init(dev); 353 return -EIO; 354 } 355 356 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) { 357 if (msg->flags & I2C_M_IGNORE_NAK) 358 return msg->len; 359 if (stop) { 360 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 361 w |= DAVINCI_I2C_MDR_STP; 362 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 363 } 364 return -EREMOTEIO; 365 } 366 return -EIO; 367 } 368 369 /* 370 * Prepare controller for a transaction and call i2c_davinci_xfer_msg 371 */ 372 static int 373 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 374 { 375 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 376 int i; 377 int ret; 378 379 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); 380 381 ret = i2c_davinci_wait_bus_not_busy(dev, 1); 382 if (ret < 0) { 383 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 384 return ret; 385 } 386 387 for (i = 0; i < num; i++) { 388 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1))); 389 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num, 390 ret); 391 if (ret < 0) 392 return ret; 393 } 394 return num; 395 } 396 397 static u32 i2c_davinci_func(struct i2c_adapter *adap) 398 { 399 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 400 } 401 402 static void terminate_read(struct davinci_i2c_dev *dev) 403 { 404 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 405 w |= DAVINCI_I2C_MDR_NACK; 406 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 407 408 /* Throw away data */ 409 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG); 410 if (!dev->terminate) 411 dev_err(dev->dev, "RDR IRQ while no data requested\n"); 412 } 413 static void terminate_write(struct davinci_i2c_dev *dev) 414 { 415 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); 416 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP; 417 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); 418 419 if (!dev->terminate) 420 dev_dbg(dev->dev, "TDR IRQ while no data to send\n"); 421 } 422 423 /* 424 * Interrupt service routine. This gets called whenever an I2C interrupt 425 * occurs. 426 */ 427 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id) 428 { 429 struct davinci_i2c_dev *dev = dev_id; 430 u32 stat; 431 int count = 0; 432 u16 w; 433 434 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) { 435 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat); 436 if (count++ == 100) { 437 dev_warn(dev->dev, "Too much work in one IRQ\n"); 438 break; 439 } 440 441 switch (stat) { 442 case DAVINCI_I2C_IVR_AL: 443 /* Arbitration lost, must retry */ 444 dev->cmd_err |= DAVINCI_I2C_STR_AL; 445 dev->buf_len = 0; 446 complete(&dev->cmd_complete); 447 break; 448 449 case DAVINCI_I2C_IVR_NACK: 450 dev->cmd_err |= DAVINCI_I2C_STR_NACK; 451 dev->buf_len = 0; 452 complete(&dev->cmd_complete); 453 break; 454 455 case DAVINCI_I2C_IVR_ARDY: 456 davinci_i2c_write_reg(dev, 457 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY); 458 if (((dev->buf_len == 0) && (dev->stop != 0)) || 459 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) { 460 w = davinci_i2c_read_reg(dev, 461 DAVINCI_I2C_MDR_REG); 462 w |= DAVINCI_I2C_MDR_STP; 463 davinci_i2c_write_reg(dev, 464 DAVINCI_I2C_MDR_REG, w); 465 } 466 complete(&dev->cmd_complete); 467 break; 468 469 case DAVINCI_I2C_IVR_RDR: 470 if (dev->buf_len) { 471 *dev->buf++ = 472 davinci_i2c_read_reg(dev, 473 DAVINCI_I2C_DRR_REG); 474 dev->buf_len--; 475 if (dev->buf_len) 476 continue; 477 478 davinci_i2c_write_reg(dev, 479 DAVINCI_I2C_STR_REG, 480 DAVINCI_I2C_IMR_RRDY); 481 } else { 482 /* signal can terminate transfer */ 483 terminate_read(dev); 484 } 485 break; 486 487 case DAVINCI_I2C_IVR_XRDY: 488 if (dev->buf_len) { 489 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, 490 *dev->buf++); 491 dev->buf_len--; 492 if (dev->buf_len) 493 continue; 494 495 w = davinci_i2c_read_reg(dev, 496 DAVINCI_I2C_IMR_REG); 497 w &= ~DAVINCI_I2C_IMR_XRDY; 498 davinci_i2c_write_reg(dev, 499 DAVINCI_I2C_IMR_REG, 500 w); 501 } else { 502 /* signal can terminate transfer */ 503 terminate_write(dev); 504 } 505 break; 506 507 case DAVINCI_I2C_IVR_SCD: 508 davinci_i2c_write_reg(dev, 509 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD); 510 complete(&dev->cmd_complete); 511 break; 512 513 case DAVINCI_I2C_IVR_AAS: 514 dev_dbg(dev->dev, "Address as slave interrupt\n"); 515 break; 516 517 default: 518 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat); 519 break; 520 } 521 } 522 523 return count ? IRQ_HANDLED : IRQ_NONE; 524 } 525 526 static struct i2c_algorithm i2c_davinci_algo = { 527 .master_xfer = i2c_davinci_xfer, 528 .functionality = i2c_davinci_func, 529 }; 530 531 static int davinci_i2c_probe(struct platform_device *pdev) 532 { 533 struct davinci_i2c_dev *dev; 534 struct i2c_adapter *adap; 535 struct resource *mem, *irq, *ioarea; 536 int r; 537 538 /* NOTE: driver uses the static register mapping */ 539 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 540 if (!mem) { 541 dev_err(&pdev->dev, "no mem resource?\n"); 542 return -ENODEV; 543 } 544 545 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 546 if (!irq) { 547 dev_err(&pdev->dev, "no irq resource?\n"); 548 return -ENODEV; 549 } 550 551 ioarea = request_mem_region(mem->start, resource_size(mem), 552 pdev->name); 553 if (!ioarea) { 554 dev_err(&pdev->dev, "I2C region already claimed\n"); 555 return -EBUSY; 556 } 557 558 dev = kzalloc(sizeof(struct davinci_i2c_dev), GFP_KERNEL); 559 if (!dev) { 560 r = -ENOMEM; 561 goto err_release_region; 562 } 563 564 init_completion(&dev->cmd_complete); 565 dev->dev = get_device(&pdev->dev); 566 dev->irq = irq->start; 567 platform_set_drvdata(pdev, dev); 568 569 dev->clk = clk_get(&pdev->dev, NULL); 570 if (IS_ERR(dev->clk)) { 571 r = -ENODEV; 572 goto err_free_mem; 573 } 574 clk_enable(dev->clk); 575 576 dev->base = ioremap(mem->start, resource_size(mem)); 577 if (!dev->base) { 578 r = -EBUSY; 579 goto err_mem_ioremap; 580 } 581 582 i2c_davinci_init(dev); 583 584 r = request_irq(dev->irq, i2c_davinci_isr, 0, pdev->name, dev); 585 if (r) { 586 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); 587 goto err_unuse_clocks; 588 } 589 590 adap = &dev->adapter; 591 i2c_set_adapdata(adap, dev); 592 adap->owner = THIS_MODULE; 593 adap->class = I2C_CLASS_HWMON; 594 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name)); 595 adap->algo = &i2c_davinci_algo; 596 adap->dev.parent = &pdev->dev; 597 adap->timeout = DAVINCI_I2C_TIMEOUT; 598 599 adap->nr = pdev->id; 600 r = i2c_add_numbered_adapter(adap); 601 if (r) { 602 dev_err(&pdev->dev, "failure adding adapter\n"); 603 goto err_free_irq; 604 } 605 606 return 0; 607 608 err_free_irq: 609 free_irq(dev->irq, dev); 610 err_unuse_clocks: 611 iounmap(dev->base); 612 err_mem_ioremap: 613 clk_disable(dev->clk); 614 clk_put(dev->clk); 615 dev->clk = NULL; 616 err_free_mem: 617 platform_set_drvdata(pdev, NULL); 618 put_device(&pdev->dev); 619 kfree(dev); 620 err_release_region: 621 release_mem_region(mem->start, resource_size(mem)); 622 623 return r; 624 } 625 626 static int davinci_i2c_remove(struct platform_device *pdev) 627 { 628 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev); 629 struct resource *mem; 630 631 platform_set_drvdata(pdev, NULL); 632 i2c_del_adapter(&dev->adapter); 633 put_device(&pdev->dev); 634 635 clk_disable(dev->clk); 636 clk_put(dev->clk); 637 dev->clk = NULL; 638 639 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0); 640 free_irq(IRQ_I2C, dev); 641 iounmap(dev->base); 642 kfree(dev); 643 644 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 645 release_mem_region(mem->start, resource_size(mem)); 646 return 0; 647 } 648 649 #ifdef CONFIG_PM 650 static int davinci_i2c_suspend(struct device *dev) 651 { 652 struct platform_device *pdev = to_platform_device(dev); 653 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 654 655 /* put I2C into reset */ 656 davinci_i2c_reset_ctrl(i2c_dev, 0); 657 clk_disable(i2c_dev->clk); 658 659 return 0; 660 } 661 662 static int davinci_i2c_resume(struct device *dev) 663 { 664 struct platform_device *pdev = to_platform_device(dev); 665 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 666 667 clk_enable(i2c_dev->clk); 668 /* take I2C out of reset */ 669 davinci_i2c_reset_ctrl(i2c_dev, 1); 670 671 return 0; 672 } 673 674 static const struct dev_pm_ops davinci_i2c_pm = { 675 .suspend = davinci_i2c_suspend, 676 .resume = davinci_i2c_resume, 677 }; 678 679 #define davinci_i2c_pm_ops (&davinci_i2c_pm) 680 #else 681 #define davinci_i2c_pm_ops NULL 682 #endif 683 684 /* work with hotplug and coldplug */ 685 MODULE_ALIAS("platform:i2c_davinci"); 686 687 static struct platform_driver davinci_i2c_driver = { 688 .probe = davinci_i2c_probe, 689 .remove = davinci_i2c_remove, 690 .driver = { 691 .name = "i2c_davinci", 692 .owner = THIS_MODULE, 693 .pm = davinci_i2c_pm_ops, 694 }, 695 }; 696 697 /* I2C may be needed to bring up other drivers */ 698 static int __init davinci_i2c_init_driver(void) 699 { 700 return platform_driver_register(&davinci_i2c_driver); 701 } 702 subsys_initcall(davinci_i2c_init_driver); 703 704 static void __exit davinci_i2c_exit_driver(void) 705 { 706 platform_driver_unregister(&davinci_i2c_driver); 707 } 708 module_exit(davinci_i2c_exit_driver); 709 710 MODULE_AUTHOR("Texas Instruments India"); 711 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter"); 712 MODULE_LICENSE("GPL"); 713