1 /* 2 * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface 3 * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com> 4 * 5 * 2.6 port by Matt Porter <mporter@kernel.crashing.org> 6 * 7 * The documentation describes this as an SMBus controller, but it doesn't 8 * understand any of the SMBus protocol in hardware. It's really an I2C 9 * controller that could emulate most of the SMBus in software. 10 * 11 * This is just a skeleton adapter to use with the Au1550 PSC 12 * algorithm. It was developed for the Pb1550, but will work with 13 * any Au1550 board that has a similar PSC configuration. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 2 18 * of the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 28 */ 29 30 #include <linux/config.h> 31 #include <linux/delay.h> 32 #include <linux/kernel.h> 33 #include <linux/module.h> 34 #include <linux/init.h> 35 #include <linux/errno.h> 36 #include <linux/i2c.h> 37 38 #include <asm/mach-au1x00/au1000.h> 39 #include <asm/mach-pb1x00/pb1550.h> 40 #include <asm/mach-au1x00/au1xxx_psc.h> 41 42 #include "i2c-au1550.h" 43 44 static int 45 wait_xfer_done(struct i2c_au1550_data *adap) 46 { 47 u32 stat; 48 int i; 49 volatile psc_smb_t *sp; 50 51 sp = (volatile psc_smb_t *)(adap->psc_base); 52 53 /* Wait for Tx FIFO Underflow. 54 */ 55 for (i = 0; i < adap->xfer_timeout; i++) { 56 stat = sp->psc_smbevnt; 57 au_sync(); 58 if ((stat & PSC_SMBEVNT_TU) != 0) { 59 /* Clear it. */ 60 sp->psc_smbevnt = PSC_SMBEVNT_TU; 61 au_sync(); 62 return 0; 63 } 64 udelay(1); 65 } 66 67 return -ETIMEDOUT; 68 } 69 70 static int 71 wait_ack(struct i2c_au1550_data *adap) 72 { 73 u32 stat; 74 volatile psc_smb_t *sp; 75 76 if (wait_xfer_done(adap)) 77 return -ETIMEDOUT; 78 79 sp = (volatile psc_smb_t *)(adap->psc_base); 80 81 stat = sp->psc_smbevnt; 82 au_sync(); 83 84 if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0) 85 return -ETIMEDOUT; 86 87 return 0; 88 } 89 90 static int 91 wait_master_done(struct i2c_au1550_data *adap) 92 { 93 u32 stat; 94 int i; 95 volatile psc_smb_t *sp; 96 97 sp = (volatile psc_smb_t *)(adap->psc_base); 98 99 /* Wait for Master Done. 100 */ 101 for (i = 0; i < adap->xfer_timeout; i++) { 102 stat = sp->psc_smbevnt; 103 au_sync(); 104 if ((stat & PSC_SMBEVNT_MD) != 0) 105 return 0; 106 udelay(1); 107 } 108 109 return -ETIMEDOUT; 110 } 111 112 static int 113 do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd) 114 { 115 volatile psc_smb_t *sp; 116 u32 stat; 117 118 sp = (volatile psc_smb_t *)(adap->psc_base); 119 120 /* Reset the FIFOs, clear events. 121 */ 122 sp->psc_smbpcr = PSC_SMBPCR_DC; 123 sp->psc_smbevnt = PSC_SMBEVNT_ALLCLR; 124 au_sync(); 125 do { 126 stat = sp->psc_smbpcr; 127 au_sync(); 128 } while ((stat & PSC_SMBPCR_DC) != 0); 129 130 /* Write out the i2c chip address and specify operation 131 */ 132 addr <<= 1; 133 if (rd) 134 addr |= 1; 135 136 /* Put byte into fifo, start up master. 137 */ 138 sp->psc_smbtxrx = addr; 139 au_sync(); 140 sp->psc_smbpcr = PSC_SMBPCR_MS; 141 au_sync(); 142 if (wait_ack(adap)) 143 return -EIO; 144 return 0; 145 } 146 147 static u32 148 wait_for_rx_byte(struct i2c_au1550_data *adap, u32 *ret_data) 149 { 150 int j; 151 u32 data, stat; 152 volatile psc_smb_t *sp; 153 154 if (wait_xfer_done(adap)) 155 return -EIO; 156 157 sp = (volatile psc_smb_t *)(adap->psc_base); 158 159 j = adap->xfer_timeout * 100; 160 do { 161 j--; 162 if (j <= 0) 163 return -EIO; 164 165 stat = sp->psc_smbstat; 166 au_sync(); 167 if ((stat & PSC_SMBSTAT_RE) == 0) 168 j = 0; 169 else 170 udelay(1); 171 } while (j > 0); 172 data = sp->psc_smbtxrx; 173 au_sync(); 174 *ret_data = data; 175 176 return 0; 177 } 178 179 static int 180 i2c_read(struct i2c_au1550_data *adap, unsigned char *buf, 181 unsigned int len) 182 { 183 int i; 184 u32 data; 185 volatile psc_smb_t *sp; 186 187 if (len == 0) 188 return 0; 189 190 /* A read is performed by stuffing the transmit fifo with 191 * zero bytes for timing, waiting for bytes to appear in the 192 * receive fifo, then reading the bytes. 193 */ 194 195 sp = (volatile psc_smb_t *)(adap->psc_base); 196 197 i = 0; 198 while (i < (len-1)) { 199 sp->psc_smbtxrx = 0; 200 au_sync(); 201 if (wait_for_rx_byte(adap, &data)) 202 return -EIO; 203 204 buf[i] = data; 205 i++; 206 } 207 208 /* The last byte has to indicate transfer done. 209 */ 210 sp->psc_smbtxrx = PSC_SMBTXRX_STP; 211 au_sync(); 212 if (wait_master_done(adap)) 213 return -EIO; 214 215 data = sp->psc_smbtxrx; 216 au_sync(); 217 buf[i] = data; 218 return 0; 219 } 220 221 static int 222 i2c_write(struct i2c_au1550_data *adap, unsigned char *buf, 223 unsigned int len) 224 { 225 int i; 226 u32 data; 227 volatile psc_smb_t *sp; 228 229 if (len == 0) 230 return 0; 231 232 sp = (volatile psc_smb_t *)(adap->psc_base); 233 234 i = 0; 235 while (i < (len-1)) { 236 data = buf[i]; 237 sp->psc_smbtxrx = data; 238 au_sync(); 239 if (wait_ack(adap)) 240 return -EIO; 241 i++; 242 } 243 244 /* The last byte has to indicate transfer done. 245 */ 246 data = buf[i]; 247 data |= PSC_SMBTXRX_STP; 248 sp->psc_smbtxrx = data; 249 au_sync(); 250 if (wait_master_done(adap)) 251 return -EIO; 252 return 0; 253 } 254 255 static int 256 au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) 257 { 258 struct i2c_au1550_data *adap = i2c_adap->algo_data; 259 struct i2c_msg *p; 260 int i, err = 0; 261 262 for (i = 0; !err && i < num; i++) { 263 p = &msgs[i]; 264 err = do_address(adap, p->addr, p->flags & I2C_M_RD); 265 if (err || !p->len) 266 continue; 267 if (p->flags & I2C_M_RD) 268 err = i2c_read(adap, p->buf, p->len); 269 else 270 err = i2c_write(adap, p->buf, p->len); 271 } 272 273 /* Return the number of messages processed, or the error code. 274 */ 275 if (err == 0) 276 err = num; 277 return err; 278 } 279 280 static u32 281 au1550_func(struct i2c_adapter *adap) 282 { 283 return I2C_FUNC_I2C; 284 } 285 286 static struct i2c_algorithm au1550_algo = { 287 .name = "Au1550 algorithm", 288 .id = I2C_ALGO_AU1550, 289 .master_xfer = au1550_xfer, 290 .functionality = au1550_func, 291 }; 292 293 /* 294 * registering functions to load algorithms at runtime 295 * Prior to calling us, the 50MHz clock frequency and routing 296 * must have been set up for the PSC indicated by the adapter. 297 */ 298 int 299 i2c_au1550_add_bus(struct i2c_adapter *i2c_adap) 300 { 301 struct i2c_au1550_data *adap = i2c_adap->algo_data; 302 volatile psc_smb_t *sp; 303 u32 stat; 304 305 i2c_adap->algo = &au1550_algo; 306 307 /* Now, set up the PSC for SMBus PIO mode. 308 */ 309 sp = (volatile psc_smb_t *)(adap->psc_base); 310 sp->psc_ctrl = PSC_CTRL_DISABLE; 311 au_sync(); 312 sp->psc_sel = PSC_SEL_PS_SMBUSMODE; 313 sp->psc_smbcfg = 0; 314 au_sync(); 315 sp->psc_ctrl = PSC_CTRL_ENABLE; 316 au_sync(); 317 do { 318 stat = sp->psc_smbstat; 319 au_sync(); 320 } while ((stat & PSC_SMBSTAT_SR) == 0); 321 322 sp->psc_smbcfg = (PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | 323 PSC_SMBCFG_DD_DISABLE); 324 325 /* Divide by 8 to get a 6.25 MHz clock. The later protocol 326 * timings are based on this clock. 327 */ 328 sp->psc_smbcfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8); 329 sp->psc_smbmsk = PSC_SMBMSK_ALLMASK; 330 au_sync(); 331 332 /* Set the protocol timer values. See Table 71 in the 333 * Au1550 Data Book for standard timing values. 334 */ 335 sp->psc_smbtmr = PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \ 336 PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \ 337 PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \ 338 PSC_SMBTMR_SET_CH(15); 339 au_sync(); 340 341 sp->psc_smbcfg |= PSC_SMBCFG_DE_ENABLE; 342 do { 343 stat = sp->psc_smbstat; 344 au_sync(); 345 } while ((stat & PSC_SMBSTAT_DR) == 0); 346 347 return i2c_add_adapter(i2c_adap); 348 } 349 350 351 int 352 i2c_au1550_del_bus(struct i2c_adapter *adap) 353 { 354 return i2c_del_adapter(adap); 355 } 356 357 static int 358 pb1550_reg(struct i2c_client *client) 359 { 360 return 0; 361 } 362 363 static int 364 pb1550_unreg(struct i2c_client *client) 365 { 366 return 0; 367 } 368 369 static struct i2c_au1550_data pb1550_i2c_info = { 370 SMBUS_PSC_BASE, 200, 200 371 }; 372 373 static struct i2c_adapter pb1550_board_adapter = { 374 name: "pb1550 adapter", 375 id: I2C_HW_AU1550_PSC, 376 algo: NULL, 377 algo_data: &pb1550_i2c_info, 378 client_register: pb1550_reg, 379 client_unregister: pb1550_unreg, 380 }; 381 382 /* BIG hack to support the control interface on the Wolfson WM8731 383 * audio codec on the Pb1550 board. We get an address and two data 384 * bytes to write, create an i2c message, and send it across the 385 * i2c transfer function. We do this here because we have access to 386 * the i2c adapter structure. 387 */ 388 static struct i2c_msg wm_i2c_msg; /* We don't want this stuff on the stack */ 389 static u8 i2cbuf[2]; 390 391 int 392 pb1550_wm_codec_write(u8 addr, u8 reg, u8 val) 393 { 394 wm_i2c_msg.addr = addr; 395 wm_i2c_msg.flags = 0; 396 wm_i2c_msg.buf = i2cbuf; 397 wm_i2c_msg.len = 2; 398 i2cbuf[0] = reg; 399 i2cbuf[1] = val; 400 401 return pb1550_board_adapter.algo->master_xfer(&pb1550_board_adapter, &wm_i2c_msg, 1); 402 } 403 404 static int __init 405 i2c_au1550_init(void) 406 { 407 printk(KERN_INFO "Au1550 I2C: "); 408 409 /* This is where we would set up a 50MHz clock source 410 * and routing. On the Pb1550, the SMBus is PSC2, which 411 * uses a shared clock with USB. This has been already 412 * configured by Yamon as a 48MHz clock, close enough 413 * for our work. 414 */ 415 if (i2c_au1550_add_bus(&pb1550_board_adapter) < 0) { 416 printk("failed to initialize.\n"); 417 return -ENODEV; 418 } 419 420 printk("initialized.\n"); 421 return 0; 422 } 423 424 static void __exit 425 i2c_au1550_exit(void) 426 { 427 i2c_au1550_del_bus(&pb1550_board_adapter); 428 } 429 430 MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC."); 431 MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550"); 432 MODULE_LICENSE("GPL"); 433 434 module_init (i2c_au1550_init); 435 module_exit (i2c_au1550_exit); 436