1*b27a6a3fSAlexander Shishkin /* 2*b27a6a3fSAlexander Shishkin * Intel(R) Trace Hub Global Trace Hub (GTH) data structures 3*b27a6a3fSAlexander Shishkin * 4*b27a6a3fSAlexander Shishkin * Copyright (C) 2014-2015 Intel Corporation. 5*b27a6a3fSAlexander Shishkin * 6*b27a6a3fSAlexander Shishkin * This program is free software; you can redistribute it and/or modify it 7*b27a6a3fSAlexander Shishkin * under the terms and conditions of the GNU General Public License, 8*b27a6a3fSAlexander Shishkin * version 2, as published by the Free Software Foundation. 9*b27a6a3fSAlexander Shishkin * 10*b27a6a3fSAlexander Shishkin * This program is distributed in the hope it will be useful, but WITHOUT 11*b27a6a3fSAlexander Shishkin * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12*b27a6a3fSAlexander Shishkin * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13*b27a6a3fSAlexander Shishkin * more details. 14*b27a6a3fSAlexander Shishkin */ 15*b27a6a3fSAlexander Shishkin 16*b27a6a3fSAlexander Shishkin #ifndef __INTEL_TH_GTH_H__ 17*b27a6a3fSAlexander Shishkin #define __INTEL_TH_GTH_H__ 18*b27a6a3fSAlexander Shishkin 19*b27a6a3fSAlexander Shishkin /* Map output port parameter bits to symbolic names */ 20*b27a6a3fSAlexander Shishkin #define TH_OUTPUT_PARM(name) \ 21*b27a6a3fSAlexander Shishkin TH_OUTPUT_ ## name 22*b27a6a3fSAlexander Shishkin 23*b27a6a3fSAlexander Shishkin enum intel_th_output_parm { 24*b27a6a3fSAlexander Shishkin /* output port type */ 25*b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(port), 26*b27a6a3fSAlexander Shishkin /* generate NULL packet */ 27*b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(null), 28*b27a6a3fSAlexander Shishkin /* packet drop */ 29*b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(drop), 30*b27a6a3fSAlexander Shishkin /* port in reset state */ 31*b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(reset), 32*b27a6a3fSAlexander Shishkin /* flush out data */ 33*b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(flush), 34*b27a6a3fSAlexander Shishkin /* mainenance packet frequency */ 35*b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(smcfreq), 36*b27a6a3fSAlexander Shishkin }; 37*b27a6a3fSAlexander Shishkin 38*b27a6a3fSAlexander Shishkin /* 39*b27a6a3fSAlexander Shishkin * Register offsets 40*b27a6a3fSAlexander Shishkin */ 41*b27a6a3fSAlexander Shishkin enum { 42*b27a6a3fSAlexander Shishkin REG_GTH_GTHOPT0 = 0x00, /* Output ports 0..3 config */ 43*b27a6a3fSAlexander Shishkin REG_GTH_GTHOPT1 = 0x04, /* Output ports 4..7 config */ 44*b27a6a3fSAlexander Shishkin REG_GTH_SWDEST0 = 0x08, /* Switching destination masters 0..7 */ 45*b27a6a3fSAlexander Shishkin REG_GTH_GSWTDEST = 0x88, /* Global sw trace destination */ 46*b27a6a3fSAlexander Shishkin REG_GTH_SMCR0 = 0x9c, /* STP mainenance for ports 0/1 */ 47*b27a6a3fSAlexander Shishkin REG_GTH_SMCR1 = 0xa0, /* STP mainenance for ports 2/3 */ 48*b27a6a3fSAlexander Shishkin REG_GTH_SMCR2 = 0xa4, /* STP mainenance for ports 4/5 */ 49*b27a6a3fSAlexander Shishkin REG_GTH_SMCR3 = 0xa8, /* STP mainenance for ports 6/7 */ 50*b27a6a3fSAlexander Shishkin REG_GTH_SCR = 0xc8, /* Source control (storeEn override) */ 51*b27a6a3fSAlexander Shishkin REG_GTH_STAT = 0xd4, /* GTH status */ 52*b27a6a3fSAlexander Shishkin REG_GTH_SCR2 = 0xd8, /* Source control (force storeEn off) */ 53*b27a6a3fSAlexander Shishkin REG_GTH_DESTOVR = 0xdc, /* Destination override */ 54*b27a6a3fSAlexander Shishkin REG_GTH_SCRPD0 = 0xe0, /* ScratchPad[0] */ 55*b27a6a3fSAlexander Shishkin REG_GTH_SCRPD1 = 0xe4, /* ScratchPad[1] */ 56*b27a6a3fSAlexander Shishkin REG_GTH_SCRPD2 = 0xe8, /* ScratchPad[2] */ 57*b27a6a3fSAlexander Shishkin REG_GTH_SCRPD3 = 0xec, /* ScratchPad[3] */ 58*b27a6a3fSAlexander Shishkin }; 59*b27a6a3fSAlexander Shishkin 60*b27a6a3fSAlexander Shishkin /* Externall debugger is using Intel TH */ 61*b27a6a3fSAlexander Shishkin #define SCRPD_DEBUGGER_IN_USE BIT(24) 62*b27a6a3fSAlexander Shishkin 63*b27a6a3fSAlexander Shishkin /* waiting for Pipeline Empty bit(s) to assert for GTH */ 64*b27a6a3fSAlexander Shishkin #define GTH_PLE_WAITLOOP_DEPTH 10000 65*b27a6a3fSAlexander Shishkin 66*b27a6a3fSAlexander Shishkin #endif /* __INTEL_TH_GTH_H__ */ 67