1b27a6a3fSAlexander Shishkin /* 2b27a6a3fSAlexander Shishkin * Intel(R) Trace Hub Global Trace Hub (GTH) data structures 3b27a6a3fSAlexander Shishkin * 4b27a6a3fSAlexander Shishkin * Copyright (C) 2014-2015 Intel Corporation. 5b27a6a3fSAlexander Shishkin * 6b27a6a3fSAlexander Shishkin * This program is free software; you can redistribute it and/or modify it 7b27a6a3fSAlexander Shishkin * under the terms and conditions of the GNU General Public License, 8b27a6a3fSAlexander Shishkin * version 2, as published by the Free Software Foundation. 9b27a6a3fSAlexander Shishkin * 10b27a6a3fSAlexander Shishkin * This program is distributed in the hope it will be useful, but WITHOUT 11b27a6a3fSAlexander Shishkin * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12b27a6a3fSAlexander Shishkin * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13b27a6a3fSAlexander Shishkin * more details. 14b27a6a3fSAlexander Shishkin */ 15b27a6a3fSAlexander Shishkin 16b27a6a3fSAlexander Shishkin #ifndef __INTEL_TH_GTH_H__ 17b27a6a3fSAlexander Shishkin #define __INTEL_TH_GTH_H__ 18b27a6a3fSAlexander Shishkin 19b27a6a3fSAlexander Shishkin /* Map output port parameter bits to symbolic names */ 20b27a6a3fSAlexander Shishkin #define TH_OUTPUT_PARM(name) \ 21b27a6a3fSAlexander Shishkin TH_OUTPUT_ ## name 22b27a6a3fSAlexander Shishkin 23b27a6a3fSAlexander Shishkin enum intel_th_output_parm { 24b27a6a3fSAlexander Shishkin /* output port type */ 25b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(port), 26b27a6a3fSAlexander Shishkin /* generate NULL packet */ 27b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(null), 28b27a6a3fSAlexander Shishkin /* packet drop */ 29b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(drop), 30b27a6a3fSAlexander Shishkin /* port in reset state */ 31b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(reset), 32b27a6a3fSAlexander Shishkin /* flush out data */ 33b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(flush), 34b27a6a3fSAlexander Shishkin /* mainenance packet frequency */ 35b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(smcfreq), 36b27a6a3fSAlexander Shishkin }; 37b27a6a3fSAlexander Shishkin 38b27a6a3fSAlexander Shishkin /* 39b27a6a3fSAlexander Shishkin * Register offsets 40b27a6a3fSAlexander Shishkin */ 41b27a6a3fSAlexander Shishkin enum { 42b27a6a3fSAlexander Shishkin REG_GTH_GTHOPT0 = 0x00, /* Output ports 0..3 config */ 43b27a6a3fSAlexander Shishkin REG_GTH_GTHOPT1 = 0x04, /* Output ports 4..7 config */ 44b27a6a3fSAlexander Shishkin REG_GTH_SWDEST0 = 0x08, /* Switching destination masters 0..7 */ 45b27a6a3fSAlexander Shishkin REG_GTH_GSWTDEST = 0x88, /* Global sw trace destination */ 46b27a6a3fSAlexander Shishkin REG_GTH_SMCR0 = 0x9c, /* STP mainenance for ports 0/1 */ 47b27a6a3fSAlexander Shishkin REG_GTH_SMCR1 = 0xa0, /* STP mainenance for ports 2/3 */ 48b27a6a3fSAlexander Shishkin REG_GTH_SMCR2 = 0xa4, /* STP mainenance for ports 4/5 */ 49b27a6a3fSAlexander Shishkin REG_GTH_SMCR3 = 0xa8, /* STP mainenance for ports 6/7 */ 50b27a6a3fSAlexander Shishkin REG_GTH_SCR = 0xc8, /* Source control (storeEn override) */ 51b27a6a3fSAlexander Shishkin REG_GTH_STAT = 0xd4, /* GTH status */ 52b27a6a3fSAlexander Shishkin REG_GTH_SCR2 = 0xd8, /* Source control (force storeEn off) */ 53b27a6a3fSAlexander Shishkin REG_GTH_DESTOVR = 0xdc, /* Destination override */ 54b27a6a3fSAlexander Shishkin REG_GTH_SCRPD0 = 0xe0, /* ScratchPad[0] */ 55b27a6a3fSAlexander Shishkin REG_GTH_SCRPD1 = 0xe4, /* ScratchPad[1] */ 56b27a6a3fSAlexander Shishkin REG_GTH_SCRPD2 = 0xe8, /* ScratchPad[2] */ 57b27a6a3fSAlexander Shishkin REG_GTH_SCRPD3 = 0xec, /* ScratchPad[3] */ 58*a0e7df33SAlexander Shishkin REG_TSCU_TSUCTRL = 0x2000, /* TSCU control register */ 59*a0e7df33SAlexander Shishkin REG_TSCU_TSCUSTAT = 0x2004, /* TSCU status register */ 60b27a6a3fSAlexander Shishkin }; 61b27a6a3fSAlexander Shishkin 62b27a6a3fSAlexander Shishkin /* waiting for Pipeline Empty bit(s) to assert for GTH */ 63b27a6a3fSAlexander Shishkin #define GTH_PLE_WAITLOOP_DEPTH 10000 64b27a6a3fSAlexander Shishkin 65*a0e7df33SAlexander Shishkin #define TSUCTRL_CTCRESYNC BIT(0) 66*a0e7df33SAlexander Shishkin #define TSCUSTAT_CTCSYNCING BIT(1) 67*a0e7df33SAlexander Shishkin 68b27a6a3fSAlexander Shishkin #endif /* __INTEL_TH_GTH_H__ */ 69