1*50352fa7SAlexander Shishkin /* SPDX-License-Identifier: GPL-2.0 */ 2b27a6a3fSAlexander Shishkin /* 3b27a6a3fSAlexander Shishkin * Intel(R) Trace Hub Global Trace Hub (GTH) data structures 4b27a6a3fSAlexander Shishkin * 5b27a6a3fSAlexander Shishkin * Copyright (C) 2014-2015 Intel Corporation. 6b27a6a3fSAlexander Shishkin */ 7b27a6a3fSAlexander Shishkin 8b27a6a3fSAlexander Shishkin #ifndef __INTEL_TH_GTH_H__ 9b27a6a3fSAlexander Shishkin #define __INTEL_TH_GTH_H__ 10b27a6a3fSAlexander Shishkin 11b27a6a3fSAlexander Shishkin /* Map output port parameter bits to symbolic names */ 12b27a6a3fSAlexander Shishkin #define TH_OUTPUT_PARM(name) \ 13b27a6a3fSAlexander Shishkin TH_OUTPUT_ ## name 14b27a6a3fSAlexander Shishkin 15b27a6a3fSAlexander Shishkin enum intel_th_output_parm { 16b27a6a3fSAlexander Shishkin /* output port type */ 17b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(port), 18b27a6a3fSAlexander Shishkin /* generate NULL packet */ 19b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(null), 20b27a6a3fSAlexander Shishkin /* packet drop */ 21b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(drop), 22b27a6a3fSAlexander Shishkin /* port in reset state */ 23b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(reset), 24b27a6a3fSAlexander Shishkin /* flush out data */ 25b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(flush), 26b27a6a3fSAlexander Shishkin /* mainenance packet frequency */ 27b27a6a3fSAlexander Shishkin TH_OUTPUT_PARM(smcfreq), 28b27a6a3fSAlexander Shishkin }; 29b27a6a3fSAlexander Shishkin 30b27a6a3fSAlexander Shishkin /* 31b27a6a3fSAlexander Shishkin * Register offsets 32b27a6a3fSAlexander Shishkin */ 33b27a6a3fSAlexander Shishkin enum { 34b27a6a3fSAlexander Shishkin REG_GTH_GTHOPT0 = 0x00, /* Output ports 0..3 config */ 35b27a6a3fSAlexander Shishkin REG_GTH_GTHOPT1 = 0x04, /* Output ports 4..7 config */ 36b27a6a3fSAlexander Shishkin REG_GTH_SWDEST0 = 0x08, /* Switching destination masters 0..7 */ 37b27a6a3fSAlexander Shishkin REG_GTH_GSWTDEST = 0x88, /* Global sw trace destination */ 38b27a6a3fSAlexander Shishkin REG_GTH_SMCR0 = 0x9c, /* STP mainenance for ports 0/1 */ 39b27a6a3fSAlexander Shishkin REG_GTH_SMCR1 = 0xa0, /* STP mainenance for ports 2/3 */ 40b27a6a3fSAlexander Shishkin REG_GTH_SMCR2 = 0xa4, /* STP mainenance for ports 4/5 */ 41b27a6a3fSAlexander Shishkin REG_GTH_SMCR3 = 0xa8, /* STP mainenance for ports 6/7 */ 42b27a6a3fSAlexander Shishkin REG_GTH_SCR = 0xc8, /* Source control (storeEn override) */ 43b27a6a3fSAlexander Shishkin REG_GTH_STAT = 0xd4, /* GTH status */ 44b27a6a3fSAlexander Shishkin REG_GTH_SCR2 = 0xd8, /* Source control (force storeEn off) */ 45b27a6a3fSAlexander Shishkin REG_GTH_DESTOVR = 0xdc, /* Destination override */ 46b27a6a3fSAlexander Shishkin REG_GTH_SCRPD0 = 0xe0, /* ScratchPad[0] */ 47b27a6a3fSAlexander Shishkin REG_GTH_SCRPD1 = 0xe4, /* ScratchPad[1] */ 48b27a6a3fSAlexander Shishkin REG_GTH_SCRPD2 = 0xe8, /* ScratchPad[2] */ 49b27a6a3fSAlexander Shishkin REG_GTH_SCRPD3 = 0xec, /* ScratchPad[3] */ 50a0e7df33SAlexander Shishkin REG_TSCU_TSUCTRL = 0x2000, /* TSCU control register */ 51a0e7df33SAlexander Shishkin REG_TSCU_TSCUSTAT = 0x2004, /* TSCU status register */ 52b27a6a3fSAlexander Shishkin }; 53b27a6a3fSAlexander Shishkin 54b27a6a3fSAlexander Shishkin /* waiting for Pipeline Empty bit(s) to assert for GTH */ 55b27a6a3fSAlexander Shishkin #define GTH_PLE_WAITLOOP_DEPTH 10000 56b27a6a3fSAlexander Shishkin 57a0e7df33SAlexander Shishkin #define TSUCTRL_CTCRESYNC BIT(0) 58a0e7df33SAlexander Shishkin #define TSCUSTAT_CTCSYNCING BIT(1) 59a0e7df33SAlexander Shishkin 60b27a6a3fSAlexander Shishkin #endif /* __INTEL_TH_GTH_H__ */ 61