1b3c71626SMao Jinlong /* SPDX-License-Identifier: GPL-2.0 */ 2b3c71626SMao Jinlong /* 3b3c71626SMao Jinlong * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4b3c71626SMao Jinlong */ 5b3c71626SMao Jinlong 6b3c71626SMao Jinlong #ifndef _CORESIGHT_CORESIGHT_TPDM_H 7b3c71626SMao Jinlong #define _CORESIGHT_CORESIGHT_TPDM_H 8b3c71626SMao Jinlong 91f00465dSMao Jinlong /* The max number of the datasets that TPDM supports */ 101f00465dSMao Jinlong #define TPDM_DATASETS 7 111f00465dSMao Jinlong 121f00465dSMao Jinlong /* DSB Subunit Registers */ 131f00465dSMao Jinlong #define TPDM_DSB_CR (0x780) 141f00465dSMao Jinlong /* Enable bit for DSB subunit */ 151f00465dSMao Jinlong #define TPDM_DSB_CR_ENA BIT(0) 161f00465dSMao Jinlong 17*436cca9aSMao Jinlong /* TPDM integration test registers */ 18*436cca9aSMao Jinlong #define TPDM_ITATBCNTRL (0xEF0) 19*436cca9aSMao Jinlong #define TPDM_ITCNTRL (0xF00) 20*436cca9aSMao Jinlong 21*436cca9aSMao Jinlong /* Register value for integration test */ 22*436cca9aSMao Jinlong #define ATBCNTRL_VAL_32 0xC00F1409 23*436cca9aSMao Jinlong #define ATBCNTRL_VAL_64 0xC01F1409 24*436cca9aSMao Jinlong 25*436cca9aSMao Jinlong /* 26*436cca9aSMao Jinlong * Number of cycles to write value when 27*436cca9aSMao Jinlong * integration test. 28*436cca9aSMao Jinlong */ 29*436cca9aSMao Jinlong #define INTEGRATION_TEST_CYCLE 10 30*436cca9aSMao Jinlong 311f00465dSMao Jinlong /** 321f00465dSMao Jinlong * The bits of PERIPHIDR0 register. 331f00465dSMao Jinlong * The fields [6:0] of PERIPHIDR0 are used to determine what 341f00465dSMao Jinlong * interfaces and subunits are present on a given TPDM. 351f00465dSMao Jinlong * 361f00465dSMao Jinlong * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0 371f00465dSMao Jinlong * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0 381f00465dSMao Jinlong */ 391f00465dSMao Jinlong 401f00465dSMao Jinlong #define TPDM_PIDR0_DS_IMPDEF BIT(0) 411f00465dSMao Jinlong #define TPDM_PIDR0_DS_DSB BIT(1) 421f00465dSMao Jinlong 43b3c71626SMao Jinlong /** 44b3c71626SMao Jinlong * struct tpdm_drvdata - specifics associated to an TPDM component 45b3c71626SMao Jinlong * @base: memory mapped base address for this component. 46b3c71626SMao Jinlong * @dev: The device entity associated to this component. 47b3c71626SMao Jinlong * @csdev: component vitals needed by the framework. 48b3c71626SMao Jinlong * @spinlock: lock for the drvdata value. 49b3c71626SMao Jinlong * @enable: enable status of the component. 501f00465dSMao Jinlong * @datasets: The datasets types present of the TPDM. 51b3c71626SMao Jinlong */ 52b3c71626SMao Jinlong 53b3c71626SMao Jinlong struct tpdm_drvdata { 54b3c71626SMao Jinlong void __iomem *base; 55b3c71626SMao Jinlong struct device *dev; 56b3c71626SMao Jinlong struct coresight_device *csdev; 57b3c71626SMao Jinlong spinlock_t spinlock; 58b3c71626SMao Jinlong bool enable; 591f00465dSMao Jinlong unsigned long datasets; 60b3c71626SMao Jinlong }; 61b3c71626SMao Jinlong 62b3c71626SMao Jinlong #endif /* _CORESIGHT_CORESIGHT_TPDM_H */ 63