1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. 4 * 5 * Description: CoreSight System Trace Macrocell driver 6 * 7 * Initial implementation by Pratik Patel 8 * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org> 9 * 10 * Serious refactoring, code cleanup and upgrading to the Coresight upstream 11 * framework by Mathieu Poirier 12 * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org> 13 * 14 * Guaranteed timing and support for various packet type coming from the 15 * generic STM API by Chunyan Zhang 16 * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org> 17 */ 18 #include <asm/local.h> 19 #include <linux/acpi.h> 20 #include <linux/amba/bus.h> 21 #include <linux/bitmap.h> 22 #include <linux/clk.h> 23 #include <linux/coresight.h> 24 #include <linux/coresight-stm.h> 25 #include <linux/err.h> 26 #include <linux/kernel.h> 27 #include <linux/moduleparam.h> 28 #include <linux/of_address.h> 29 #include <linux/perf_event.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/stm.h> 32 33 #include "coresight-priv.h" 34 #include "coresight-trace-id.h" 35 36 #define STMDMASTARTR 0xc04 37 #define STMDMASTOPR 0xc08 38 #define STMDMASTATR 0xc0c 39 #define STMDMACTLR 0xc10 40 #define STMDMAIDR 0xcfc 41 #define STMHEER 0xd00 42 #define STMHETER 0xd20 43 #define STMHEBSR 0xd60 44 #define STMHEMCR 0xd64 45 #define STMHEMASTR 0xdf4 46 #define STMHEFEAT1R 0xdf8 47 #define STMHEIDR 0xdfc 48 #define STMSPER 0xe00 49 #define STMSPTER 0xe20 50 #define STMPRIVMASKR 0xe40 51 #define STMSPSCR 0xe60 52 #define STMSPMSCR 0xe64 53 #define STMSPOVERRIDER 0xe68 54 #define STMSPMOVERRIDER 0xe6c 55 #define STMSPTRIGCSR 0xe70 56 #define STMTCSR 0xe80 57 #define STMTSSTIMR 0xe84 58 #define STMTSFREQR 0xe8c 59 #define STMSYNCR 0xe90 60 #define STMAUXCR 0xe94 61 #define STMSPFEAT1R 0xea0 62 #define STMSPFEAT2R 0xea4 63 #define STMSPFEAT3R 0xea8 64 #define STMITTRIGGER 0xee8 65 #define STMITATBDATA0 0xeec 66 #define STMITATBCTR2 0xef0 67 #define STMITATBID 0xef4 68 #define STMITATBCTR0 0xef8 69 70 #define STM_32_CHANNEL 32 71 #define BYTES_PER_CHANNEL 256 72 #define STM_TRACE_BUF_SIZE 4096 73 #define STM_SW_MASTER_END 127 74 75 /* Register bit definition */ 76 #define STMTCSR_BUSY_BIT 23 77 /* Reserve the first 10 channels for kernel usage */ 78 #define STM_CHANNEL_OFFSET 0 79 80 enum stm_pkt_type { 81 STM_PKT_TYPE_DATA = 0x98, 82 STM_PKT_TYPE_FLAG = 0xE8, 83 STM_PKT_TYPE_TRIG = 0xF8, 84 }; 85 86 #define stm_channel_addr(drvdata, ch) (drvdata->chs.base + \ 87 (ch * BYTES_PER_CHANNEL)) 88 #define stm_channel_off(type, opts) (type & ~opts) 89 90 static int boot_nr_channel; 91 92 /* 93 * Not really modular but using module_param is the easiest way to 94 * remain consistent with existing use cases for now. 95 */ 96 module_param_named( 97 boot_nr_channel, boot_nr_channel, int, S_IRUGO 98 ); 99 100 /* 101 * struct channel_space - central management entity for extended ports 102 * @base: memory mapped base address where channels start. 103 * @phys: physical base address of channel region. 104 * @guaraneed: is the channel delivery guaranteed. 105 */ 106 struct channel_space { 107 void __iomem *base; 108 phys_addr_t phys; 109 unsigned long *guaranteed; 110 }; 111 112 DEFINE_CORESIGHT_DEVLIST(stm_devs, "stm"); 113 114 /** 115 * struct stm_drvdata - specifics associated to an STM component 116 * @base: memory mapped base address for this component. 117 * @atclk: optional clock for the core parts of the STM. 118 * @csdev: component vitals needed by the framework. 119 * @spinlock: only one at a time pls. 120 * @chs: the channels accociated to this STM. 121 * @stm: structure associated to the generic STM interface. 122 * @mode: this tracer's mode, i.e sysFS, or disabled. 123 * @traceid: value of the current ID for this component. 124 * @write_bytes: Maximus bytes this STM can write at a time. 125 * @stmsper: settings for register STMSPER. 126 * @stmspscr: settings for register STMSPSCR. 127 * @numsp: the total number of stimulus port support by this STM. 128 * @stmheer: settings for register STMHEER. 129 * @stmheter: settings for register STMHETER. 130 * @stmhebsr: settings for register STMHEBSR. 131 */ 132 struct stm_drvdata { 133 void __iomem *base; 134 struct clk *atclk; 135 struct coresight_device *csdev; 136 spinlock_t spinlock; 137 struct channel_space chs; 138 struct stm_data stm; 139 local_t mode; 140 u8 traceid; 141 u32 write_bytes; 142 u32 stmsper; 143 u32 stmspscr; 144 u32 numsp; 145 u32 stmheer; 146 u32 stmheter; 147 u32 stmhebsr; 148 }; 149 150 static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata) 151 { 152 CS_UNLOCK(drvdata->base); 153 154 writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR); 155 writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER); 156 writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER); 157 writel_relaxed(0x01 | /* Enable HW event tracing */ 158 0x04, /* Error detection on event tracing */ 159 drvdata->base + STMHEMCR); 160 161 CS_LOCK(drvdata->base); 162 } 163 164 static void stm_port_enable_hw(struct stm_drvdata *drvdata) 165 { 166 CS_UNLOCK(drvdata->base); 167 /* ATB trigger enable on direct writes to TRIG locations */ 168 writel_relaxed(0x10, 169 drvdata->base + STMSPTRIGCSR); 170 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR); 171 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER); 172 173 CS_LOCK(drvdata->base); 174 } 175 176 static void stm_enable_hw(struct stm_drvdata *drvdata) 177 { 178 if (drvdata->stmheer) 179 stm_hwevent_enable_hw(drvdata); 180 181 stm_port_enable_hw(drvdata); 182 183 CS_UNLOCK(drvdata->base); 184 185 /* 4096 byte between synchronisation packets */ 186 writel_relaxed(0xFFF, drvdata->base + STMSYNCR); 187 writel_relaxed((drvdata->traceid << 16 | /* trace id */ 188 0x02 | /* timestamp enable */ 189 0x01), /* global STM enable */ 190 drvdata->base + STMTCSR); 191 192 CS_LOCK(drvdata->base); 193 } 194 195 static int stm_enable(struct coresight_device *csdev, 196 struct perf_event *event, u32 mode) 197 { 198 u32 val; 199 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 200 201 if (mode != CS_MODE_SYSFS) 202 return -EINVAL; 203 204 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); 205 206 /* Someone is already using the tracer */ 207 if (val) 208 return -EBUSY; 209 210 pm_runtime_get_sync(csdev->dev.parent); 211 212 spin_lock(&drvdata->spinlock); 213 stm_enable_hw(drvdata); 214 spin_unlock(&drvdata->spinlock); 215 216 dev_dbg(&csdev->dev, "STM tracing enabled\n"); 217 return 0; 218 } 219 220 static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata) 221 { 222 CS_UNLOCK(drvdata->base); 223 224 writel_relaxed(0x0, drvdata->base + STMHEMCR); 225 writel_relaxed(0x0, drvdata->base + STMHEER); 226 writel_relaxed(0x0, drvdata->base + STMHETER); 227 228 CS_LOCK(drvdata->base); 229 } 230 231 static void stm_port_disable_hw(struct stm_drvdata *drvdata) 232 { 233 CS_UNLOCK(drvdata->base); 234 235 writel_relaxed(0x0, drvdata->base + STMSPER); 236 writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR); 237 238 CS_LOCK(drvdata->base); 239 } 240 241 static void stm_disable_hw(struct stm_drvdata *drvdata) 242 { 243 u32 val; 244 245 CS_UNLOCK(drvdata->base); 246 247 val = readl_relaxed(drvdata->base + STMTCSR); 248 val &= ~0x1; /* clear global STM enable [0] */ 249 writel_relaxed(val, drvdata->base + STMTCSR); 250 251 CS_LOCK(drvdata->base); 252 253 stm_port_disable_hw(drvdata); 254 if (drvdata->stmheer) 255 stm_hwevent_disable_hw(drvdata); 256 } 257 258 static void stm_disable(struct coresight_device *csdev, 259 struct perf_event *event) 260 { 261 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 262 struct csdev_access *csa = &csdev->access; 263 264 /* 265 * For as long as the tracer isn't disabled another entity can't 266 * change its status. As such we can read the status here without 267 * fearing it will change under us. 268 */ 269 if (local_read(&drvdata->mode) == CS_MODE_SYSFS) { 270 spin_lock(&drvdata->spinlock); 271 stm_disable_hw(drvdata); 272 spin_unlock(&drvdata->spinlock); 273 274 /* Wait until the engine has completely stopped */ 275 coresight_timeout(csa, STMTCSR, STMTCSR_BUSY_BIT, 0); 276 277 pm_runtime_put(csdev->dev.parent); 278 279 local_set(&drvdata->mode, CS_MODE_DISABLED); 280 dev_dbg(&csdev->dev, "STM tracing disabled\n"); 281 } 282 } 283 284 static int stm_trace_id(struct coresight_device *csdev) 285 { 286 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 287 288 return drvdata->traceid; 289 } 290 291 static const struct coresight_ops_source stm_source_ops = { 292 .trace_id = stm_trace_id, 293 .enable = stm_enable, 294 .disable = stm_disable, 295 }; 296 297 static const struct coresight_ops stm_cs_ops = { 298 .source_ops = &stm_source_ops, 299 }; 300 301 static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes) 302 { 303 return ((unsigned long)addr & (write_bytes - 1)); 304 } 305 306 static void stm_send(void __iomem *addr, const void *data, 307 u32 size, u8 write_bytes) 308 { 309 u8 paload[8]; 310 311 if (stm_addr_unaligned(data, write_bytes)) { 312 memcpy(paload, data, size); 313 data = paload; 314 } 315 316 /* now we are 64bit/32bit aligned */ 317 switch (size) { 318 #ifdef CONFIG_64BIT 319 case 8: 320 writeq_relaxed(*(u64 *)data, addr); 321 break; 322 #endif 323 case 4: 324 writel_relaxed(*(u32 *)data, addr); 325 break; 326 case 2: 327 writew_relaxed(*(u16 *)data, addr); 328 break; 329 case 1: 330 writeb_relaxed(*(u8 *)data, addr); 331 break; 332 default: 333 break; 334 } 335 } 336 337 static int stm_generic_link(struct stm_data *stm_data, 338 unsigned int master, unsigned int channel) 339 { 340 struct stm_drvdata *drvdata = container_of(stm_data, 341 struct stm_drvdata, stm); 342 if (!drvdata || !drvdata->csdev) 343 return -EINVAL; 344 345 return coresight_enable(drvdata->csdev); 346 } 347 348 static void stm_generic_unlink(struct stm_data *stm_data, 349 unsigned int master, unsigned int channel) 350 { 351 struct stm_drvdata *drvdata = container_of(stm_data, 352 struct stm_drvdata, stm); 353 if (!drvdata || !drvdata->csdev) 354 return; 355 356 coresight_disable(drvdata->csdev); 357 } 358 359 static phys_addr_t 360 stm_mmio_addr(struct stm_data *stm_data, unsigned int master, 361 unsigned int channel, unsigned int nr_chans) 362 { 363 struct stm_drvdata *drvdata = container_of(stm_data, 364 struct stm_drvdata, stm); 365 phys_addr_t addr; 366 367 addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL; 368 369 if (offset_in_page(addr) || 370 offset_in_page(nr_chans * BYTES_PER_CHANNEL)) 371 return 0; 372 373 return addr; 374 } 375 376 static long stm_generic_set_options(struct stm_data *stm_data, 377 unsigned int master, 378 unsigned int channel, 379 unsigned int nr_chans, 380 unsigned long options) 381 { 382 struct stm_drvdata *drvdata = container_of(stm_data, 383 struct stm_drvdata, stm); 384 if (!(drvdata && local_read(&drvdata->mode))) 385 return -EINVAL; 386 387 if (channel >= drvdata->numsp) 388 return -EINVAL; 389 390 switch (options) { 391 case STM_OPTION_GUARANTEED: 392 set_bit(channel, drvdata->chs.guaranteed); 393 break; 394 395 case STM_OPTION_INVARIANT: 396 clear_bit(channel, drvdata->chs.guaranteed); 397 break; 398 399 default: 400 return -EINVAL; 401 } 402 403 return 0; 404 } 405 406 static ssize_t notrace stm_generic_packet(struct stm_data *stm_data, 407 unsigned int master, 408 unsigned int channel, 409 unsigned int packet, 410 unsigned int flags, 411 unsigned int size, 412 const unsigned char *payload) 413 { 414 void __iomem *ch_addr; 415 struct stm_drvdata *drvdata = container_of(stm_data, 416 struct stm_drvdata, stm); 417 unsigned int stm_flags; 418 419 if (!(drvdata && local_read(&drvdata->mode))) 420 return -EACCES; 421 422 if (channel >= drvdata->numsp) 423 return -EINVAL; 424 425 ch_addr = stm_channel_addr(drvdata, channel); 426 427 stm_flags = (flags & STP_PACKET_TIMESTAMPED) ? 428 STM_FLAG_TIMESTAMPED : 0; 429 stm_flags |= test_bit(channel, drvdata->chs.guaranteed) ? 430 STM_FLAG_GUARANTEED : 0; 431 432 if (size > drvdata->write_bytes) 433 size = drvdata->write_bytes; 434 else 435 size = rounddown_pow_of_two(size); 436 437 switch (packet) { 438 case STP_PACKET_FLAG: 439 ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, stm_flags); 440 441 /* 442 * The generic STM core sets a size of '0' on flag packets. 443 * As such send a flag packet of size '1' and tell the 444 * core we did so. 445 */ 446 stm_send(ch_addr, payload, 1, drvdata->write_bytes); 447 size = 1; 448 break; 449 450 case STP_PACKET_DATA: 451 stm_flags |= (flags & STP_PACKET_MARKED) ? STM_FLAG_MARKED : 0; 452 ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, stm_flags); 453 stm_send(ch_addr, payload, size, 454 drvdata->write_bytes); 455 break; 456 457 default: 458 return -ENOTSUPP; 459 } 460 461 return size; 462 } 463 464 static ssize_t hwevent_enable_show(struct device *dev, 465 struct device_attribute *attr, char *buf) 466 { 467 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 468 unsigned long val = drvdata->stmheer; 469 470 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); 471 } 472 473 static ssize_t hwevent_enable_store(struct device *dev, 474 struct device_attribute *attr, 475 const char *buf, size_t size) 476 { 477 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 478 unsigned long val; 479 int ret = 0; 480 481 ret = kstrtoul(buf, 16, &val); 482 if (ret) 483 return -EINVAL; 484 485 drvdata->stmheer = val; 486 /* HW event enable and trigger go hand in hand */ 487 drvdata->stmheter = val; 488 489 return size; 490 } 491 static DEVICE_ATTR_RW(hwevent_enable); 492 493 static ssize_t hwevent_select_show(struct device *dev, 494 struct device_attribute *attr, char *buf) 495 { 496 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 497 unsigned long val = drvdata->stmhebsr; 498 499 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); 500 } 501 502 static ssize_t hwevent_select_store(struct device *dev, 503 struct device_attribute *attr, 504 const char *buf, size_t size) 505 { 506 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 507 unsigned long val; 508 int ret = 0; 509 510 ret = kstrtoul(buf, 16, &val); 511 if (ret) 512 return -EINVAL; 513 514 drvdata->stmhebsr = val; 515 516 return size; 517 } 518 static DEVICE_ATTR_RW(hwevent_select); 519 520 static ssize_t port_select_show(struct device *dev, 521 struct device_attribute *attr, char *buf) 522 { 523 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 524 unsigned long val; 525 526 if (!local_read(&drvdata->mode)) { 527 val = drvdata->stmspscr; 528 } else { 529 spin_lock(&drvdata->spinlock); 530 val = readl_relaxed(drvdata->base + STMSPSCR); 531 spin_unlock(&drvdata->spinlock); 532 } 533 534 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); 535 } 536 537 static ssize_t port_select_store(struct device *dev, 538 struct device_attribute *attr, 539 const char *buf, size_t size) 540 { 541 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 542 unsigned long val, stmsper; 543 int ret = 0; 544 545 ret = kstrtoul(buf, 16, &val); 546 if (ret) 547 return ret; 548 549 spin_lock(&drvdata->spinlock); 550 drvdata->stmspscr = val; 551 552 if (local_read(&drvdata->mode)) { 553 CS_UNLOCK(drvdata->base); 554 /* Process as per ARM's TRM recommendation */ 555 stmsper = readl_relaxed(drvdata->base + STMSPER); 556 writel_relaxed(0x0, drvdata->base + STMSPER); 557 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR); 558 writel_relaxed(stmsper, drvdata->base + STMSPER); 559 CS_LOCK(drvdata->base); 560 } 561 spin_unlock(&drvdata->spinlock); 562 563 return size; 564 } 565 static DEVICE_ATTR_RW(port_select); 566 567 static ssize_t port_enable_show(struct device *dev, 568 struct device_attribute *attr, char *buf) 569 { 570 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 571 unsigned long val; 572 573 if (!local_read(&drvdata->mode)) { 574 val = drvdata->stmsper; 575 } else { 576 spin_lock(&drvdata->spinlock); 577 val = readl_relaxed(drvdata->base + STMSPER); 578 spin_unlock(&drvdata->spinlock); 579 } 580 581 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); 582 } 583 584 static ssize_t port_enable_store(struct device *dev, 585 struct device_attribute *attr, 586 const char *buf, size_t size) 587 { 588 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 589 unsigned long val; 590 int ret = 0; 591 592 ret = kstrtoul(buf, 16, &val); 593 if (ret) 594 return ret; 595 596 spin_lock(&drvdata->spinlock); 597 drvdata->stmsper = val; 598 599 if (local_read(&drvdata->mode)) { 600 CS_UNLOCK(drvdata->base); 601 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER); 602 CS_LOCK(drvdata->base); 603 } 604 spin_unlock(&drvdata->spinlock); 605 606 return size; 607 } 608 static DEVICE_ATTR_RW(port_enable); 609 610 static ssize_t traceid_show(struct device *dev, 611 struct device_attribute *attr, char *buf) 612 { 613 unsigned long val; 614 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 615 616 val = drvdata->traceid; 617 return sprintf(buf, "%#lx\n", val); 618 } 619 static DEVICE_ATTR_RO(traceid); 620 621 static struct attribute *coresight_stm_attrs[] = { 622 &dev_attr_hwevent_enable.attr, 623 &dev_attr_hwevent_select.attr, 624 &dev_attr_port_enable.attr, 625 &dev_attr_port_select.attr, 626 &dev_attr_traceid.attr, 627 NULL, 628 }; 629 630 static struct attribute *coresight_stm_mgmt_attrs[] = { 631 coresight_simple_reg32(tcsr, STMTCSR), 632 coresight_simple_reg32(tsfreqr, STMTSFREQR), 633 coresight_simple_reg32(syncr, STMSYNCR), 634 coresight_simple_reg32(sper, STMSPER), 635 coresight_simple_reg32(spter, STMSPTER), 636 coresight_simple_reg32(privmaskr, STMPRIVMASKR), 637 coresight_simple_reg32(spscr, STMSPSCR), 638 coresight_simple_reg32(spmscr, STMSPMSCR), 639 coresight_simple_reg32(spfeat1r, STMSPFEAT1R), 640 coresight_simple_reg32(spfeat2r, STMSPFEAT2R), 641 coresight_simple_reg32(spfeat3r, STMSPFEAT3R), 642 coresight_simple_reg32(devid, CORESIGHT_DEVID), 643 NULL, 644 }; 645 646 static const struct attribute_group coresight_stm_group = { 647 .attrs = coresight_stm_attrs, 648 }; 649 650 static const struct attribute_group coresight_stm_mgmt_group = { 651 .attrs = coresight_stm_mgmt_attrs, 652 .name = "mgmt", 653 }; 654 655 static const struct attribute_group *coresight_stm_groups[] = { 656 &coresight_stm_group, 657 &coresight_stm_mgmt_group, 658 NULL, 659 }; 660 661 #ifdef CONFIG_OF 662 static int of_stm_get_stimulus_area(struct device *dev, struct resource *res) 663 { 664 const char *name = NULL; 665 int index = 0, found = 0; 666 struct device_node *np = dev->of_node; 667 668 while (!of_property_read_string_index(np, "reg-names", index, &name)) { 669 if (strcmp("stm-stimulus-base", name)) { 670 index++; 671 continue; 672 } 673 674 /* We have a match and @index is where it's at */ 675 found = 1; 676 break; 677 } 678 679 if (!found) 680 return -EINVAL; 681 682 return of_address_to_resource(np, index, res); 683 } 684 #else 685 static inline int of_stm_get_stimulus_area(struct device *dev, 686 struct resource *res) 687 { 688 return -ENOENT; 689 } 690 #endif 691 692 #ifdef CONFIG_ACPI 693 static int acpi_stm_get_stimulus_area(struct device *dev, struct resource *res) 694 { 695 int rc; 696 bool found_base = false; 697 struct resource_entry *rent; 698 LIST_HEAD(res_list); 699 700 struct acpi_device *adev = ACPI_COMPANION(dev); 701 702 rc = acpi_dev_get_resources(adev, &res_list, NULL, NULL); 703 if (rc < 0) 704 return rc; 705 706 /* 707 * The stimulus base for STM device must be listed as the second memory 708 * resource, followed by the programming base address as described in 709 * "Section 2.3 Resources" in ACPI for CoreSightTM 1.0 Platform Design 710 * document (DEN0067). 711 */ 712 rc = -ENOENT; 713 list_for_each_entry(rent, &res_list, node) { 714 if (resource_type(rent->res) != IORESOURCE_MEM) 715 continue; 716 if (found_base) { 717 *res = *rent->res; 718 rc = 0; 719 break; 720 } 721 722 found_base = true; 723 } 724 725 acpi_dev_free_resource_list(&res_list); 726 return rc; 727 } 728 #else 729 static inline int acpi_stm_get_stimulus_area(struct device *dev, 730 struct resource *res) 731 { 732 return -ENOENT; 733 } 734 #endif 735 736 static int stm_get_stimulus_area(struct device *dev, struct resource *res) 737 { 738 struct fwnode_handle *fwnode = dev_fwnode(dev); 739 740 if (is_of_node(fwnode)) 741 return of_stm_get_stimulus_area(dev, res); 742 else if (is_acpi_node(fwnode)) 743 return acpi_stm_get_stimulus_area(dev, res); 744 return -ENOENT; 745 } 746 747 static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata) 748 { 749 u32 stmspfeat2r; 750 751 if (!IS_ENABLED(CONFIG_64BIT)) 752 return 4; 753 754 stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R); 755 756 /* 757 * bit[15:12] represents the fundamental data size 758 * 0 - 32-bit data 759 * 1 - 64-bit data 760 */ 761 return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4; 762 } 763 764 static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata) 765 { 766 u32 numsp; 767 768 numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID); 769 /* 770 * NUMPS in STMDEVID is 17 bit long and if equal to 0x0, 771 * 32 stimulus ports are supported. 772 */ 773 numsp &= 0x1ffff; 774 if (!numsp) 775 numsp = STM_32_CHANNEL; 776 return numsp; 777 } 778 779 static void stm_init_default_data(struct stm_drvdata *drvdata) 780 { 781 /* Don't use port selection */ 782 drvdata->stmspscr = 0x0; 783 /* 784 * Enable all channel regardless of their number. When port 785 * selection isn't used (see above) STMSPER applies to all 786 * 32 channel group available, hence setting all 32 bits to 1 787 */ 788 drvdata->stmsper = ~0x0; 789 790 /* Set invariant transaction timing on all channels */ 791 bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp); 792 } 793 794 static void stm_init_generic_data(struct stm_drvdata *drvdata, 795 const char *name) 796 { 797 drvdata->stm.name = name; 798 799 /* 800 * MasterIDs are assigned at HW design phase. As such the core is 801 * using a single master for interaction with this device. 802 */ 803 drvdata->stm.sw_start = 1; 804 drvdata->stm.sw_end = 1; 805 drvdata->stm.hw_override = true; 806 drvdata->stm.sw_nchannels = drvdata->numsp; 807 drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL; 808 drvdata->stm.packet = stm_generic_packet; 809 drvdata->stm.mmio_addr = stm_mmio_addr; 810 drvdata->stm.link = stm_generic_link; 811 drvdata->stm.unlink = stm_generic_unlink; 812 drvdata->stm.set_options = stm_generic_set_options; 813 } 814 815 static int stm_probe(struct amba_device *adev, const struct amba_id *id) 816 { 817 int ret, trace_id; 818 void __iomem *base; 819 struct device *dev = &adev->dev; 820 struct coresight_platform_data *pdata = NULL; 821 struct stm_drvdata *drvdata; 822 struct resource *res = &adev->res; 823 struct resource ch_res; 824 struct coresight_desc desc = { 0 }; 825 826 desc.name = coresight_alloc_device_name(&stm_devs, dev); 827 if (!desc.name) 828 return -ENOMEM; 829 830 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 831 if (!drvdata) 832 return -ENOMEM; 833 834 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ 835 if (!IS_ERR(drvdata->atclk)) { 836 ret = clk_prepare_enable(drvdata->atclk); 837 if (ret) 838 return ret; 839 } 840 dev_set_drvdata(dev, drvdata); 841 842 base = devm_ioremap_resource(dev, res); 843 if (IS_ERR(base)) 844 return PTR_ERR(base); 845 drvdata->base = base; 846 desc.access = CSDEV_ACCESS_IOMEM(base); 847 848 ret = stm_get_stimulus_area(dev, &ch_res); 849 if (ret) 850 return ret; 851 drvdata->chs.phys = ch_res.start; 852 853 base = devm_ioremap_resource(dev, &ch_res); 854 if (IS_ERR(base)) 855 return PTR_ERR(base); 856 drvdata->chs.base = base; 857 858 drvdata->write_bytes = stm_fundamental_data_size(drvdata); 859 860 if (boot_nr_channel) 861 drvdata->numsp = boot_nr_channel; 862 else 863 drvdata->numsp = stm_num_stimulus_port(drvdata); 864 865 drvdata->chs.guaranteed = devm_bitmap_zalloc(dev, drvdata->numsp, 866 GFP_KERNEL); 867 if (!drvdata->chs.guaranteed) 868 return -ENOMEM; 869 870 spin_lock_init(&drvdata->spinlock); 871 872 stm_init_default_data(drvdata); 873 stm_init_generic_data(drvdata, desc.name); 874 875 if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) { 876 dev_info(dev, 877 "%s : stm_register_device failed, probing deferred\n", 878 desc.name); 879 return -EPROBE_DEFER; 880 } 881 882 pdata = coresight_get_platform_data(dev); 883 if (IS_ERR(pdata)) { 884 ret = PTR_ERR(pdata); 885 goto stm_unregister; 886 } 887 adev->dev.platform_data = pdata; 888 889 desc.type = CORESIGHT_DEV_TYPE_SOURCE; 890 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE; 891 desc.ops = &stm_cs_ops; 892 desc.pdata = pdata; 893 desc.dev = dev; 894 desc.groups = coresight_stm_groups; 895 drvdata->csdev = coresight_register(&desc); 896 if (IS_ERR(drvdata->csdev)) { 897 ret = PTR_ERR(drvdata->csdev); 898 goto stm_unregister; 899 } 900 901 trace_id = coresight_trace_id_get_system_id(); 902 if (trace_id < 0) { 903 ret = trace_id; 904 goto cs_unregister; 905 } 906 drvdata->traceid = (u8)trace_id; 907 908 pm_runtime_put(&adev->dev); 909 910 dev_info(&drvdata->csdev->dev, "%s initialized\n", 911 (char *)coresight_get_uci_data(id)); 912 return 0; 913 914 cs_unregister: 915 coresight_unregister(drvdata->csdev); 916 917 stm_unregister: 918 stm_unregister_device(&drvdata->stm); 919 return ret; 920 } 921 922 static void stm_remove(struct amba_device *adev) 923 { 924 struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev); 925 926 coresight_trace_id_put_system_id(drvdata->traceid); 927 coresight_unregister(drvdata->csdev); 928 929 stm_unregister_device(&drvdata->stm); 930 } 931 932 #ifdef CONFIG_PM 933 static int stm_runtime_suspend(struct device *dev) 934 { 935 struct stm_drvdata *drvdata = dev_get_drvdata(dev); 936 937 if (drvdata && !IS_ERR(drvdata->atclk)) 938 clk_disable_unprepare(drvdata->atclk); 939 940 return 0; 941 } 942 943 static int stm_runtime_resume(struct device *dev) 944 { 945 struct stm_drvdata *drvdata = dev_get_drvdata(dev); 946 947 if (drvdata && !IS_ERR(drvdata->atclk)) 948 clk_prepare_enable(drvdata->atclk); 949 950 return 0; 951 } 952 #endif 953 954 static const struct dev_pm_ops stm_dev_pm_ops = { 955 SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL) 956 }; 957 958 static const struct amba_id stm_ids[] = { 959 CS_AMBA_ID_DATA(0x000bb962, "STM32"), 960 CS_AMBA_ID_DATA(0x000bb963, "STM500"), 961 { 0, 0}, 962 }; 963 964 MODULE_DEVICE_TABLE(amba, stm_ids); 965 966 static struct amba_driver stm_driver = { 967 .drv = { 968 .name = "coresight-stm", 969 .owner = THIS_MODULE, 970 .pm = &stm_dev_pm_ops, 971 .suppress_bind_attrs = true, 972 }, 973 .probe = stm_probe, 974 .remove = stm_remove, 975 .id_table = stm_ids, 976 }; 977 978 module_amba_driver(stm_driver); 979 980 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>"); 981 MODULE_DESCRIPTION("Arm CoreSight System Trace Macrocell driver"); 982 MODULE_LICENSE("GPL v2"); 983