1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2014-2018 Nuvoton Technology corporation. 3 4 #include <linux/clk.h> 5 #include <linux/device.h> 6 #include <linux/hwmon.h> 7 #include <linux/hwmon-sysfs.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of_address.h> 12 #include <linux/of_irq.h> 13 #include <linux/platform_device.h> 14 #include <linux/spinlock.h> 15 #include <linux/sysfs.h> 16 #include <linux/thermal.h> 17 18 /* NPCM7XX PWM registers */ 19 #define NPCM7XX_PWM_REG_BASE(base, n) ((base) + ((n) * 0x1000L)) 20 21 #define NPCM7XX_PWM_REG_PR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x00) 22 #define NPCM7XX_PWM_REG_CSR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x04) 23 #define NPCM7XX_PWM_REG_CR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x08) 24 #define NPCM7XX_PWM_REG_CNRx(base, n, ch) \ 25 (NPCM7XX_PWM_REG_BASE(base, n) + 0x0C + (12 * (ch))) 26 #define NPCM7XX_PWM_REG_CMRx(base, n, ch) \ 27 (NPCM7XX_PWM_REG_BASE(base, n) + 0x10 + (12 * (ch))) 28 #define NPCM7XX_PWM_REG_PDRx(base, n, ch) \ 29 (NPCM7XX_PWM_REG_BASE(base, n) + 0x14 + (12 * (ch))) 30 #define NPCM7XX_PWM_REG_PIER(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x3C) 31 #define NPCM7XX_PWM_REG_PIIR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x40) 32 33 #define NPCM7XX_PWM_CTRL_CH0_MODE_BIT BIT(3) 34 #define NPCM7XX_PWM_CTRL_CH1_MODE_BIT BIT(11) 35 #define NPCM7XX_PWM_CTRL_CH2_MODE_BIT BIT(15) 36 #define NPCM7XX_PWM_CTRL_CH3_MODE_BIT BIT(19) 37 38 #define NPCM7XX_PWM_CTRL_CH0_INV_BIT BIT(2) 39 #define NPCM7XX_PWM_CTRL_CH1_INV_BIT BIT(10) 40 #define NPCM7XX_PWM_CTRL_CH2_INV_BIT BIT(14) 41 #define NPCM7XX_PWM_CTRL_CH3_INV_BIT BIT(18) 42 43 #define NPCM7XX_PWM_CTRL_CH0_EN_BIT BIT(0) 44 #define NPCM7XX_PWM_CTRL_CH1_EN_BIT BIT(8) 45 #define NPCM7XX_PWM_CTRL_CH2_EN_BIT BIT(12) 46 #define NPCM7XX_PWM_CTRL_CH3_EN_BIT BIT(16) 47 48 /* Define the maximum PWM channel number */ 49 #define NPCM7XX_PWM_MAX_CHN_NUM 12 50 #define NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE 4 51 #define NPCM7XX_PWM_MAX_MODULES 3 52 53 /* Define the Counter Register, value = 100 for match 100% */ 54 #define NPCM7XX_PWM_COUNTER_DEFAULT_NUM 255 55 #define NPCM7XX_PWM_CMR_DEFAULT_NUM 255 56 #define NPCM7XX_PWM_CMR_MAX 255 57 58 /* default all PWM channels PRESCALE2 = 1 */ 59 #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 0x4 60 #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 0x40 61 #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 0x400 62 #define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3 0x4000 63 64 #define PWM_OUTPUT_FREQ_25KHZ 25000 65 #define PWN_CNT_DEFAULT 256 66 #define MIN_PRESCALE1 2 67 #define NPCM7XX_PWM_PRESCALE_SHIFT_CH01 8 68 69 #define NPCM7XX_PWM_PRESCALE2_DEFAULT (NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 | \ 70 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 | \ 71 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 | \ 72 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3) 73 74 #define NPCM7XX_PWM_CTRL_MODE_DEFAULT (NPCM7XX_PWM_CTRL_CH0_MODE_BIT | \ 75 NPCM7XX_PWM_CTRL_CH1_MODE_BIT | \ 76 NPCM7XX_PWM_CTRL_CH2_MODE_BIT | \ 77 NPCM7XX_PWM_CTRL_CH3_MODE_BIT) 78 79 /* NPCM7XX FAN Tacho registers */ 80 #define NPCM7XX_FAN_REG_BASE(base, n) ((base) + ((n) * 0x1000L)) 81 82 #define NPCM7XX_FAN_REG_TCNT1(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x00) 83 #define NPCM7XX_FAN_REG_TCRA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x02) 84 #define NPCM7XX_FAN_REG_TCRB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x04) 85 #define NPCM7XX_FAN_REG_TCNT2(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x06) 86 #define NPCM7XX_FAN_REG_TPRSC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x08) 87 #define NPCM7XX_FAN_REG_TCKC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0A) 88 #define NPCM7XX_FAN_REG_TMCTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0C) 89 #define NPCM7XX_FAN_REG_TICTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0E) 90 #define NPCM7XX_FAN_REG_TICLR(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x10) 91 #define NPCM7XX_FAN_REG_TIEN(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x12) 92 #define NPCM7XX_FAN_REG_TCPA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x14) 93 #define NPCM7XX_FAN_REG_TCPB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x16) 94 #define NPCM7XX_FAN_REG_TCPCFG(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x18) 95 #define NPCM7XX_FAN_REG_TINASEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1A) 96 #define NPCM7XX_FAN_REG_TINBSEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1C) 97 98 #define NPCM7XX_FAN_TCKC_CLKX_NONE 0 99 #define NPCM7XX_FAN_TCKC_CLK1_APB BIT(0) 100 #define NPCM7XX_FAN_TCKC_CLK2_APB BIT(3) 101 102 #define NPCM7XX_FAN_TMCTRL_TBEN BIT(6) 103 #define NPCM7XX_FAN_TMCTRL_TAEN BIT(5) 104 #define NPCM7XX_FAN_TMCTRL_TBEDG BIT(4) 105 #define NPCM7XX_FAN_TMCTRL_TAEDG BIT(3) 106 #define NPCM7XX_FAN_TMCTRL_MODE_5 BIT(2) 107 108 #define NPCM7XX_FAN_TICLR_CLEAR_ALL GENMASK(5, 0) 109 #define NPCM7XX_FAN_TICLR_TFCLR BIT(5) 110 #define NPCM7XX_FAN_TICLR_TECLR BIT(4) 111 #define NPCM7XX_FAN_TICLR_TDCLR BIT(3) 112 #define NPCM7XX_FAN_TICLR_TCCLR BIT(2) 113 #define NPCM7XX_FAN_TICLR_TBCLR BIT(1) 114 #define NPCM7XX_FAN_TICLR_TACLR BIT(0) 115 116 #define NPCM7XX_FAN_TIEN_ENABLE_ALL GENMASK(5, 0) 117 #define NPCM7XX_FAN_TIEN_TFIEN BIT(5) 118 #define NPCM7XX_FAN_TIEN_TEIEN BIT(4) 119 #define NPCM7XX_FAN_TIEN_TDIEN BIT(3) 120 #define NPCM7XX_FAN_TIEN_TCIEN BIT(2) 121 #define NPCM7XX_FAN_TIEN_TBIEN BIT(1) 122 #define NPCM7XX_FAN_TIEN_TAIEN BIT(0) 123 124 #define NPCM7XX_FAN_TICTRL_TFPND BIT(5) 125 #define NPCM7XX_FAN_TICTRL_TEPND BIT(4) 126 #define NPCM7XX_FAN_TICTRL_TDPND BIT(3) 127 #define NPCM7XX_FAN_TICTRL_TCPND BIT(2) 128 #define NPCM7XX_FAN_TICTRL_TBPND BIT(1) 129 #define NPCM7XX_FAN_TICTRL_TAPND BIT(0) 130 131 #define NPCM7XX_FAN_TCPCFG_HIBEN BIT(7) 132 #define NPCM7XX_FAN_TCPCFG_EQBEN BIT(6) 133 #define NPCM7XX_FAN_TCPCFG_LOBEN BIT(5) 134 #define NPCM7XX_FAN_TCPCFG_CPBSEL BIT(4) 135 #define NPCM7XX_FAN_TCPCFG_HIAEN BIT(3) 136 #define NPCM7XX_FAN_TCPCFG_EQAEN BIT(2) 137 #define NPCM7XX_FAN_TCPCFG_LOAEN BIT(1) 138 #define NPCM7XX_FAN_TCPCFG_CPASEL BIT(0) 139 140 /* FAN General Definition */ 141 /* Define the maximum FAN channel number */ 142 #define NPCM7XX_FAN_MAX_MODULE 8 143 #define NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE 2 144 #define NPCM7XX_FAN_MAX_CHN_NUM 16 145 146 /* 147 * Get Fan Tach Timeout (base on clock 214843.75Hz, 1 cnt = 4.654us) 148 * Timeout 94ms ~= 0x5000 149 * (The minimum FAN speed could to support ~640RPM/pulse 1, 150 * 320RPM/pulse 2, ...-- 10.6Hz) 151 */ 152 #define NPCM7XX_FAN_TIMEOUT 0x5000 153 #define NPCM7XX_FAN_TCNT 0xFFFF 154 #define NPCM7XX_FAN_TCPA (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT) 155 #define NPCM7XX_FAN_TCPB (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT) 156 157 #define NPCM7XX_FAN_POLL_TIMER_200MS 200 158 #define NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION 2 159 #define NPCM7XX_FAN_TINASEL_FANIN_DEFAULT 0 160 #define NPCM7XX_FAN_CLK_PRESCALE 255 161 162 #define NPCM7XX_FAN_CMPA 0 163 #define NPCM7XX_FAN_CMPB 1 164 165 /* Obtain the fan number */ 166 #define NPCM7XX_FAN_INPUT(fan, cmp) (((fan) << 1) + (cmp)) 167 168 /* fan sample status */ 169 #define FAN_DISABLE 0xFF 170 #define FAN_INIT 0x00 171 #define FAN_PREPARE_TO_GET_FIRST_CAPTURE 0x01 172 #define FAN_ENOUGH_SAMPLE 0x02 173 174 struct npcm_hwmon_info { 175 u32 pwm_max_channel; 176 }; 177 178 struct npcm7xx_fan_dev { 179 u8 fan_st_flg; 180 u8 fan_pls_per_rev; 181 u16 fan_cnt; 182 u32 fan_cnt_tmp; 183 }; 184 185 struct npcm7xx_cooling_device { 186 char name[THERMAL_NAME_LENGTH]; 187 struct npcm7xx_pwm_fan_data *data; 188 struct thermal_cooling_device *tcdev; 189 int pwm_port; 190 u8 *cooling_levels; 191 u8 max_state; 192 u8 cur_state; 193 }; 194 195 struct npcm7xx_pwm_fan_data { 196 void __iomem *pwm_base; 197 void __iomem *fan_base; 198 unsigned long pwm_clk_freq; 199 unsigned long fan_clk_freq; 200 struct clk *pwm_clk; 201 struct clk *fan_clk; 202 struct mutex pwm_lock[NPCM7XX_PWM_MAX_MODULES]; 203 spinlock_t fan_lock[NPCM7XX_FAN_MAX_MODULE]; 204 int fan_irq[NPCM7XX_FAN_MAX_MODULE]; 205 bool pwm_present[NPCM7XX_PWM_MAX_CHN_NUM]; 206 bool fan_present[NPCM7XX_FAN_MAX_CHN_NUM]; 207 u32 input_clk_freq; 208 struct timer_list fan_timer; 209 struct npcm7xx_fan_dev fan_dev[NPCM7XX_FAN_MAX_CHN_NUM]; 210 struct npcm7xx_cooling_device *cdev[NPCM7XX_PWM_MAX_CHN_NUM]; 211 const struct npcm_hwmon_info *info; 212 u8 fan_select; 213 }; 214 npcm7xx_pwm_config_set(struct npcm7xx_pwm_fan_data * data,int channel,u16 val)215 static int npcm7xx_pwm_config_set(struct npcm7xx_pwm_fan_data *data, 216 int channel, u16 val) 217 { 218 u32 pwm_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE); 219 u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE); 220 u32 tmp_buf, ctrl_en_bit, env_bit; 221 222 /* 223 * Config PWM Comparator register for setting duty cycle 224 */ 225 mutex_lock(&data->pwm_lock[module]); 226 227 /* write new CMR value */ 228 iowrite32(val, NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pwm_ch)); 229 tmp_buf = ioread32(NPCM7XX_PWM_REG_CR(data->pwm_base, module)); 230 231 switch (pwm_ch) { 232 case 0: 233 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH0_EN_BIT; 234 env_bit = NPCM7XX_PWM_CTRL_CH0_INV_BIT; 235 break; 236 case 1: 237 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH1_EN_BIT; 238 env_bit = NPCM7XX_PWM_CTRL_CH1_INV_BIT; 239 break; 240 case 2: 241 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH2_EN_BIT; 242 env_bit = NPCM7XX_PWM_CTRL_CH2_INV_BIT; 243 break; 244 case 3: 245 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH3_EN_BIT; 246 env_bit = NPCM7XX_PWM_CTRL_CH3_INV_BIT; 247 break; 248 default: 249 mutex_unlock(&data->pwm_lock[module]); 250 return -ENODEV; 251 } 252 253 if (val == 0) { 254 /* Disable PWM */ 255 tmp_buf &= ~ctrl_en_bit; 256 tmp_buf |= env_bit; 257 } else { 258 /* Enable PWM */ 259 tmp_buf |= ctrl_en_bit; 260 tmp_buf &= ~env_bit; 261 } 262 263 iowrite32(tmp_buf, NPCM7XX_PWM_REG_CR(data->pwm_base, module)); 264 mutex_unlock(&data->pwm_lock[module]); 265 266 return 0; 267 } 268 npcm7xx_fan_start_capture(struct npcm7xx_pwm_fan_data * data,u8 fan,u8 cmp)269 static inline void npcm7xx_fan_start_capture(struct npcm7xx_pwm_fan_data *data, 270 u8 fan, u8 cmp) 271 { 272 u8 fan_id; 273 u8 reg_mode; 274 u8 reg_int; 275 unsigned long flags; 276 277 fan_id = NPCM7XX_FAN_INPUT(fan, cmp); 278 279 /* to check whether any fan tach is enable */ 280 if (data->fan_dev[fan_id].fan_st_flg != FAN_DISABLE) { 281 /* reset status */ 282 spin_lock_irqsave(&data->fan_lock[fan], flags); 283 284 data->fan_dev[fan_id].fan_st_flg = FAN_INIT; 285 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 286 287 /* 288 * the interrupt enable bits do not need to be cleared before 289 * it sets, the interrupt enable bits are cleared only on reset. 290 * the clock unit control register is behaving in the same 291 * manner that the interrupt enable register behave. 292 */ 293 if (cmp == NPCM7XX_FAN_CMPA) { 294 /* enable interrupt */ 295 iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TAIEN | 296 NPCM7XX_FAN_TIEN_TEIEN), 297 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 298 299 reg_mode = NPCM7XX_FAN_TCKC_CLK1_APB 300 | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, 301 fan)); 302 303 /* start to Capture */ 304 iowrite8(reg_mode, NPCM7XX_FAN_REG_TCKC(data->fan_base, 305 fan)); 306 } else { 307 /* enable interrupt */ 308 iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TBIEN | 309 NPCM7XX_FAN_TIEN_TFIEN), 310 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 311 312 reg_mode = 313 NPCM7XX_FAN_TCKC_CLK2_APB 314 | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, 315 fan)); 316 317 /* start to Capture */ 318 iowrite8(reg_mode, 319 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); 320 } 321 322 spin_unlock_irqrestore(&data->fan_lock[fan], flags); 323 } 324 } 325 326 /* 327 * Enable a background timer to poll fan tach value, (200ms * 4) 328 * to polling all fan 329 */ npcm7xx_fan_polling(struct timer_list * t)330 static void npcm7xx_fan_polling(struct timer_list *t) 331 { 332 struct npcm7xx_pwm_fan_data *data; 333 int i; 334 335 data = from_timer(data, t, fan_timer); 336 337 /* 338 * Polling two module per one round, 339 * FAN01 & FAN89 / FAN23 & FAN1011 / FAN45 & FAN1213 / FAN67 & FAN1415 340 */ 341 for (i = data->fan_select; i < NPCM7XX_FAN_MAX_MODULE; 342 i = i + 4) { 343 /* clear the flag and reset the counter (TCNT) */ 344 iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL, 345 NPCM7XX_FAN_REG_TICLR(data->fan_base, i)); 346 347 if (data->fan_present[i * 2]) { 348 iowrite16(NPCM7XX_FAN_TCNT, 349 NPCM7XX_FAN_REG_TCNT1(data->fan_base, i)); 350 npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPA); 351 } 352 if (data->fan_present[(i * 2) + 1]) { 353 iowrite16(NPCM7XX_FAN_TCNT, 354 NPCM7XX_FAN_REG_TCNT2(data->fan_base, i)); 355 npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPB); 356 } 357 } 358 359 data->fan_select++; 360 data->fan_select &= 0x3; 361 362 /* reset the timer interval */ 363 data->fan_timer.expires = jiffies + 364 msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS); 365 add_timer(&data->fan_timer); 366 } 367 npcm7xx_fan_compute(struct npcm7xx_pwm_fan_data * data,u8 fan,u8 cmp,u8 fan_id,u8 flag_int,u8 flag_mode,u8 flag_clear)368 static inline void npcm7xx_fan_compute(struct npcm7xx_pwm_fan_data *data, 369 u8 fan, u8 cmp, u8 fan_id, u8 flag_int, 370 u8 flag_mode, u8 flag_clear) 371 { 372 u8 reg_int; 373 u8 reg_mode; 374 u16 fan_cap; 375 376 if (cmp == NPCM7XX_FAN_CMPA) 377 fan_cap = ioread16(NPCM7XX_FAN_REG_TCRA(data->fan_base, fan)); 378 else 379 fan_cap = ioread16(NPCM7XX_FAN_REG_TCRB(data->fan_base, fan)); 380 381 /* clear capature flag, H/W will auto reset the NPCM7XX_FAN_TCNTx */ 382 iowrite8(flag_clear, NPCM7XX_FAN_REG_TICLR(data->fan_base, fan)); 383 384 if (data->fan_dev[fan_id].fan_st_flg == FAN_INIT) { 385 /* First capture, drop it */ 386 data->fan_dev[fan_id].fan_st_flg = 387 FAN_PREPARE_TO_GET_FIRST_CAPTURE; 388 389 /* reset counter */ 390 data->fan_dev[fan_id].fan_cnt_tmp = 0; 391 } else if (data->fan_dev[fan_id].fan_st_flg < FAN_ENOUGH_SAMPLE) { 392 /* 393 * collect the enough sample, 394 * (ex: 2 pulse fan need to get 2 sample) 395 */ 396 data->fan_dev[fan_id].fan_cnt_tmp += 397 (NPCM7XX_FAN_TCNT - fan_cap); 398 399 data->fan_dev[fan_id].fan_st_flg++; 400 } else { 401 /* get enough sample or fan disable */ 402 if (data->fan_dev[fan_id].fan_st_flg == FAN_ENOUGH_SAMPLE) { 403 data->fan_dev[fan_id].fan_cnt_tmp += 404 (NPCM7XX_FAN_TCNT - fan_cap); 405 406 /* compute finial average cnt per pulse */ 407 data->fan_dev[fan_id].fan_cnt = 408 data->fan_dev[fan_id].fan_cnt_tmp / 409 FAN_ENOUGH_SAMPLE; 410 411 data->fan_dev[fan_id].fan_st_flg = FAN_INIT; 412 } 413 414 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 415 416 /* disable interrupt */ 417 iowrite8((reg_int & ~flag_int), 418 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 419 reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); 420 421 /* stop capturing */ 422 iowrite8((reg_mode & ~flag_mode), 423 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); 424 } 425 } 426 npcm7xx_check_cmp(struct npcm7xx_pwm_fan_data * data,u8 fan,u8 cmp,u8 flag)427 static inline void npcm7xx_check_cmp(struct npcm7xx_pwm_fan_data *data, 428 u8 fan, u8 cmp, u8 flag) 429 { 430 u8 reg_int; 431 u8 reg_mode; 432 u8 flag_timeout; 433 u8 flag_cap; 434 u8 flag_clear; 435 u8 flag_int; 436 u8 flag_mode; 437 u8 fan_id; 438 439 fan_id = NPCM7XX_FAN_INPUT(fan, cmp); 440 441 if (cmp == NPCM7XX_FAN_CMPA) { 442 flag_cap = NPCM7XX_FAN_TICTRL_TAPND; 443 flag_timeout = NPCM7XX_FAN_TICTRL_TEPND; 444 flag_int = NPCM7XX_FAN_TIEN_TAIEN | NPCM7XX_FAN_TIEN_TEIEN; 445 flag_mode = NPCM7XX_FAN_TCKC_CLK1_APB; 446 flag_clear = NPCM7XX_FAN_TICLR_TACLR | NPCM7XX_FAN_TICLR_TECLR; 447 } else { 448 flag_cap = NPCM7XX_FAN_TICTRL_TBPND; 449 flag_timeout = NPCM7XX_FAN_TICTRL_TFPND; 450 flag_int = NPCM7XX_FAN_TIEN_TBIEN | NPCM7XX_FAN_TIEN_TFIEN; 451 flag_mode = NPCM7XX_FAN_TCKC_CLK2_APB; 452 flag_clear = NPCM7XX_FAN_TICLR_TBCLR | NPCM7XX_FAN_TICLR_TFCLR; 453 } 454 455 if (flag & flag_timeout) { 456 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 457 458 /* disable interrupt */ 459 iowrite8((reg_int & ~flag_int), 460 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan)); 461 462 /* clear interrupt flag */ 463 iowrite8(flag_clear, 464 NPCM7XX_FAN_REG_TICLR(data->fan_base, fan)); 465 466 reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); 467 468 /* stop capturing */ 469 iowrite8((reg_mode & ~flag_mode), 470 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan)); 471 472 /* 473 * If timeout occurs (NPCM7XX_FAN_TIMEOUT), the fan doesn't 474 * connect or speed is lower than 10.6Hz (320RPM/pulse2). 475 * In these situation, the RPM output should be zero. 476 */ 477 data->fan_dev[fan_id].fan_cnt = 0; 478 } else { 479 /* input capture is occurred */ 480 if (flag & flag_cap) 481 npcm7xx_fan_compute(data, fan, cmp, fan_id, flag_int, 482 flag_mode, flag_clear); 483 } 484 } 485 npcm7xx_fan_isr(int irq,void * dev_id)486 static irqreturn_t npcm7xx_fan_isr(int irq, void *dev_id) 487 { 488 struct npcm7xx_pwm_fan_data *data = dev_id; 489 unsigned long flags; 490 int module; 491 u8 flag; 492 493 module = irq - data->fan_irq[0]; 494 spin_lock_irqsave(&data->fan_lock[module], flags); 495 496 flag = ioread8(NPCM7XX_FAN_REG_TICTRL(data->fan_base, module)); 497 if (flag > 0) { 498 npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPA, flag); 499 npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPB, flag); 500 spin_unlock_irqrestore(&data->fan_lock[module], flags); 501 return IRQ_HANDLED; 502 } 503 504 spin_unlock_irqrestore(&data->fan_lock[module], flags); 505 506 return IRQ_NONE; 507 } 508 npcm7xx_read_pwm(struct device * dev,u32 attr,int channel,long * val)509 static int npcm7xx_read_pwm(struct device *dev, u32 attr, int channel, 510 long *val) 511 { 512 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev); 513 u32 pmw_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE); 514 u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE); 515 516 switch (attr) { 517 case hwmon_pwm_input: 518 *val = ioread32 519 (NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pmw_ch)); 520 return 0; 521 default: 522 return -EOPNOTSUPP; 523 } 524 } 525 npcm7xx_write_pwm(struct device * dev,u32 attr,int channel,long val)526 static int npcm7xx_write_pwm(struct device *dev, u32 attr, int channel, 527 long val) 528 { 529 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev); 530 int err; 531 532 switch (attr) { 533 case hwmon_pwm_input: 534 if (val < 0 || val > NPCM7XX_PWM_CMR_MAX) 535 return -EINVAL; 536 err = npcm7xx_pwm_config_set(data, channel, (u16)val); 537 break; 538 default: 539 err = -EOPNOTSUPP; 540 break; 541 } 542 543 return err; 544 } 545 npcm7xx_pwm_is_visible(const void * _data,u32 attr,int channel)546 static umode_t npcm7xx_pwm_is_visible(const void *_data, u32 attr, int channel) 547 { 548 const struct npcm7xx_pwm_fan_data *data = _data; 549 550 if (!data->pwm_present[channel] || channel >= data->info->pwm_max_channel) 551 return 0; 552 553 switch (attr) { 554 case hwmon_pwm_input: 555 return 0644; 556 default: 557 return 0; 558 } 559 } 560 npcm7xx_read_fan(struct device * dev,u32 attr,int channel,long * val)561 static int npcm7xx_read_fan(struct device *dev, u32 attr, int channel, 562 long *val) 563 { 564 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev); 565 566 switch (attr) { 567 case hwmon_fan_input: 568 *val = 0; 569 if (data->fan_dev[channel].fan_cnt <= 0) 570 return data->fan_dev[channel].fan_cnt; 571 572 /* Convert the raw reading to RPM */ 573 if (data->fan_dev[channel].fan_cnt > 0 && 574 data->fan_dev[channel].fan_pls_per_rev > 0) 575 *val = ((data->input_clk_freq * 60) / 576 (data->fan_dev[channel].fan_cnt * 577 data->fan_dev[channel].fan_pls_per_rev)); 578 return 0; 579 default: 580 return -EOPNOTSUPP; 581 } 582 } 583 npcm7xx_fan_is_visible(const void * _data,u32 attr,int channel)584 static umode_t npcm7xx_fan_is_visible(const void *_data, u32 attr, int channel) 585 { 586 const struct npcm7xx_pwm_fan_data *data = _data; 587 588 if (!data->fan_present[channel]) 589 return 0; 590 591 switch (attr) { 592 case hwmon_fan_input: 593 return 0444; 594 default: 595 return 0; 596 } 597 } 598 npcm7xx_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)599 static int npcm7xx_read(struct device *dev, enum hwmon_sensor_types type, 600 u32 attr, int channel, long *val) 601 { 602 switch (type) { 603 case hwmon_pwm: 604 return npcm7xx_read_pwm(dev, attr, channel, val); 605 case hwmon_fan: 606 return npcm7xx_read_fan(dev, attr, channel, val); 607 default: 608 return -EOPNOTSUPP; 609 } 610 } 611 npcm7xx_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long val)612 static int npcm7xx_write(struct device *dev, enum hwmon_sensor_types type, 613 u32 attr, int channel, long val) 614 { 615 switch (type) { 616 case hwmon_pwm: 617 return npcm7xx_write_pwm(dev, attr, channel, val); 618 default: 619 return -EOPNOTSUPP; 620 } 621 } 622 npcm7xx_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)623 static umode_t npcm7xx_is_visible(const void *data, 624 enum hwmon_sensor_types type, 625 u32 attr, int channel) 626 { 627 switch (type) { 628 case hwmon_pwm: 629 return npcm7xx_pwm_is_visible(data, attr, channel); 630 case hwmon_fan: 631 return npcm7xx_fan_is_visible(data, attr, channel); 632 default: 633 return 0; 634 } 635 } 636 637 static const struct hwmon_channel_info * const npcm7xx_info[] = { 638 HWMON_CHANNEL_INFO(pwm, 639 HWMON_PWM_INPUT, 640 HWMON_PWM_INPUT, 641 HWMON_PWM_INPUT, 642 HWMON_PWM_INPUT, 643 HWMON_PWM_INPUT, 644 HWMON_PWM_INPUT, 645 HWMON_PWM_INPUT, 646 HWMON_PWM_INPUT, 647 HWMON_PWM_INPUT, 648 HWMON_PWM_INPUT, 649 HWMON_PWM_INPUT, 650 HWMON_PWM_INPUT), 651 HWMON_CHANNEL_INFO(fan, 652 HWMON_F_INPUT, 653 HWMON_F_INPUT, 654 HWMON_F_INPUT, 655 HWMON_F_INPUT, 656 HWMON_F_INPUT, 657 HWMON_F_INPUT, 658 HWMON_F_INPUT, 659 HWMON_F_INPUT, 660 HWMON_F_INPUT, 661 HWMON_F_INPUT, 662 HWMON_F_INPUT, 663 HWMON_F_INPUT, 664 HWMON_F_INPUT, 665 HWMON_F_INPUT, 666 HWMON_F_INPUT, 667 HWMON_F_INPUT), 668 NULL 669 }; 670 671 static const struct hwmon_ops npcm7xx_hwmon_ops = { 672 .is_visible = npcm7xx_is_visible, 673 .read = npcm7xx_read, 674 .write = npcm7xx_write, 675 }; 676 677 static const struct hwmon_chip_info npcm7xx_chip_info = { 678 .ops = &npcm7xx_hwmon_ops, 679 .info = npcm7xx_info, 680 }; 681 682 static const struct npcm_hwmon_info npxm7xx_hwmon_info = { 683 .pwm_max_channel = 8, 684 }; 685 686 static const struct npcm_hwmon_info npxm8xx_hwmon_info = { 687 .pwm_max_channel = 12, 688 }; 689 npcm7xx_pwm_init(struct npcm7xx_pwm_fan_data * data)690 static u32 npcm7xx_pwm_init(struct npcm7xx_pwm_fan_data *data) 691 { 692 int m, ch; 693 u32 prescale_val, output_freq; 694 695 data->pwm_clk_freq = clk_get_rate(data->pwm_clk); 696 697 /* Adjust NPCM7xx PWMs output frequency to ~25Khz */ 698 output_freq = data->pwm_clk_freq / PWN_CNT_DEFAULT; 699 prescale_val = DIV_ROUND_CLOSEST(output_freq, PWM_OUTPUT_FREQ_25KHZ); 700 701 /* If prescale_val = 0, then the prescale output clock is stopped */ 702 if (prescale_val < MIN_PRESCALE1) 703 prescale_val = MIN_PRESCALE1; 704 /* 705 * prescale_val need to decrement in one because in the PWM Prescale 706 * register the Prescale value increment by one 707 */ 708 prescale_val--; 709 710 /* Setting PWM Prescale Register value register to both modules */ 711 prescale_val |= (prescale_val << NPCM7XX_PWM_PRESCALE_SHIFT_CH01); 712 713 for (m = 0; m < NPCM7XX_PWM_MAX_MODULES ; m++) { 714 iowrite32(prescale_val, NPCM7XX_PWM_REG_PR(data->pwm_base, m)); 715 iowrite32(NPCM7XX_PWM_PRESCALE2_DEFAULT, 716 NPCM7XX_PWM_REG_CSR(data->pwm_base, m)); 717 iowrite32(NPCM7XX_PWM_CTRL_MODE_DEFAULT, 718 NPCM7XX_PWM_REG_CR(data->pwm_base, m)); 719 720 for (ch = 0; ch < NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE; ch++) { 721 iowrite32(NPCM7XX_PWM_COUNTER_DEFAULT_NUM, 722 NPCM7XX_PWM_REG_CNRx(data->pwm_base, m, ch)); 723 } 724 } 725 726 return output_freq / ((prescale_val & 0xf) + 1); 727 } 728 npcm7xx_fan_init(struct npcm7xx_pwm_fan_data * data)729 static void npcm7xx_fan_init(struct npcm7xx_pwm_fan_data *data) 730 { 731 int md; 732 int ch; 733 int i; 734 u32 apb_clk_freq; 735 736 for (md = 0; md < NPCM7XX_FAN_MAX_MODULE; md++) { 737 /* stop FAN0~7 clock */ 738 iowrite8(NPCM7XX_FAN_TCKC_CLKX_NONE, 739 NPCM7XX_FAN_REG_TCKC(data->fan_base, md)); 740 741 /* disable all interrupt */ 742 iowrite8(0x00, NPCM7XX_FAN_REG_TIEN(data->fan_base, md)); 743 744 /* clear all interrupt */ 745 iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL, 746 NPCM7XX_FAN_REG_TICLR(data->fan_base, md)); 747 748 /* set FAN0~7 clock prescaler */ 749 iowrite8(NPCM7XX_FAN_CLK_PRESCALE, 750 NPCM7XX_FAN_REG_TPRSC(data->fan_base, md)); 751 752 /* set FAN0~7 mode (high-to-low transition) */ 753 iowrite8((NPCM7XX_FAN_TMCTRL_MODE_5 | NPCM7XX_FAN_TMCTRL_TBEN | 754 NPCM7XX_FAN_TMCTRL_TAEN), 755 NPCM7XX_FAN_REG_TMCTRL(data->fan_base, md)); 756 757 /* set FAN0~7 Initial Count/Cap */ 758 iowrite16(NPCM7XX_FAN_TCNT, 759 NPCM7XX_FAN_REG_TCNT1(data->fan_base, md)); 760 iowrite16(NPCM7XX_FAN_TCNT, 761 NPCM7XX_FAN_REG_TCNT2(data->fan_base, md)); 762 763 /* set FAN0~7 compare (equal to count) */ 764 iowrite8((NPCM7XX_FAN_TCPCFG_EQAEN | NPCM7XX_FAN_TCPCFG_EQBEN), 765 NPCM7XX_FAN_REG_TCPCFG(data->fan_base, md)); 766 767 /* set FAN0~7 compare value */ 768 iowrite16(NPCM7XX_FAN_TCPA, 769 NPCM7XX_FAN_REG_TCPA(data->fan_base, md)); 770 iowrite16(NPCM7XX_FAN_TCPB, 771 NPCM7XX_FAN_REG_TCPB(data->fan_base, md)); 772 773 /* set FAN0~7 fan input FANIN 0~15 */ 774 iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT, 775 NPCM7XX_FAN_REG_TINASEL(data->fan_base, md)); 776 iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT, 777 NPCM7XX_FAN_REG_TINBSEL(data->fan_base, md)); 778 779 for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE; i++) { 780 ch = md * NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE + i; 781 data->fan_dev[ch].fan_st_flg = FAN_DISABLE; 782 data->fan_dev[ch].fan_pls_per_rev = 783 NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION; 784 data->fan_dev[ch].fan_cnt = 0; 785 } 786 } 787 788 apb_clk_freq = clk_get_rate(data->fan_clk); 789 790 /* Fan tach input clock = APB clock / prescalar, default is 255. */ 791 data->input_clk_freq = apb_clk_freq / (NPCM7XX_FAN_CLK_PRESCALE + 1); 792 } 793 794 static int npcm7xx_pwm_cz_get_max_state(struct thermal_cooling_device * tcdev,unsigned long * state)795 npcm7xx_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev, 796 unsigned long *state) 797 { 798 struct npcm7xx_cooling_device *cdev = tcdev->devdata; 799 800 *state = cdev->max_state; 801 802 return 0; 803 } 804 805 static int npcm7xx_pwm_cz_get_cur_state(struct thermal_cooling_device * tcdev,unsigned long * state)806 npcm7xx_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev, 807 unsigned long *state) 808 { 809 struct npcm7xx_cooling_device *cdev = tcdev->devdata; 810 811 *state = cdev->cur_state; 812 813 return 0; 814 } 815 816 static int npcm7xx_pwm_cz_set_cur_state(struct thermal_cooling_device * tcdev,unsigned long state)817 npcm7xx_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev, 818 unsigned long state) 819 { 820 struct npcm7xx_cooling_device *cdev = tcdev->devdata; 821 int ret; 822 823 if (state > cdev->max_state) 824 return -EINVAL; 825 826 cdev->cur_state = state; 827 ret = npcm7xx_pwm_config_set(cdev->data, cdev->pwm_port, 828 cdev->cooling_levels[cdev->cur_state]); 829 830 return ret; 831 } 832 833 static const struct thermal_cooling_device_ops npcm7xx_pwm_cool_ops = { 834 .get_max_state = npcm7xx_pwm_cz_get_max_state, 835 .get_cur_state = npcm7xx_pwm_cz_get_cur_state, 836 .set_cur_state = npcm7xx_pwm_cz_set_cur_state, 837 }; 838 npcm7xx_create_pwm_cooling(struct device * dev,struct device_node * child,struct npcm7xx_pwm_fan_data * data,u32 pwm_port,u8 num_levels)839 static int npcm7xx_create_pwm_cooling(struct device *dev, 840 struct device_node *child, 841 struct npcm7xx_pwm_fan_data *data, 842 u32 pwm_port, u8 num_levels) 843 { 844 int ret; 845 struct npcm7xx_cooling_device *cdev; 846 847 cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL); 848 if (!cdev) 849 return -ENOMEM; 850 851 cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL); 852 if (!cdev->cooling_levels) 853 return -ENOMEM; 854 855 cdev->max_state = num_levels - 1; 856 ret = of_property_read_u8_array(child, "cooling-levels", 857 cdev->cooling_levels, 858 num_levels); 859 if (ret) { 860 dev_err(dev, "Property 'cooling-levels' cannot be read.\n"); 861 return ret; 862 } 863 snprintf(cdev->name, THERMAL_NAME_LENGTH, "%pOFn%d", child, 864 pwm_port); 865 866 cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child, 867 cdev->name, cdev, &npcm7xx_pwm_cool_ops); 868 if (IS_ERR(cdev->tcdev)) 869 return PTR_ERR(cdev->tcdev); 870 871 cdev->data = data; 872 cdev->pwm_port = pwm_port; 873 874 data->cdev[pwm_port] = cdev; 875 876 return 0; 877 } 878 npcm7xx_en_pwm_fan(struct device * dev,struct device_node * child,struct npcm7xx_pwm_fan_data * data)879 static int npcm7xx_en_pwm_fan(struct device *dev, 880 struct device_node *child, 881 struct npcm7xx_pwm_fan_data *data) 882 { 883 u8 *fan_ch; 884 u32 pwm_port; 885 int ret, fan_cnt; 886 u8 index, ch; 887 888 ret = of_property_read_u32(child, "reg", &pwm_port); 889 if (ret) 890 return ret; 891 892 data->pwm_present[pwm_port] = true; 893 ret = npcm7xx_pwm_config_set(data, pwm_port, 894 NPCM7XX_PWM_CMR_DEFAULT_NUM); 895 896 ret = of_property_count_u8_elems(child, "cooling-levels"); 897 if (ret > 0) { 898 ret = npcm7xx_create_pwm_cooling(dev, child, data, pwm_port, 899 ret); 900 if (ret) 901 return ret; 902 } 903 904 fan_cnt = of_property_count_u8_elems(child, "fan-tach-ch"); 905 if (fan_cnt < 1) 906 return -EINVAL; 907 908 fan_ch = devm_kcalloc(dev, fan_cnt, sizeof(*fan_ch), GFP_KERNEL); 909 if (!fan_ch) 910 return -ENOMEM; 911 912 ret = of_property_read_u8_array(child, "fan-tach-ch", fan_ch, fan_cnt); 913 if (ret) 914 return ret; 915 916 for (ch = 0; ch < fan_cnt; ch++) { 917 index = fan_ch[ch]; 918 data->fan_present[index] = true; 919 data->fan_dev[index].fan_st_flg = FAN_INIT; 920 } 921 922 return 0; 923 } 924 npcm7xx_pwm_fan_probe(struct platform_device * pdev)925 static int npcm7xx_pwm_fan_probe(struct platform_device *pdev) 926 { 927 struct device *dev = &pdev->dev; 928 struct device_node *np, *child; 929 struct npcm7xx_pwm_fan_data *data; 930 struct resource *res; 931 struct device *hwmon; 932 char name[20]; 933 int ret, cnt; 934 u32 output_freq; 935 u32 i; 936 937 np = dev->of_node; 938 939 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 940 if (!data) 941 return -ENOMEM; 942 943 data->info = device_get_match_data(dev); 944 if (!data->info) 945 return -EINVAL; 946 947 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"); 948 if (!res) { 949 dev_err(dev, "pwm resource not found\n"); 950 return -ENODEV; 951 } 952 953 data->pwm_base = devm_ioremap_resource(dev, res); 954 dev_dbg(dev, "pwm base resource is %pR\n", res); 955 if (IS_ERR(data->pwm_base)) 956 return PTR_ERR(data->pwm_base); 957 958 data->pwm_clk = devm_clk_get(dev, "pwm"); 959 if (IS_ERR(data->pwm_clk)) { 960 dev_err(dev, "couldn't get pwm clock\n"); 961 return PTR_ERR(data->pwm_clk); 962 } 963 964 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fan"); 965 if (!res) { 966 dev_err(dev, "fan resource not found\n"); 967 return -ENODEV; 968 } 969 970 data->fan_base = devm_ioremap_resource(dev, res); 971 dev_dbg(dev, "fan base resource is %pR\n", res); 972 if (IS_ERR(data->fan_base)) 973 return PTR_ERR(data->fan_base); 974 975 data->fan_clk = devm_clk_get(dev, "fan"); 976 if (IS_ERR(data->fan_clk)) { 977 dev_err(dev, "couldn't get fan clock\n"); 978 return PTR_ERR(data->fan_clk); 979 } 980 981 output_freq = npcm7xx_pwm_init(data); 982 npcm7xx_fan_init(data); 983 984 for (cnt = 0; cnt < NPCM7XX_PWM_MAX_MODULES ; cnt++) 985 mutex_init(&data->pwm_lock[cnt]); 986 987 for (i = 0; i < NPCM7XX_FAN_MAX_MODULE; i++) { 988 spin_lock_init(&data->fan_lock[i]); 989 990 data->fan_irq[i] = platform_get_irq(pdev, i); 991 if (data->fan_irq[i] < 0) 992 return data->fan_irq[i]; 993 994 sprintf(name, "NPCM7XX-FAN-MD%d", i); 995 ret = devm_request_irq(dev, data->fan_irq[i], npcm7xx_fan_isr, 996 0, name, (void *)data); 997 if (ret) { 998 dev_err(dev, "register IRQ fan%d failed\n", i); 999 return ret; 1000 } 1001 } 1002 1003 for_each_child_of_node(np, child) { 1004 ret = npcm7xx_en_pwm_fan(dev, child, data); 1005 if (ret) { 1006 dev_err(dev, "enable pwm and fan failed\n"); 1007 of_node_put(child); 1008 return ret; 1009 } 1010 } 1011 1012 hwmon = devm_hwmon_device_register_with_info(dev, "npcm7xx_pwm_fan", 1013 data, &npcm7xx_chip_info, 1014 NULL); 1015 if (IS_ERR(hwmon)) { 1016 dev_err(dev, "unable to register hwmon device\n"); 1017 return PTR_ERR(hwmon); 1018 } 1019 1020 for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM; i++) { 1021 if (data->fan_present[i]) { 1022 /* fan timer initialization */ 1023 data->fan_timer.expires = jiffies + 1024 msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS); 1025 timer_setup(&data->fan_timer, 1026 npcm7xx_fan_polling, 0); 1027 add_timer(&data->fan_timer); 1028 break; 1029 } 1030 } 1031 1032 pr_info("NPCM7XX PWM-FAN Driver probed, output Freq %dHz[PWM], input Freq %dHz[FAN]\n", 1033 output_freq, data->input_clk_freq); 1034 1035 return 0; 1036 } 1037 1038 static const struct of_device_id of_pwm_fan_match_table[] = { 1039 { .compatible = "nuvoton,npcm750-pwm-fan", .data = &npxm7xx_hwmon_info}, 1040 { .compatible = "nuvoton,npcm845-pwm-fan", .data = &npxm8xx_hwmon_info}, 1041 {}, 1042 }; 1043 MODULE_DEVICE_TABLE(of, of_pwm_fan_match_table); 1044 1045 static struct platform_driver npcm7xx_pwm_fan_driver = { 1046 .probe = npcm7xx_pwm_fan_probe, 1047 .driver = { 1048 .name = "npcm7xx_pwm_fan", 1049 .of_match_table = of_pwm_fan_match_table, 1050 }, 1051 }; 1052 1053 module_platform_driver(npcm7xx_pwm_fan_driver); 1054 1055 MODULE_DESCRIPTION("Nuvoton NPCM7XX PWM and Fan Tacho driver"); 1056 MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>"); 1057 MODULE_LICENSE("GPL v2"); 1058