1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h 4 * processor hardware monitoring 5 * 6 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de> 7 * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net> 8 * 9 * Implementation notes: 10 * - CCD register address information as well as the calculation to 11 * convert raw register values is from https://github.com/ocerman/zenpower. 12 * The information is not confirmed from chip datasheets, but experiments 13 * suggest that it provides reasonable temperature values. 14 */ 15 16 #include <linux/bitops.h> 17 #include <linux/err.h> 18 #include <linux/hwmon.h> 19 #include <linux/init.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/pci_ids.h> 23 #include <asm/amd_nb.h> 24 #include <asm/processor.h> 25 26 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor"); 27 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); 28 MODULE_LICENSE("GPL"); 29 30 static bool force; 31 module_param(force, bool, 0444); 32 MODULE_PARM_DESC(force, "force loading on processors with erratum 319"); 33 34 /* Provide lock for writing to NB_SMU_IND_ADDR */ 35 static DEFINE_MUTEX(nb_smu_ind_mutex); 36 37 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 38 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3 39 #endif 40 41 /* CPUID function 0x80000001, ebx */ 42 #define CPUID_PKGTYPE_MASK GENMASK(31, 28) 43 #define CPUID_PKGTYPE_F 0x00000000 44 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000 45 46 /* DRAM controller (PCI function 2) */ 47 #define REG_DCT0_CONFIG_HIGH 0x094 48 #define DDR3_MODE BIT(8) 49 50 /* miscellaneous (PCI function 3) */ 51 #define REG_HARDWARE_THERMAL_CONTROL 0x64 52 #define HTC_ENABLE BIT(0) 53 54 #define REG_REPORTED_TEMPERATURE 0xa4 55 56 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8 57 #define NB_CAP_HTC BIT(10) 58 59 /* 60 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL 61 * and REG_REPORTED_TEMPERATURE have been moved to 62 * D0F0xBC_xD820_0C64 [Hardware Temperature Control] 63 * D0F0xBC_xD820_0CA4 [Reported Temperature Control] 64 */ 65 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64 66 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4 67 68 /* Common for Zen CPU families (Family 17h and 18h and 19h) */ 69 #define ZEN_REPORTED_TEMP_CTRL_BASE 0x00059800 70 71 #define ZEN_CCD_TEMP(offset, x) (ZEN_REPORTED_TEMP_CTRL_BASE + \ 72 (offset) + ((x) * 4)) 73 #define ZEN_CCD_TEMP_VALID BIT(11) 74 #define ZEN_CCD_TEMP_MASK GENMASK(10, 0) 75 76 #define ZEN_CUR_TEMP_SHIFT 21 77 #define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19) 78 79 struct k10temp_data { 80 struct pci_dev *pdev; 81 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval); 82 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval); 83 int temp_offset; 84 u32 temp_adjust_mask; 85 u32 show_temp; 86 bool is_zen; 87 u32 ccd_offset; 88 }; 89 90 #define TCTL_BIT 0 91 #define TDIE_BIT 1 92 #define TCCD_BIT(x) ((x) + 2) 93 94 #define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel)) 95 #define HAVE_TDIE(d) HAVE_TEMP(d, TDIE_BIT) 96 97 struct tctl_offset { 98 u8 model; 99 char const *id; 100 int offset; 101 }; 102 103 static const struct tctl_offset tctl_offset_table[] = { 104 { 0x17, "AMD Ryzen 5 1600X", 20000 }, 105 { 0x17, "AMD Ryzen 7 1700X", 20000 }, 106 { 0x17, "AMD Ryzen 7 1800X", 20000 }, 107 { 0x17, "AMD Ryzen 7 2700X", 10000 }, 108 { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */ 109 { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */ 110 }; 111 112 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval) 113 { 114 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval); 115 } 116 117 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval) 118 { 119 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval); 120 } 121 122 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn, 123 unsigned int base, int offset, u32 *val) 124 { 125 mutex_lock(&nb_smu_ind_mutex); 126 pci_bus_write_config_dword(pdev->bus, devfn, 127 base, offset); 128 pci_bus_read_config_dword(pdev->bus, devfn, 129 base + 4, val); 130 mutex_unlock(&nb_smu_ind_mutex); 131 } 132 133 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval) 134 { 135 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 136 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval); 137 } 138 139 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval) 140 { 141 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, 142 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval); 143 } 144 145 static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval) 146 { 147 amd_smn_read(amd_pci_dev_to_node_id(pdev), 148 ZEN_REPORTED_TEMP_CTRL_BASE, regval); 149 } 150 151 static long get_raw_temp(struct k10temp_data *data) 152 { 153 u32 regval; 154 long temp; 155 156 data->read_tempreg(data->pdev, ®val); 157 temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125; 158 if (regval & data->temp_adjust_mask) 159 temp -= 49000; 160 return temp; 161 } 162 163 static const char *k10temp_temp_label[] = { 164 "Tctl", 165 "Tdie", 166 "Tccd1", 167 "Tccd2", 168 "Tccd3", 169 "Tccd4", 170 "Tccd5", 171 "Tccd6", 172 "Tccd7", 173 "Tccd8", 174 }; 175 176 static int k10temp_read_labels(struct device *dev, 177 enum hwmon_sensor_types type, 178 u32 attr, int channel, const char **str) 179 { 180 switch (type) { 181 case hwmon_temp: 182 *str = k10temp_temp_label[channel]; 183 break; 184 default: 185 return -EOPNOTSUPP; 186 } 187 return 0; 188 } 189 190 static int k10temp_read_temp(struct device *dev, u32 attr, int channel, 191 long *val) 192 { 193 struct k10temp_data *data = dev_get_drvdata(dev); 194 u32 regval; 195 196 switch (attr) { 197 case hwmon_temp_input: 198 switch (channel) { 199 case 0: /* Tctl */ 200 *val = get_raw_temp(data); 201 if (*val < 0) 202 *val = 0; 203 break; 204 case 1: /* Tdie */ 205 *val = get_raw_temp(data) - data->temp_offset; 206 if (*val < 0) 207 *val = 0; 208 break; 209 case 2 ... 9: /* Tccd{1-8} */ 210 amd_smn_read(amd_pci_dev_to_node_id(data->pdev), 211 ZEN_CCD_TEMP(data->ccd_offset, channel - 2), 212 ®val); 213 *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000; 214 break; 215 default: 216 return -EOPNOTSUPP; 217 } 218 break; 219 case hwmon_temp_max: 220 *val = 70 * 1000; 221 break; 222 case hwmon_temp_crit: 223 data->read_htcreg(data->pdev, ®val); 224 *val = ((regval >> 16) & 0x7f) * 500 + 52000; 225 break; 226 case hwmon_temp_crit_hyst: 227 data->read_htcreg(data->pdev, ®val); 228 *val = (((regval >> 16) & 0x7f) 229 - ((regval >> 24) & 0xf)) * 500 + 52000; 230 break; 231 default: 232 return -EOPNOTSUPP; 233 } 234 return 0; 235 } 236 237 static int k10temp_read(struct device *dev, enum hwmon_sensor_types type, 238 u32 attr, int channel, long *val) 239 { 240 switch (type) { 241 case hwmon_temp: 242 return k10temp_read_temp(dev, attr, channel, val); 243 default: 244 return -EOPNOTSUPP; 245 } 246 } 247 248 static umode_t k10temp_is_visible(const void *_data, 249 enum hwmon_sensor_types type, 250 u32 attr, int channel) 251 { 252 const struct k10temp_data *data = _data; 253 struct pci_dev *pdev = data->pdev; 254 u32 reg; 255 256 switch (type) { 257 case hwmon_temp: 258 switch (attr) { 259 case hwmon_temp_input: 260 if (!HAVE_TEMP(data, channel)) 261 return 0; 262 break; 263 case hwmon_temp_max: 264 if (channel || data->is_zen) 265 return 0; 266 break; 267 case hwmon_temp_crit: 268 case hwmon_temp_crit_hyst: 269 if (channel || !data->read_htcreg) 270 return 0; 271 272 pci_read_config_dword(pdev, 273 REG_NORTHBRIDGE_CAPABILITIES, 274 ®); 275 if (!(reg & NB_CAP_HTC)) 276 return 0; 277 278 data->read_htcreg(data->pdev, ®); 279 if (!(reg & HTC_ENABLE)) 280 return 0; 281 break; 282 case hwmon_temp_label: 283 /* Show temperature labels only on Zen CPUs */ 284 if (!data->is_zen || !HAVE_TEMP(data, channel)) 285 return 0; 286 break; 287 default: 288 return 0; 289 } 290 break; 291 default: 292 return 0; 293 } 294 return 0444; 295 } 296 297 static bool has_erratum_319(struct pci_dev *pdev) 298 { 299 u32 pkg_type, reg_dram_cfg; 300 301 if (boot_cpu_data.x86 != 0x10) 302 return false; 303 304 /* 305 * Erratum 319: The thermal sensor of Socket F/AM2+ processors 306 * may be unreliable. 307 */ 308 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK; 309 if (pkg_type == CPUID_PKGTYPE_F) 310 return true; 311 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3) 312 return false; 313 314 /* DDR3 memory implies socket AM3, which is good */ 315 pci_bus_read_config_dword(pdev->bus, 316 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2), 317 REG_DCT0_CONFIG_HIGH, ®_dram_cfg); 318 if (reg_dram_cfg & DDR3_MODE) 319 return false; 320 321 /* 322 * Unfortunately it is possible to run a socket AM3 CPU with DDR2 323 * memory. We blacklist all the cores which do exist in socket AM2+ 324 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+ 325 * and AM3 formats, but that's the best we can do. 326 */ 327 return boot_cpu_data.x86_model < 4 || 328 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2); 329 } 330 331 static const struct hwmon_channel_info *k10temp_info[] = { 332 HWMON_CHANNEL_INFO(temp, 333 HWMON_T_INPUT | HWMON_T_MAX | 334 HWMON_T_CRIT | HWMON_T_CRIT_HYST | 335 HWMON_T_LABEL, 336 HWMON_T_INPUT | HWMON_T_LABEL, 337 HWMON_T_INPUT | HWMON_T_LABEL, 338 HWMON_T_INPUT | HWMON_T_LABEL, 339 HWMON_T_INPUT | HWMON_T_LABEL, 340 HWMON_T_INPUT | HWMON_T_LABEL, 341 HWMON_T_INPUT | HWMON_T_LABEL, 342 HWMON_T_INPUT | HWMON_T_LABEL, 343 HWMON_T_INPUT | HWMON_T_LABEL, 344 HWMON_T_INPUT | HWMON_T_LABEL), 345 NULL 346 }; 347 348 static const struct hwmon_ops k10temp_hwmon_ops = { 349 .is_visible = k10temp_is_visible, 350 .read = k10temp_read, 351 .read_string = k10temp_read_labels, 352 }; 353 354 static const struct hwmon_chip_info k10temp_chip_info = { 355 .ops = &k10temp_hwmon_ops, 356 .info = k10temp_info, 357 }; 358 359 static void k10temp_get_ccd_support(struct pci_dev *pdev, 360 struct k10temp_data *data, int limit) 361 { 362 u32 regval; 363 int i; 364 365 for (i = 0; i < limit; i++) { 366 amd_smn_read(amd_pci_dev_to_node_id(pdev), 367 ZEN_CCD_TEMP(data->ccd_offset, i), ®val); 368 if (regval & ZEN_CCD_TEMP_VALID) 369 data->show_temp |= BIT(TCCD_BIT(i)); 370 } 371 } 372 373 static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id) 374 { 375 int unreliable = has_erratum_319(pdev); 376 struct device *dev = &pdev->dev; 377 struct k10temp_data *data; 378 struct device *hwmon_dev; 379 int i; 380 381 if (unreliable) { 382 if (!force) { 383 dev_err(dev, 384 "unreliable CPU thermal sensor; monitoring disabled\n"); 385 return -ENODEV; 386 } 387 dev_warn(dev, 388 "unreliable CPU thermal sensor; check erratum 319\n"); 389 } 390 391 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 392 if (!data) 393 return -ENOMEM; 394 395 data->pdev = pdev; 396 data->show_temp |= BIT(TCTL_BIT); /* Always show Tctl */ 397 398 if (boot_cpu_data.x86 == 0x15 && 399 ((boot_cpu_data.x86_model & 0xf0) == 0x60 || 400 (boot_cpu_data.x86_model & 0xf0) == 0x70)) { 401 data->read_htcreg = read_htcreg_nb_f15; 402 data->read_tempreg = read_tempreg_nb_f15; 403 } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) { 404 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK; 405 data->read_tempreg = read_tempreg_nb_zen; 406 data->is_zen = true; 407 408 switch (boot_cpu_data.x86_model) { 409 case 0x1: /* Zen */ 410 case 0x8: /* Zen+ */ 411 case 0x11: /* Zen APU */ 412 case 0x18: /* Zen+ APU */ 413 data->ccd_offset = 0x154; 414 k10temp_get_ccd_support(pdev, data, 4); 415 break; 416 case 0x31: /* Zen2 Threadripper */ 417 case 0x60: /* Renoir */ 418 case 0x68: /* Lucienne */ 419 case 0x71: /* Zen2 */ 420 data->ccd_offset = 0x154; 421 k10temp_get_ccd_support(pdev, data, 8); 422 break; 423 } 424 } else if (boot_cpu_data.x86 == 0x19) { 425 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK; 426 data->read_tempreg = read_tempreg_nb_zen; 427 data->is_zen = true; 428 429 switch (boot_cpu_data.x86_model) { 430 case 0x0 ... 0x1: /* Zen3 SP3/TR */ 431 case 0x21: /* Zen3 Ryzen Desktop */ 432 case 0x50 ... 0x5f: /* Green Sardine */ 433 data->ccd_offset = 0x154; 434 k10temp_get_ccd_support(pdev, data, 8); 435 break; 436 case 0x10 ... 0x1f: 437 case 0x40 ... 0x4f: /* Yellow Carp */ 438 case 0xa0 ... 0xaf: 439 data->ccd_offset = 0x300; 440 k10temp_get_ccd_support(pdev, data, 8); 441 break; 442 } 443 } else { 444 data->read_htcreg = read_htcreg_pci; 445 data->read_tempreg = read_tempreg_pci; 446 } 447 448 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) { 449 const struct tctl_offset *entry = &tctl_offset_table[i]; 450 451 if (boot_cpu_data.x86 == entry->model && 452 strstr(boot_cpu_data.x86_model_id, entry->id)) { 453 data->show_temp |= BIT(TDIE_BIT); /* show Tdie */ 454 data->temp_offset = entry->offset; 455 break; 456 } 457 } 458 459 hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data, 460 &k10temp_chip_info, 461 NULL); 462 return PTR_ERR_OR_ZERO(hwmon_dev); 463 } 464 465 static const struct pci_device_id k10temp_id_table[] = { 466 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, 467 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) }, 468 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) }, 469 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, 470 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, 471 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, 472 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) }, 473 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) }, 474 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, 475 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) }, 476 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) }, 477 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) }, 478 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) }, 479 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) }, 480 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) }, 481 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) }, 482 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) }, 483 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) }, 484 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) }, 485 { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) }, 486 {} 487 }; 488 MODULE_DEVICE_TABLE(pci, k10temp_id_table); 489 490 static struct pci_driver k10temp_driver = { 491 .name = "k10temp", 492 .id_table = k10temp_id_table, 493 .probe = k10temp_probe, 494 }; 495 496 module_pci_driver(k10temp_driver); 497