18412b410SNuno Sá // SPDX-License-Identifier: GPL-2.0 28412b410SNuno Sá /* 38412b410SNuno Sá * Fan Control HDL CORE driver 48412b410SNuno Sá * 58412b410SNuno Sá * Copyright 2019 Analog Devices Inc. 68412b410SNuno Sá */ 78412b410SNuno Sá #include <linux/bits.h> 88412b410SNuno Sá #include <linux/clk.h> 98412b410SNuno Sá #include <linux/fpga/adi-axi-common.h> 108412b410SNuno Sá #include <linux/hwmon.h> 118412b410SNuno Sá #include <linux/interrupt.h> 128412b410SNuno Sá #include <linux/io.h> 138412b410SNuno Sá #include <linux/kernel.h> 148412b410SNuno Sá #include <linux/module.h> 158412b410SNuno Sá #include <linux/of.h> 168412b410SNuno Sá #include <linux/platform_device.h> 178412b410SNuno Sá 188412b410SNuno Sá /* register map */ 198412b410SNuno Sá #define ADI_REG_RSTN 0x0080 208412b410SNuno Sá #define ADI_REG_PWM_WIDTH 0x0084 218412b410SNuno Sá #define ADI_REG_TACH_PERIOD 0x0088 228412b410SNuno Sá #define ADI_REG_TACH_TOLERANCE 0x008c 238412b410SNuno Sá #define ADI_REG_PWM_PERIOD 0x00c0 248412b410SNuno Sá #define ADI_REG_TACH_MEASUR 0x00c4 258412b410SNuno Sá #define ADI_REG_TEMPERATURE 0x00c8 268412b410SNuno Sá 278412b410SNuno Sá #define ADI_REG_IRQ_MASK 0x0040 288412b410SNuno Sá #define ADI_REG_IRQ_PENDING 0x0044 298412b410SNuno Sá #define ADI_REG_IRQ_SRC 0x0048 308412b410SNuno Sá 318412b410SNuno Sá /* IRQ sources */ 328412b410SNuno Sá #define ADI_IRQ_SRC_PWM_CHANGED BIT(0) 338412b410SNuno Sá #define ADI_IRQ_SRC_TACH_ERR BIT(1) 348412b410SNuno Sá #define ADI_IRQ_SRC_TEMP_INCREASE BIT(2) 358412b410SNuno Sá #define ADI_IRQ_SRC_NEW_MEASUR BIT(3) 368412b410SNuno Sá #define ADI_IRQ_SRC_MASK GENMASK(3, 0) 378412b410SNuno Sá #define ADI_IRQ_MASK_OUT_ALL 0xFFFFFFFFU 388412b410SNuno Sá 398412b410SNuno Sá #define SYSFS_PWM_MAX 255 408412b410SNuno Sá 418412b410SNuno Sá struct axi_fan_control_data { 428412b410SNuno Sá void __iomem *base; 438412b410SNuno Sá struct device *hdev; 448412b410SNuno Sá unsigned long clk_rate; 458412b410SNuno Sá int irq; 468412b410SNuno Sá /* pulses per revolution */ 478412b410SNuno Sá u32 ppr; 488412b410SNuno Sá bool hw_pwm_req; 498412b410SNuno Sá bool update_tacho_params; 508412b410SNuno Sá u8 fan_fault; 518412b410SNuno Sá }; 528412b410SNuno Sá 538412b410SNuno Sá static inline void axi_iowrite(const u32 val, const u32 reg, 548412b410SNuno Sá const struct axi_fan_control_data *ctl) 558412b410SNuno Sá { 568412b410SNuno Sá iowrite32(val, ctl->base + reg); 578412b410SNuno Sá } 588412b410SNuno Sá 598412b410SNuno Sá static inline u32 axi_ioread(const u32 reg, 608412b410SNuno Sá const struct axi_fan_control_data *ctl) 618412b410SNuno Sá { 628412b410SNuno Sá return ioread32(ctl->base + reg); 638412b410SNuno Sá } 648412b410SNuno Sá 658412b410SNuno Sá static long axi_fan_control_get_pwm_duty(const struct axi_fan_control_data *ctl) 668412b410SNuno Sá { 678412b410SNuno Sá u32 pwm_width = axi_ioread(ADI_REG_PWM_WIDTH, ctl); 688412b410SNuno Sá u32 pwm_period = axi_ioread(ADI_REG_PWM_PERIOD, ctl); 698412b410SNuno Sá /* 708412b410SNuno Sá * PWM_PERIOD is a RO register set by the core. It should never be 0. 718412b410SNuno Sá * For now we are trusting the HW... 728412b410SNuno Sá */ 738412b410SNuno Sá return DIV_ROUND_CLOSEST(pwm_width * SYSFS_PWM_MAX, pwm_period); 748412b410SNuno Sá } 758412b410SNuno Sá 768412b410SNuno Sá static int axi_fan_control_set_pwm_duty(const long val, 778412b410SNuno Sá struct axi_fan_control_data *ctl) 788412b410SNuno Sá { 798412b410SNuno Sá u32 pwm_period = axi_ioread(ADI_REG_PWM_PERIOD, ctl); 808412b410SNuno Sá u32 new_width; 818412b410SNuno Sá long __val = clamp_val(val, 0, SYSFS_PWM_MAX); 828412b410SNuno Sá 838412b410SNuno Sá new_width = DIV_ROUND_CLOSEST(__val * pwm_period, SYSFS_PWM_MAX); 848412b410SNuno Sá 858412b410SNuno Sá axi_iowrite(new_width, ADI_REG_PWM_WIDTH, ctl); 868412b410SNuno Sá 878412b410SNuno Sá return 0; 888412b410SNuno Sá } 898412b410SNuno Sá 908412b410SNuno Sá static long axi_fan_control_get_fan_rpm(const struct axi_fan_control_data *ctl) 918412b410SNuno Sá { 928412b410SNuno Sá const u32 tach = axi_ioread(ADI_REG_TACH_MEASUR, ctl); 938412b410SNuno Sá 948412b410SNuno Sá if (tach == 0) 958412b410SNuno Sá /* should we return error, EAGAIN maybe? */ 968412b410SNuno Sá return 0; 978412b410SNuno Sá /* 988412b410SNuno Sá * The tacho period should be: 998412b410SNuno Sá * TACH = 60/(ppr * rpm), where rpm is revolutions per second 1008412b410SNuno Sá * and ppr is pulses per revolution. 1018412b410SNuno Sá * Given the tacho period, we can multiply it by the input clock 1028412b410SNuno Sá * so that we know how many clocks we need to have this period. 1038412b410SNuno Sá * From this, we can derive the RPM value. 1048412b410SNuno Sá */ 1058412b410SNuno Sá return DIV_ROUND_CLOSEST(60 * ctl->clk_rate, ctl->ppr * tach); 1068412b410SNuno Sá } 1078412b410SNuno Sá 1088412b410SNuno Sá static int axi_fan_control_read_temp(struct device *dev, u32 attr, long *val) 1098412b410SNuno Sá { 1108412b410SNuno Sá struct axi_fan_control_data *ctl = dev_get_drvdata(dev); 1118412b410SNuno Sá long raw_temp; 1128412b410SNuno Sá 1138412b410SNuno Sá switch (attr) { 1148412b410SNuno Sá case hwmon_temp_input: 1158412b410SNuno Sá raw_temp = axi_ioread(ADI_REG_TEMPERATURE, ctl); 1168412b410SNuno Sá /* 1178412b410SNuno Sá * The formula for the temperature is: 1188412b410SNuno Sá * T = (ADC * 501.3743 / 2^bits) - 273.6777 1198412b410SNuno Sá * It's multiplied by 1000 to have millidegrees as 1208412b410SNuno Sá * specified by the hwmon sysfs interface. 1218412b410SNuno Sá */ 1228412b410SNuno Sá *val = ((raw_temp * 501374) >> 16) - 273677; 1238412b410SNuno Sá return 0; 1248412b410SNuno Sá default: 1258412b410SNuno Sá return -ENOTSUPP; 1268412b410SNuno Sá } 1278412b410SNuno Sá } 1288412b410SNuno Sá 1298412b410SNuno Sá static int axi_fan_control_read_fan(struct device *dev, u32 attr, long *val) 1308412b410SNuno Sá { 1318412b410SNuno Sá struct axi_fan_control_data *ctl = dev_get_drvdata(dev); 1328412b410SNuno Sá 1338412b410SNuno Sá switch (attr) { 1348412b410SNuno Sá case hwmon_fan_fault: 1358412b410SNuno Sá *val = ctl->fan_fault; 1368412b410SNuno Sá /* clear it now */ 1378412b410SNuno Sá ctl->fan_fault = 0; 1388412b410SNuno Sá return 0; 1398412b410SNuno Sá case hwmon_fan_input: 1408412b410SNuno Sá *val = axi_fan_control_get_fan_rpm(ctl); 1418412b410SNuno Sá return 0; 1428412b410SNuno Sá default: 1438412b410SNuno Sá return -ENOTSUPP; 1448412b410SNuno Sá } 1458412b410SNuno Sá } 1468412b410SNuno Sá 1478412b410SNuno Sá static int axi_fan_control_read_pwm(struct device *dev, u32 attr, long *val) 1488412b410SNuno Sá { 1498412b410SNuno Sá struct axi_fan_control_data *ctl = dev_get_drvdata(dev); 1508412b410SNuno Sá 1518412b410SNuno Sá switch (attr) { 1528412b410SNuno Sá case hwmon_pwm_input: 1538412b410SNuno Sá *val = axi_fan_control_get_pwm_duty(ctl); 1548412b410SNuno Sá return 0; 1558412b410SNuno Sá default: 1568412b410SNuno Sá return -ENOTSUPP; 1578412b410SNuno Sá } 1588412b410SNuno Sá } 1598412b410SNuno Sá 1608412b410SNuno Sá static int axi_fan_control_write_pwm(struct device *dev, u32 attr, long val) 1618412b410SNuno Sá { 1628412b410SNuno Sá struct axi_fan_control_data *ctl = dev_get_drvdata(dev); 1638412b410SNuno Sá 1648412b410SNuno Sá switch (attr) { 1658412b410SNuno Sá case hwmon_pwm_input: 1668412b410SNuno Sá return axi_fan_control_set_pwm_duty(val, ctl); 1678412b410SNuno Sá default: 1688412b410SNuno Sá return -ENOTSUPP; 1698412b410SNuno Sá } 1708412b410SNuno Sá } 1718412b410SNuno Sá 1728412b410SNuno Sá static int axi_fan_control_read_labels(struct device *dev, 1738412b410SNuno Sá enum hwmon_sensor_types type, 1748412b410SNuno Sá u32 attr, int channel, const char **str) 1758412b410SNuno Sá { 1768412b410SNuno Sá switch (type) { 1778412b410SNuno Sá case hwmon_fan: 1788412b410SNuno Sá *str = "FAN"; 1798412b410SNuno Sá return 0; 1808412b410SNuno Sá case hwmon_temp: 1818412b410SNuno Sá *str = "SYSMON4"; 1828412b410SNuno Sá return 0; 1838412b410SNuno Sá default: 1848412b410SNuno Sá return -ENOTSUPP; 1858412b410SNuno Sá } 1868412b410SNuno Sá } 1878412b410SNuno Sá 1888412b410SNuno Sá static int axi_fan_control_read(struct device *dev, 1898412b410SNuno Sá enum hwmon_sensor_types type, 1908412b410SNuno Sá u32 attr, int channel, long *val) 1918412b410SNuno Sá { 1928412b410SNuno Sá switch (type) { 1938412b410SNuno Sá case hwmon_fan: 1948412b410SNuno Sá return axi_fan_control_read_fan(dev, attr, val); 1958412b410SNuno Sá case hwmon_pwm: 1968412b410SNuno Sá return axi_fan_control_read_pwm(dev, attr, val); 1978412b410SNuno Sá case hwmon_temp: 1988412b410SNuno Sá return axi_fan_control_read_temp(dev, attr, val); 1998412b410SNuno Sá default: 2008412b410SNuno Sá return -ENOTSUPP; 2018412b410SNuno Sá } 2028412b410SNuno Sá } 2038412b410SNuno Sá 2048412b410SNuno Sá static int axi_fan_control_write(struct device *dev, 2058412b410SNuno Sá enum hwmon_sensor_types type, 2068412b410SNuno Sá u32 attr, int channel, long val) 2078412b410SNuno Sá { 2088412b410SNuno Sá switch (type) { 2098412b410SNuno Sá case hwmon_pwm: 2108412b410SNuno Sá return axi_fan_control_write_pwm(dev, attr, val); 2118412b410SNuno Sá default: 2128412b410SNuno Sá return -ENOTSUPP; 2138412b410SNuno Sá } 2148412b410SNuno Sá } 2158412b410SNuno Sá 2168412b410SNuno Sá static umode_t axi_fan_control_fan_is_visible(const u32 attr) 2178412b410SNuno Sá { 2188412b410SNuno Sá switch (attr) { 2198412b410SNuno Sá case hwmon_fan_input: 2208412b410SNuno Sá case hwmon_fan_fault: 2218412b410SNuno Sá case hwmon_fan_label: 2228412b410SNuno Sá return 0444; 2238412b410SNuno Sá default: 2248412b410SNuno Sá return 0; 2258412b410SNuno Sá } 2268412b410SNuno Sá } 2278412b410SNuno Sá 2288412b410SNuno Sá static umode_t axi_fan_control_pwm_is_visible(const u32 attr) 2298412b410SNuno Sá { 2308412b410SNuno Sá switch (attr) { 2318412b410SNuno Sá case hwmon_pwm_input: 2328412b410SNuno Sá return 0644; 2338412b410SNuno Sá default: 2348412b410SNuno Sá return 0; 2358412b410SNuno Sá } 2368412b410SNuno Sá } 2378412b410SNuno Sá 2388412b410SNuno Sá static umode_t axi_fan_control_temp_is_visible(const u32 attr) 2398412b410SNuno Sá { 2408412b410SNuno Sá switch (attr) { 2418412b410SNuno Sá case hwmon_temp_input: 2428412b410SNuno Sá case hwmon_temp_label: 2438412b410SNuno Sá return 0444; 2448412b410SNuno Sá default: 2458412b410SNuno Sá return 0; 2468412b410SNuno Sá } 2478412b410SNuno Sá } 2488412b410SNuno Sá 2498412b410SNuno Sá static umode_t axi_fan_control_is_visible(const void *data, 2508412b410SNuno Sá enum hwmon_sensor_types type, 2518412b410SNuno Sá u32 attr, int channel) 2528412b410SNuno Sá { 2538412b410SNuno Sá switch (type) { 2548412b410SNuno Sá case hwmon_fan: 2558412b410SNuno Sá return axi_fan_control_fan_is_visible(attr); 2568412b410SNuno Sá case hwmon_pwm: 2578412b410SNuno Sá return axi_fan_control_pwm_is_visible(attr); 2588412b410SNuno Sá case hwmon_temp: 2598412b410SNuno Sá return axi_fan_control_temp_is_visible(attr); 2608412b410SNuno Sá default: 2618412b410SNuno Sá return 0; 2628412b410SNuno Sá } 2638412b410SNuno Sá } 2648412b410SNuno Sá 2658412b410SNuno Sá /* 2668412b410SNuno Sá * This core has two main ways of changing the PWM duty cycle. It is done, 2678412b410SNuno Sá * either by a request from userspace (writing on pwm1_input) or by the 2688412b410SNuno Sá * core itself. When the change is done by the core, it will use predefined 2698412b410SNuno Sá * parameters to evaluate the tach signal and, on that case we cannot set them. 2708412b410SNuno Sá * On the other hand, when the request is done by the user, with some arbitrary 2718412b410SNuno Sá * value that the core does not now about, we have to provide the tach 2728412b410SNuno Sá * parameters so that, the core can evaluate the signal. On the IRQ handler we 2738412b410SNuno Sá * distinguish this by using the ADI_IRQ_SRC_TEMP_INCREASE interrupt. This tell 2748412b410SNuno Sá * us that the CORE requested a new duty cycle. After this, there is 5s delay 2758412b410SNuno Sá * on which the core waits for the fan rotation speed to stabilize. After this 2768412b410SNuno Sá * we get ADI_IRQ_SRC_PWM_CHANGED irq where we will decide if we need to set 2778412b410SNuno Sá * the tach parameters or not on the next tach measurement cycle (corresponding 2788412b410SNuno Sá * already to the ney duty cycle) based on the %ctl->hw_pwm_req flag. 2798412b410SNuno Sá */ 2808412b410SNuno Sá static irqreturn_t axi_fan_control_irq_handler(int irq, void *data) 2818412b410SNuno Sá { 2828412b410SNuno Sá struct axi_fan_control_data *ctl = (struct axi_fan_control_data *)data; 2838412b410SNuno Sá u32 irq_pending = axi_ioread(ADI_REG_IRQ_PENDING, ctl); 2848412b410SNuno Sá u32 clear_mask; 2858412b410SNuno Sá 286*e66705deSNuno Sá if (irq_pending & ADI_IRQ_SRC_TEMP_INCREASE) 287*e66705deSNuno Sá /* hardware requested a new pwm */ 288*e66705deSNuno Sá ctl->hw_pwm_req = true; 2898412b410SNuno Sá 2908412b410SNuno Sá if (irq_pending & ADI_IRQ_SRC_PWM_CHANGED) { 2918412b410SNuno Sá /* 2928412b410SNuno Sá * if the pwm changes on behalf of software, 2938412b410SNuno Sá * we need to provide new tacho parameters to the core. 2948412b410SNuno Sá * Wait for the next measurement for that... 2958412b410SNuno Sá */ 2968412b410SNuno Sá if (!ctl->hw_pwm_req) { 2978412b410SNuno Sá ctl->update_tacho_params = true; 2988412b410SNuno Sá } else { 2998412b410SNuno Sá ctl->hw_pwm_req = false; 3008412b410SNuno Sá sysfs_notify(&ctl->hdev->kobj, NULL, "pwm1"); 3018412b410SNuno Sá } 3028412b410SNuno Sá } 3038412b410SNuno Sá 304*e66705deSNuno Sá if (irq_pending & ADI_IRQ_SRC_NEW_MEASUR) { 305*e66705deSNuno Sá if (ctl->update_tacho_params) { 306*e66705deSNuno Sá u32 new_tach = axi_ioread(ADI_REG_TACH_MEASUR, ctl); 307*e66705deSNuno Sá /* get 25% tolerance */ 308*e66705deSNuno Sá u32 tach_tol = DIV_ROUND_CLOSEST(new_tach * 25, 100); 309*e66705deSNuno Sá 310*e66705deSNuno Sá /* set new tacho parameters */ 311*e66705deSNuno Sá axi_iowrite(new_tach, ADI_REG_TACH_PERIOD, ctl); 312*e66705deSNuno Sá axi_iowrite(tach_tol, ADI_REG_TACH_TOLERANCE, ctl); 313*e66705deSNuno Sá ctl->update_tacho_params = false; 314*e66705deSNuno Sá } 315*e66705deSNuno Sá } 3168412b410SNuno Sá 3178412b410SNuno Sá if (irq_pending & ADI_IRQ_SRC_TACH_ERR) 3188412b410SNuno Sá ctl->fan_fault = 1; 3198412b410SNuno Sá 3208412b410SNuno Sá /* clear all interrupts */ 3218412b410SNuno Sá clear_mask = irq_pending & ADI_IRQ_SRC_MASK; 3228412b410SNuno Sá axi_iowrite(clear_mask, ADI_REG_IRQ_PENDING, ctl); 3238412b410SNuno Sá 3248412b410SNuno Sá return IRQ_HANDLED; 3258412b410SNuno Sá } 3268412b410SNuno Sá 3278412b410SNuno Sá static int axi_fan_control_init(struct axi_fan_control_data *ctl, 3288412b410SNuno Sá const struct device_node *np) 3298412b410SNuno Sá { 3308412b410SNuno Sá int ret; 3318412b410SNuno Sá 3328412b410SNuno Sá /* get fan pulses per revolution */ 3338412b410SNuno Sá ret = of_property_read_u32(np, "pulses-per-revolution", &ctl->ppr); 3348412b410SNuno Sá if (ret) 3358412b410SNuno Sá return ret; 3368412b410SNuno Sá 3378412b410SNuno Sá /* 1, 2 and 4 are the typical and accepted values */ 3388412b410SNuno Sá if (ctl->ppr != 1 && ctl->ppr != 2 && ctl->ppr != 4) 3398412b410SNuno Sá return -EINVAL; 3408412b410SNuno Sá /* 3418412b410SNuno Sá * Enable all IRQs 3428412b410SNuno Sá */ 3438412b410SNuno Sá axi_iowrite(ADI_IRQ_MASK_OUT_ALL & 3448412b410SNuno Sá ~(ADI_IRQ_SRC_NEW_MEASUR | ADI_IRQ_SRC_TACH_ERR | 3458412b410SNuno Sá ADI_IRQ_SRC_PWM_CHANGED | ADI_IRQ_SRC_TEMP_INCREASE), 3468412b410SNuno Sá ADI_REG_IRQ_MASK, ctl); 3478412b410SNuno Sá 3488412b410SNuno Sá /* bring the device out of reset */ 3498412b410SNuno Sá axi_iowrite(0x01, ADI_REG_RSTN, ctl); 3508412b410SNuno Sá 3518412b410SNuno Sá return ret; 3528412b410SNuno Sá } 3538412b410SNuno Sá 354a3933625SNuno Sá static void axi_fan_control_clk_disable(void *clk) 355a3933625SNuno Sá { 356a3933625SNuno Sá clk_disable_unprepare(clk); 357a3933625SNuno Sá } 358a3933625SNuno Sá 3598412b410SNuno Sá static const struct hwmon_channel_info *axi_fan_control_info[] = { 3608412b410SNuno Sá HWMON_CHANNEL_INFO(pwm, HWMON_PWM_INPUT), 3618412b410SNuno Sá HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT | HWMON_F_FAULT | HWMON_F_LABEL), 3628412b410SNuno Sá HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_LABEL), 3638412b410SNuno Sá NULL 3648412b410SNuno Sá }; 3658412b410SNuno Sá 3668412b410SNuno Sá static const struct hwmon_ops axi_fan_control_hwmon_ops = { 3678412b410SNuno Sá .is_visible = axi_fan_control_is_visible, 3688412b410SNuno Sá .read = axi_fan_control_read, 3698412b410SNuno Sá .write = axi_fan_control_write, 3708412b410SNuno Sá .read_string = axi_fan_control_read_labels, 3718412b410SNuno Sá }; 3728412b410SNuno Sá 3738412b410SNuno Sá static const struct hwmon_chip_info axi_chip_info = { 3748412b410SNuno Sá .ops = &axi_fan_control_hwmon_ops, 3758412b410SNuno Sá .info = axi_fan_control_info, 3768412b410SNuno Sá }; 3778412b410SNuno Sá 3788412b410SNuno Sá static const u32 version_1_0_0 = ADI_AXI_PCORE_VER(1, 0, 'a'); 3798412b410SNuno Sá 3808412b410SNuno Sá static const struct of_device_id axi_fan_control_of_match[] = { 3818412b410SNuno Sá { .compatible = "adi,axi-fan-control-1.00.a", 3828412b410SNuno Sá .data = (void *)&version_1_0_0}, 3838412b410SNuno Sá {}, 3848412b410SNuno Sá }; 3858412b410SNuno Sá MODULE_DEVICE_TABLE(of, axi_fan_control_of_match); 3868412b410SNuno Sá 3878412b410SNuno Sá static int axi_fan_control_probe(struct platform_device *pdev) 3888412b410SNuno Sá { 3898412b410SNuno Sá struct axi_fan_control_data *ctl; 3908412b410SNuno Sá struct clk *clk; 3918412b410SNuno Sá const struct of_device_id *id; 3928412b410SNuno Sá const char *name = "axi_fan_control"; 3938412b410SNuno Sá u32 version; 3948412b410SNuno Sá int ret; 3958412b410SNuno Sá 3968412b410SNuno Sá id = of_match_node(axi_fan_control_of_match, pdev->dev.of_node); 3978412b410SNuno Sá if (!id) 3988412b410SNuno Sá return -EINVAL; 3998412b410SNuno Sá 4008412b410SNuno Sá ctl = devm_kzalloc(&pdev->dev, sizeof(*ctl), GFP_KERNEL); 4018412b410SNuno Sá if (!ctl) 4028412b410SNuno Sá return -ENOMEM; 4038412b410SNuno Sá 4048412b410SNuno Sá ctl->base = devm_platform_ioremap_resource(pdev, 0); 4058412b410SNuno Sá if (IS_ERR(ctl->base)) 4068412b410SNuno Sá return PTR_ERR(ctl->base); 4078412b410SNuno Sá 4088412b410SNuno Sá clk = devm_clk_get(&pdev->dev, NULL); 4098412b410SNuno Sá if (IS_ERR(clk)) { 4108412b410SNuno Sá dev_err(&pdev->dev, "clk_get failed with %ld\n", PTR_ERR(clk)); 4118412b410SNuno Sá return PTR_ERR(clk); 4128412b410SNuno Sá } 4138412b410SNuno Sá 414a3933625SNuno Sá ret = clk_prepare_enable(clk); 415a3933625SNuno Sá if (ret) 416a3933625SNuno Sá return ret; 417a3933625SNuno Sá 418a3933625SNuno Sá ret = devm_add_action_or_reset(&pdev->dev, axi_fan_control_clk_disable, clk); 419a3933625SNuno Sá if (ret) 420a3933625SNuno Sá return ret; 421a3933625SNuno Sá 4228412b410SNuno Sá ctl->clk_rate = clk_get_rate(clk); 4238412b410SNuno Sá if (!ctl->clk_rate) 4248412b410SNuno Sá return -EINVAL; 4258412b410SNuno Sá 4268412b410SNuno Sá version = axi_ioread(ADI_AXI_REG_VERSION, ctl); 4278412b410SNuno Sá if (ADI_AXI_PCORE_VER_MAJOR(version) != 4288412b410SNuno Sá ADI_AXI_PCORE_VER_MAJOR((*(u32 *)id->data))) { 4298412b410SNuno Sá dev_err(&pdev->dev, "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n", 4308412b410SNuno Sá ADI_AXI_PCORE_VER_MAJOR((*(u32 *)id->data)), 4318412b410SNuno Sá ADI_AXI_PCORE_VER_MINOR((*(u32 *)id->data)), 4328412b410SNuno Sá ADI_AXI_PCORE_VER_PATCH((*(u32 *)id->data)), 4338412b410SNuno Sá ADI_AXI_PCORE_VER_MAJOR(version), 4348412b410SNuno Sá ADI_AXI_PCORE_VER_MINOR(version), 4358412b410SNuno Sá ADI_AXI_PCORE_VER_PATCH(version)); 4368412b410SNuno Sá return -ENODEV; 4378412b410SNuno Sá } 4388412b410SNuno Sá 4398412b410SNuno Sá ctl->irq = platform_get_irq(pdev, 0); 4408412b410SNuno Sá if (ctl->irq < 0) 4418412b410SNuno Sá return ctl->irq; 4428412b410SNuno Sá 4438412b410SNuno Sá ret = devm_request_threaded_irq(&pdev->dev, ctl->irq, NULL, 4448412b410SNuno Sá axi_fan_control_irq_handler, 4458412b410SNuno Sá IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 4468412b410SNuno Sá pdev->driver_override, ctl); 4478412b410SNuno Sá if (ret) { 4488412b410SNuno Sá dev_err(&pdev->dev, "failed to request an irq, %d", ret); 4498412b410SNuno Sá return ret; 4508412b410SNuno Sá } 4518412b410SNuno Sá 4528412b410SNuno Sá ret = axi_fan_control_init(ctl, pdev->dev.of_node); 4538412b410SNuno Sá if (ret) { 4548412b410SNuno Sá dev_err(&pdev->dev, "Failed to initialize device\n"); 4558412b410SNuno Sá return ret; 4568412b410SNuno Sá } 4578412b410SNuno Sá 4588412b410SNuno Sá ctl->hdev = devm_hwmon_device_register_with_info(&pdev->dev, 4598412b410SNuno Sá name, 4608412b410SNuno Sá ctl, 4618412b410SNuno Sá &axi_chip_info, 4628412b410SNuno Sá NULL); 4638412b410SNuno Sá 4648412b410SNuno Sá return PTR_ERR_OR_ZERO(ctl->hdev); 4658412b410SNuno Sá } 4668412b410SNuno Sá 4678412b410SNuno Sá static struct platform_driver axi_fan_control_driver = { 4688412b410SNuno Sá .driver = { 4698412b410SNuno Sá .name = "axi_fan_control_driver", 4708412b410SNuno Sá .of_match_table = axi_fan_control_of_match, 4718412b410SNuno Sá }, 4728412b410SNuno Sá .probe = axi_fan_control_probe, 4738412b410SNuno Sá }; 4748412b410SNuno Sá module_platform_driver(axi_fan_control_driver); 4758412b410SNuno Sá 4768412b410SNuno Sá MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>"); 4778412b410SNuno Sá MODULE_DESCRIPTION("Analog Devices Fan Control HDL CORE driver"); 4788412b410SNuno Sá MODULE_LICENSE("GPL"); 479