14f567b9fSSandeep Singh /* SPDX-License-Identifier: GPL-2.0-or-later */ 24f567b9fSSandeep Singh /* 34f567b9fSSandeep Singh * AMD MP2 PCIe communication driver 44f567b9fSSandeep Singh * Copyright 2020 Advanced Micro Devices, Inc. 54f567b9fSSandeep Singh * Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 64f567b9fSSandeep Singh * Sandeep Singh <Sandeep.singh@amd.com> 74f567b9fSSandeep Singh */ 84f567b9fSSandeep Singh 94f567b9fSSandeep Singh #ifndef PCIE_MP2_AMD_H 104f567b9fSSandeep Singh #define PCIE_MP2_AMD_H 114f567b9fSSandeep Singh 124f567b9fSSandeep Singh #include <linux/pci.h> 134f567b9fSSandeep Singh 144f567b9fSSandeep Singh #define PCI_DEVICE_ID_AMD_MP2 0x15E4 154f567b9fSSandeep Singh 164f567b9fSSandeep Singh #define ENABLE_SENSOR 1 174f567b9fSSandeep Singh #define DISABLE_SENSOR 2 184f567b9fSSandeep Singh #define STOP_ALL_SENSORS 8 194f567b9fSSandeep Singh 204f567b9fSSandeep Singh /* MP2 C2P Message Registers */ 214f567b9fSSandeep Singh #define AMD_C2P_MSG0 0x10500 224f567b9fSSandeep Singh #define AMD_C2P_MSG1 0x10504 234f567b9fSSandeep Singh #define AMD_C2P_MSG2 0x10508 244f567b9fSSandeep Singh 254f567b9fSSandeep Singh /* MP2 P2C Message Registers */ 264f567b9fSSandeep Singh #define AMD_P2C_MSG3 0x1068C /* Supported Sensors info */ 274f567b9fSSandeep Singh 284f567b9fSSandeep Singh /* SFH Command register */ 294f567b9fSSandeep Singh union sfh_cmd_base { 304f567b9fSSandeep Singh u32 ul; 314f567b9fSSandeep Singh struct { 324f567b9fSSandeep Singh u32 cmd_id : 8; 334f567b9fSSandeep Singh u32 sensor_id : 8; 344f567b9fSSandeep Singh u32 period : 16; 354f567b9fSSandeep Singh } s; 364f567b9fSSandeep Singh }; 374f567b9fSSandeep Singh 384f567b9fSSandeep Singh union sfh_cmd_param { 394f567b9fSSandeep Singh u32 ul; 404f567b9fSSandeep Singh struct { 414f567b9fSSandeep Singh u32 buf_layout : 2; 424f567b9fSSandeep Singh u32 buf_length : 6; 434f567b9fSSandeep Singh u32 rsvd : 24; 444f567b9fSSandeep Singh } s; 454f567b9fSSandeep Singh }; 464f567b9fSSandeep Singh 474f567b9fSSandeep Singh struct sfh_cmd_reg { 484f567b9fSSandeep Singh union sfh_cmd_base cmd_base; 494f567b9fSSandeep Singh union sfh_cmd_param cmd_param; 504f567b9fSSandeep Singh phys_addr_t phys_addr; 514f567b9fSSandeep Singh }; 524f567b9fSSandeep Singh 534f567b9fSSandeep Singh enum sensor_idx { 544f567b9fSSandeep Singh accel_idx = 0, 554f567b9fSSandeep Singh gyro_idx = 1, 564f567b9fSSandeep Singh mag_idx = 2, 574f567b9fSSandeep Singh als_idx = 19 584f567b9fSSandeep Singh }; 594f567b9fSSandeep Singh 604f567b9fSSandeep Singh struct amd_mp2_dev { 614f567b9fSSandeep Singh struct pci_dev *pdev; 624f567b9fSSandeep Singh struct amdtp_cl_data *cl_data; 634f567b9fSSandeep Singh void __iomem *mmio; 644f567b9fSSandeep Singh u32 activecontrolstatus; 654f567b9fSSandeep Singh }; 664f567b9fSSandeep Singh 674f567b9fSSandeep Singh struct amd_mp2_sensor_info { 684f567b9fSSandeep Singh u8 sensor_idx; 694f567b9fSSandeep Singh u32 period; 70*de30491eSArnd Bergmann dma_addr_t dma_address; 714f567b9fSSandeep Singh }; 724f567b9fSSandeep Singh 734f567b9fSSandeep Singh void amd_start_sensor(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info); 744f567b9fSSandeep Singh void amd_stop_sensor(struct amd_mp2_dev *privdata, u16 sensor_idx); 754f567b9fSSandeep Singh void amd_stop_all_sensors(struct amd_mp2_dev *privdata); 764f567b9fSSandeep Singh int amd_mp2_get_sensor_num(struct amd_mp2_dev *privdata, u8 *sensor_id); 774f567b9fSSandeep Singh int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata); 784f567b9fSSandeep Singh int amd_sfh_hid_client_deinit(struct amd_mp2_dev *privdata); 794f567b9fSSandeep Singh #endif 80