14f567b9fSSandeep Singh /* SPDX-License-Identifier: GPL-2.0-or-later */ 24f567b9fSSandeep Singh /* 34f567b9fSSandeep Singh * AMD MP2 PCIe communication driver 4f75203cdSBasavaraj Natikar * Copyright 2020-2021 Advanced Micro Devices, Inc. 54f567b9fSSandeep Singh * Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 64f567b9fSSandeep Singh * Sandeep Singh <Sandeep.singh@amd.com> 7f75203cdSBasavaraj Natikar * Basavaraj Natikar <Basavaraj.Natikar@amd.com> 84f567b9fSSandeep Singh */ 94f567b9fSSandeep Singh 104f567b9fSSandeep Singh #ifndef PCIE_MP2_AMD_H 114f567b9fSSandeep Singh #define PCIE_MP2_AMD_H 124f567b9fSSandeep Singh 134f567b9fSSandeep Singh #include <linux/pci.h> 140aad9c95SBasavaraj Natikar #include "amd_sfh_hid.h" 154f567b9fSSandeep Singh 164f567b9fSSandeep Singh #define PCI_DEVICE_ID_AMD_MP2 0x15E4 174f567b9fSSandeep Singh 184f567b9fSSandeep Singh #define ENABLE_SENSOR 1 194f567b9fSSandeep Singh #define DISABLE_SENSOR 2 204f567b9fSSandeep Singh #define STOP_ALL_SENSORS 8 214f567b9fSSandeep Singh 224f567b9fSSandeep Singh /* MP2 C2P Message Registers */ 234f567b9fSSandeep Singh #define AMD_C2P_MSG0 0x10500 244f567b9fSSandeep Singh #define AMD_C2P_MSG1 0x10504 254f567b9fSSandeep Singh #define AMD_C2P_MSG2 0x10508 264f567b9fSSandeep Singh 27f264481aSBasavaraj Natikar #define AMD_C2P_MSG(regno) (0x10500 + ((regno) * 4)) 28173709f5SBasavaraj Natikar #define AMD_P2C_MSG(regno) (0x10680 + ((regno) * 4)) 29f264481aSBasavaraj Natikar 304f567b9fSSandeep Singh /* MP2 P2C Message Registers */ 314f567b9fSSandeep Singh #define AMD_P2C_MSG3 0x1068C /* Supported Sensors info */ 324f567b9fSSandeep Singh 33f264481aSBasavaraj Natikar #define V2_STATUS 0x2 34f264481aSBasavaraj Natikar 35173709f5SBasavaraj Natikar #define SENSOR_ENABLED 4 36173709f5SBasavaraj Natikar #define SENSOR_DISABLED 5 37173709f5SBasavaraj Natikar 3824a31ea9SBasavaraj Natikar #define HPD_IDX 16 3924a31ea9SBasavaraj Natikar 400873d1afSBasavaraj Natikar #define AMD_SFH_IDLE_LOOP 200 410873d1afSBasavaraj Natikar 42*b5d7f43eSBasavaraj Natikar #define SENSOR_DISCOVERY_STATUS_MASK GENMASK(5, 3) 43*b5d7f43eSBasavaraj Natikar #define SENSOR_DISCOVERY_STATUS_SHIFT 3 44*b5d7f43eSBasavaraj Natikar 454f567b9fSSandeep Singh /* SFH Command register */ 464f567b9fSSandeep Singh union sfh_cmd_base { 474f567b9fSSandeep Singh u32 ul; 484f567b9fSSandeep Singh struct { 494f567b9fSSandeep Singh u32 cmd_id : 8; 504f567b9fSSandeep Singh u32 sensor_id : 8; 514f567b9fSSandeep Singh u32 period : 16; 524f567b9fSSandeep Singh } s; 53f264481aSBasavaraj Natikar struct { 54f264481aSBasavaraj Natikar u32 cmd_id : 4; 55aa0b724aSBasavaraj Natikar u32 intr_disable : 1; 56f264481aSBasavaraj Natikar u32 rsvd1 : 3; 57f264481aSBasavaraj Natikar u32 length : 7; 58f264481aSBasavaraj Natikar u32 mem_type : 1; 59f264481aSBasavaraj Natikar u32 sensor_id : 8; 60f264481aSBasavaraj Natikar u32 period : 8; 61f264481aSBasavaraj Natikar } cmd_v2; 624f567b9fSSandeep Singh }; 634f567b9fSSandeep Singh 64173709f5SBasavaraj Natikar union cmd_response { 65173709f5SBasavaraj Natikar u32 resp; 66173709f5SBasavaraj Natikar struct { 67173709f5SBasavaraj Natikar u32 status : 2; 68173709f5SBasavaraj Natikar u32 out_in_c2p : 1; 69173709f5SBasavaraj Natikar u32 rsvd1 : 1; 70173709f5SBasavaraj Natikar u32 response : 4; 71173709f5SBasavaraj Natikar u32 sub_cmd : 8; 72173709f5SBasavaraj Natikar u32 sensor_id : 6; 73173709f5SBasavaraj Natikar u32 rsvd2 : 10; 74173709f5SBasavaraj Natikar } response_v2; 75173709f5SBasavaraj Natikar }; 76173709f5SBasavaraj Natikar 774f567b9fSSandeep Singh union sfh_cmd_param { 784f567b9fSSandeep Singh u32 ul; 794f567b9fSSandeep Singh struct { 804f567b9fSSandeep Singh u32 buf_layout : 2; 814f567b9fSSandeep Singh u32 buf_length : 6; 824f567b9fSSandeep Singh u32 rsvd : 24; 834f567b9fSSandeep Singh } s; 844f567b9fSSandeep Singh }; 854f567b9fSSandeep Singh 864f567b9fSSandeep Singh struct sfh_cmd_reg { 874f567b9fSSandeep Singh union sfh_cmd_base cmd_base; 884f567b9fSSandeep Singh union sfh_cmd_param cmd_param; 894f567b9fSSandeep Singh phys_addr_t phys_addr; 904f567b9fSSandeep Singh }; 914f567b9fSSandeep Singh 924f567b9fSSandeep Singh enum sensor_idx { 934f567b9fSSandeep Singh accel_idx = 0, 944f567b9fSSandeep Singh gyro_idx = 1, 954f567b9fSSandeep Singh mag_idx = 2, 964f567b9fSSandeep Singh als_idx = 19 974f567b9fSSandeep Singh }; 984f567b9fSSandeep Singh 994f567b9fSSandeep Singh struct amd_mp2_dev { 1004f567b9fSSandeep Singh struct pci_dev *pdev; 1014f567b9fSSandeep Singh struct amdtp_cl_data *cl_data; 1024f567b9fSSandeep Singh void __iomem *mmio; 103f264481aSBasavaraj Natikar const struct amd_mp2_ops *mp2_ops; 1040aad9c95SBasavaraj Natikar struct amd_input_data in_data; 105f264481aSBasavaraj Natikar /* mp2 active control status */ 106f264481aSBasavaraj Natikar u32 mp2_acs; 1074f567b9fSSandeep Singh }; 1084f567b9fSSandeep Singh 1094f567b9fSSandeep Singh struct amd_mp2_sensor_info { 1104f567b9fSSandeep Singh u8 sensor_idx; 1114f567b9fSSandeep Singh u32 period; 112de30491eSArnd Bergmann dma_addr_t dma_address; 1134f567b9fSSandeep Singh }; 1144f567b9fSSandeep Singh 115f264481aSBasavaraj Natikar enum mem_use_type { 116f264481aSBasavaraj Natikar USE_DRAM, 117f264481aSBasavaraj Natikar USE_C2P_REG, 118f264481aSBasavaraj Natikar }; 119f264481aSBasavaraj Natikar 12024a31ea9SBasavaraj Natikar struct hpd_status { 12124a31ea9SBasavaraj Natikar union { 12224a31ea9SBasavaraj Natikar struct { 12324a31ea9SBasavaraj Natikar u32 human_presence_report : 4; 12424a31ea9SBasavaraj Natikar u32 human_presence_actual : 4; 12524a31ea9SBasavaraj Natikar u32 probablity : 8; 12624a31ea9SBasavaraj Natikar u32 object_distance : 16; 12724a31ea9SBasavaraj Natikar } shpd; 12824a31ea9SBasavaraj Natikar u32 val; 12924a31ea9SBasavaraj Natikar }; 13024a31ea9SBasavaraj Natikar }; 13124a31ea9SBasavaraj Natikar 1324f567b9fSSandeep Singh void amd_start_sensor(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info); 1334f567b9fSSandeep Singh void amd_stop_sensor(struct amd_mp2_dev *privdata, u16 sensor_idx); 1344f567b9fSSandeep Singh void amd_stop_all_sensors(struct amd_mp2_dev *privdata); 1354f567b9fSSandeep Singh int amd_mp2_get_sensor_num(struct amd_mp2_dev *privdata, u8 *sensor_id); 1364f567b9fSSandeep Singh int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata); 1374f567b9fSSandeep Singh int amd_sfh_hid_client_deinit(struct amd_mp2_dev *privdata); 1380873d1afSBasavaraj Natikar u32 amd_sfh_wait_for_response(struct amd_mp2_dev *mp2, u8 sid, u32 sensor_sts); 1390873d1afSBasavaraj Natikar void amd_mp2_suspend(struct amd_mp2_dev *mp2); 1400873d1afSBasavaraj Natikar void amd_mp2_resume(struct amd_mp2_dev *mp2); 141f264481aSBasavaraj Natikar 142f264481aSBasavaraj Natikar struct amd_mp2_ops { 143f264481aSBasavaraj Natikar void (*start)(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info); 144f264481aSBasavaraj Natikar void (*stop)(struct amd_mp2_dev *privdata, u16 sensor_idx); 145f264481aSBasavaraj Natikar void (*stop_all)(struct amd_mp2_dev *privdata); 146173709f5SBasavaraj Natikar int (*response)(struct amd_mp2_dev *mp2, u8 sid, u32 sensor_sts); 147fb75a379SBasavaraj Natikar void (*clear_intr)(struct amd_mp2_dev *privdata); 1487f016b35SBasavaraj Natikar int (*init_intr)(struct amd_mp2_dev *privdata); 149*b5d7f43eSBasavaraj Natikar int (*discovery_status)(struct amd_mp2_dev *privdata); 150f264481aSBasavaraj Natikar }; 1514f567b9fSSandeep Singh #endif 152