xref: /openbmc/linux/drivers/hid/amd-sfh-hid/amd_sfh_pcie.h (revision 4f567b9f8141a86c7d878fadf136e5d1408e3e61)
1*4f567b9fSSandeep Singh /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4f567b9fSSandeep Singh /*
3*4f567b9fSSandeep Singh  * AMD MP2 PCIe communication driver
4*4f567b9fSSandeep Singh  * Copyright 2020 Advanced Micro Devices, Inc.
5*4f567b9fSSandeep Singh  * Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
6*4f567b9fSSandeep Singh  *	    Sandeep Singh <Sandeep.singh@amd.com>
7*4f567b9fSSandeep Singh  */
8*4f567b9fSSandeep Singh 
9*4f567b9fSSandeep Singh #ifndef PCIE_MP2_AMD_H
10*4f567b9fSSandeep Singh #define PCIE_MP2_AMD_H
11*4f567b9fSSandeep Singh 
12*4f567b9fSSandeep Singh #include <linux/pci.h>
13*4f567b9fSSandeep Singh 
14*4f567b9fSSandeep Singh #define PCI_DEVICE_ID_AMD_MP2	0x15E4
15*4f567b9fSSandeep Singh 
16*4f567b9fSSandeep Singh #define ENABLE_SENSOR		1
17*4f567b9fSSandeep Singh #define DISABLE_SENSOR		2
18*4f567b9fSSandeep Singh #define STOP_ALL_SENSORS	8
19*4f567b9fSSandeep Singh 
20*4f567b9fSSandeep Singh /* MP2 C2P Message Registers */
21*4f567b9fSSandeep Singh #define AMD_C2P_MSG0	0x10500
22*4f567b9fSSandeep Singh #define AMD_C2P_MSG1	0x10504
23*4f567b9fSSandeep Singh #define AMD_C2P_MSG2	0x10508
24*4f567b9fSSandeep Singh 
25*4f567b9fSSandeep Singh /* MP2 P2C Message Registers */
26*4f567b9fSSandeep Singh #define AMD_P2C_MSG3	0x1068C /* Supported Sensors info */
27*4f567b9fSSandeep Singh 
28*4f567b9fSSandeep Singh /* SFH Command register */
29*4f567b9fSSandeep Singh union sfh_cmd_base {
30*4f567b9fSSandeep Singh 	u32 ul;
31*4f567b9fSSandeep Singh 	struct {
32*4f567b9fSSandeep Singh 		u32 cmd_id : 8;
33*4f567b9fSSandeep Singh 		u32 sensor_id : 8;
34*4f567b9fSSandeep Singh 		u32 period : 16;
35*4f567b9fSSandeep Singh 	} s;
36*4f567b9fSSandeep Singh };
37*4f567b9fSSandeep Singh 
38*4f567b9fSSandeep Singh union sfh_cmd_param {
39*4f567b9fSSandeep Singh 	u32 ul;
40*4f567b9fSSandeep Singh 	struct {
41*4f567b9fSSandeep Singh 		u32 buf_layout : 2;
42*4f567b9fSSandeep Singh 		u32 buf_length : 6;
43*4f567b9fSSandeep Singh 		u32 rsvd : 24;
44*4f567b9fSSandeep Singh 	} s;
45*4f567b9fSSandeep Singh };
46*4f567b9fSSandeep Singh 
47*4f567b9fSSandeep Singh struct sfh_cmd_reg {
48*4f567b9fSSandeep Singh 	union sfh_cmd_base cmd_base;
49*4f567b9fSSandeep Singh 	union sfh_cmd_param cmd_param;
50*4f567b9fSSandeep Singh 	phys_addr_t phys_addr;
51*4f567b9fSSandeep Singh };
52*4f567b9fSSandeep Singh 
53*4f567b9fSSandeep Singh enum sensor_idx {
54*4f567b9fSSandeep Singh 	accel_idx = 0,
55*4f567b9fSSandeep Singh 	gyro_idx = 1,
56*4f567b9fSSandeep Singh 	mag_idx = 2,
57*4f567b9fSSandeep Singh 	als_idx = 19
58*4f567b9fSSandeep Singh };
59*4f567b9fSSandeep Singh 
60*4f567b9fSSandeep Singh struct amd_mp2_dev {
61*4f567b9fSSandeep Singh 	struct pci_dev *pdev;
62*4f567b9fSSandeep Singh 	struct amdtp_cl_data *cl_data;
63*4f567b9fSSandeep Singh 	void __iomem *mmio;
64*4f567b9fSSandeep Singh 	u32 activecontrolstatus;
65*4f567b9fSSandeep Singh };
66*4f567b9fSSandeep Singh 
67*4f567b9fSSandeep Singh struct amd_mp2_sensor_info {
68*4f567b9fSSandeep Singh 	u8 sensor_idx;
69*4f567b9fSSandeep Singh 	u32 period;
70*4f567b9fSSandeep Singh 	phys_addr_t phys_address;
71*4f567b9fSSandeep Singh };
72*4f567b9fSSandeep Singh 
73*4f567b9fSSandeep Singh void amd_start_sensor(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info);
74*4f567b9fSSandeep Singh void amd_stop_sensor(struct amd_mp2_dev *privdata, u16 sensor_idx);
75*4f567b9fSSandeep Singh void amd_stop_all_sensors(struct amd_mp2_dev *privdata);
76*4f567b9fSSandeep Singh int amd_mp2_get_sensor_num(struct amd_mp2_dev *privdata, u8 *sensor_id);
77*4f567b9fSSandeep Singh int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata);
78*4f567b9fSSandeep Singh int amd_sfh_hid_client_deinit(struct amd_mp2_dev *privdata);
79*4f567b9fSSandeep Singh #endif
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