1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Tegra host1x driver 4 * 5 * Copyright (c) 2010-2013, NVIDIA Corporation. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/io.h> 11 #include <linux/list.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/of.h> 15 #include <linux/slab.h> 16 17 #define CREATE_TRACE_POINTS 18 #include <trace/events/host1x.h> 19 #undef CREATE_TRACE_POINTS 20 21 #include "bus.h" 22 #include "channel.h" 23 #include "debug.h" 24 #include "dev.h" 25 #include "intr.h" 26 27 #include "hw/host1x01.h" 28 #include "hw/host1x02.h" 29 #include "hw/host1x04.h" 30 #include "hw/host1x05.h" 31 #include "hw/host1x06.h" 32 #include "hw/host1x07.h" 33 34 void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r) 35 { 36 writel(v, host1x->hv_regs + r); 37 } 38 39 u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r) 40 { 41 return readl(host1x->hv_regs + r); 42 } 43 44 void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r) 45 { 46 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 47 48 writel(v, sync_regs + r); 49 } 50 51 u32 host1x_sync_readl(struct host1x *host1x, u32 r) 52 { 53 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 54 55 return readl(sync_regs + r); 56 } 57 58 void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r) 59 { 60 writel(v, ch->regs + r); 61 } 62 63 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r) 64 { 65 return readl(ch->regs + r); 66 } 67 68 static const struct host1x_info host1x01_info = { 69 .nb_channels = 8, 70 .nb_pts = 32, 71 .nb_mlocks = 16, 72 .nb_bases = 8, 73 .init = host1x01_init, 74 .sync_offset = 0x3000, 75 .dma_mask = DMA_BIT_MASK(32), 76 .has_hypervisor = false, 77 .num_sid_entries = 0, 78 .sid_table = NULL, 79 }; 80 81 static const struct host1x_info host1x02_info = { 82 .nb_channels = 9, 83 .nb_pts = 32, 84 .nb_mlocks = 16, 85 .nb_bases = 12, 86 .init = host1x02_init, 87 .sync_offset = 0x3000, 88 .dma_mask = DMA_BIT_MASK(32), 89 .has_hypervisor = false, 90 .num_sid_entries = 0, 91 .sid_table = NULL, 92 }; 93 94 static const struct host1x_info host1x04_info = { 95 .nb_channels = 12, 96 .nb_pts = 192, 97 .nb_mlocks = 16, 98 .nb_bases = 64, 99 .init = host1x04_init, 100 .sync_offset = 0x2100, 101 .dma_mask = DMA_BIT_MASK(34), 102 .has_hypervisor = false, 103 .num_sid_entries = 0, 104 .sid_table = NULL, 105 }; 106 107 static const struct host1x_info host1x05_info = { 108 .nb_channels = 14, 109 .nb_pts = 192, 110 .nb_mlocks = 16, 111 .nb_bases = 64, 112 .init = host1x05_init, 113 .sync_offset = 0x2100, 114 .dma_mask = DMA_BIT_MASK(34), 115 .has_hypervisor = false, 116 .num_sid_entries = 0, 117 .sid_table = NULL, 118 }; 119 120 static const struct host1x_sid_entry tegra186_sid_table[] = { 121 { 122 /* VIC */ 123 .base = 0x1af0, 124 .offset = 0x30, 125 .limit = 0x34 126 }, 127 }; 128 129 static const struct host1x_info host1x06_info = { 130 .nb_channels = 63, 131 .nb_pts = 576, 132 .nb_mlocks = 24, 133 .nb_bases = 16, 134 .init = host1x06_init, 135 .sync_offset = 0x0, 136 .dma_mask = DMA_BIT_MASK(40), 137 .has_hypervisor = true, 138 .num_sid_entries = ARRAY_SIZE(tegra186_sid_table), 139 .sid_table = tegra186_sid_table, 140 }; 141 142 static const struct host1x_sid_entry tegra194_sid_table[] = { 143 { 144 /* VIC */ 145 .base = 0x1af0, 146 .offset = 0x30, 147 .limit = 0x34 148 }, 149 }; 150 151 static const struct host1x_info host1x07_info = { 152 .nb_channels = 63, 153 .nb_pts = 704, 154 .nb_mlocks = 32, 155 .nb_bases = 0, 156 .init = host1x07_init, 157 .sync_offset = 0x0, 158 .dma_mask = DMA_BIT_MASK(40), 159 .has_hypervisor = true, 160 .num_sid_entries = ARRAY_SIZE(tegra194_sid_table), 161 .sid_table = tegra194_sid_table, 162 }; 163 164 static const struct of_device_id host1x_of_match[] = { 165 { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, }, 166 { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, }, 167 { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, }, 168 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, }, 169 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, }, 170 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, }, 171 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, }, 172 { }, 173 }; 174 MODULE_DEVICE_TABLE(of, host1x_of_match); 175 176 static void host1x_setup_sid_table(struct host1x *host) 177 { 178 const struct host1x_info *info = host->info; 179 unsigned int i; 180 181 for (i = 0; i < info->num_sid_entries; i++) { 182 const struct host1x_sid_entry *entry = &info->sid_table[i]; 183 184 host1x_hypervisor_writel(host, entry->offset, entry->base); 185 host1x_hypervisor_writel(host, entry->limit, entry->base + 4); 186 } 187 } 188 189 static int host1x_probe(struct platform_device *pdev) 190 { 191 struct host1x *host; 192 struct resource *regs, *hv_regs = NULL; 193 int syncpt_irq; 194 int err; 195 196 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 197 if (!host) 198 return -ENOMEM; 199 200 host->info = of_device_get_match_data(&pdev->dev); 201 202 if (host->info->has_hypervisor) { 203 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm"); 204 if (!regs) { 205 dev_err(&pdev->dev, "failed to get vm registers\n"); 206 return -ENXIO; 207 } 208 209 hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, 210 "hypervisor"); 211 if (!hv_regs) { 212 dev_err(&pdev->dev, 213 "failed to get hypervisor registers\n"); 214 return -ENXIO; 215 } 216 } else { 217 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 218 if (!regs) { 219 dev_err(&pdev->dev, "failed to get registers\n"); 220 return -ENXIO; 221 } 222 } 223 224 syncpt_irq = platform_get_irq(pdev, 0); 225 if (syncpt_irq < 0) { 226 dev_err(&pdev->dev, "failed to get IRQ: %d\n", syncpt_irq); 227 return syncpt_irq; 228 } 229 230 mutex_init(&host->devices_lock); 231 INIT_LIST_HEAD(&host->devices); 232 INIT_LIST_HEAD(&host->list); 233 host->dev = &pdev->dev; 234 235 /* set common host1x device data */ 236 platform_set_drvdata(pdev, host); 237 238 host->regs = devm_ioremap_resource(&pdev->dev, regs); 239 if (IS_ERR(host->regs)) 240 return PTR_ERR(host->regs); 241 242 if (host->info->has_hypervisor) { 243 host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs); 244 if (IS_ERR(host->hv_regs)) 245 return PTR_ERR(host->hv_regs); 246 } 247 248 host->dev->dma_parms = &host->dma_parms; 249 dma_set_max_seg_size(host->dev, UINT_MAX); 250 251 dma_set_mask_and_coherent(host->dev, host->info->dma_mask); 252 253 if (host->info->init) { 254 err = host->info->init(host); 255 if (err) 256 return err; 257 } 258 259 host->clk = devm_clk_get(&pdev->dev, NULL); 260 if (IS_ERR(host->clk)) { 261 err = PTR_ERR(host->clk); 262 263 if (err != -EPROBE_DEFER) 264 dev_err(&pdev->dev, "failed to get clock: %d\n", err); 265 266 return err; 267 } 268 269 host->rst = devm_reset_control_get(&pdev->dev, "host1x"); 270 if (IS_ERR(host->rst)) { 271 err = PTR_ERR(host->rst); 272 dev_err(&pdev->dev, "failed to get reset: %d\n", err); 273 return err; 274 } 275 276 if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL)) 277 goto skip_iommu; 278 279 if (iommu_get_domain_for_dev(&pdev->dev)) 280 goto skip_iommu; 281 282 host->group = iommu_group_get(&pdev->dev); 283 if (host->group) { 284 struct iommu_domain_geometry *geometry; 285 u64 mask = dma_get_mask(host->dev); 286 dma_addr_t start, end; 287 unsigned long order; 288 289 err = iova_cache_get(); 290 if (err < 0) 291 goto put_group; 292 293 host->domain = iommu_domain_alloc(&platform_bus_type); 294 if (!host->domain) { 295 err = -ENOMEM; 296 goto put_cache; 297 } 298 299 err = iommu_attach_group(host->domain, host->group); 300 if (err) { 301 if (err == -ENODEV) { 302 iommu_domain_free(host->domain); 303 host->domain = NULL; 304 iova_cache_put(); 305 iommu_group_put(host->group); 306 host->group = NULL; 307 goto skip_iommu; 308 } 309 310 goto fail_free_domain; 311 } 312 313 geometry = &host->domain->geometry; 314 start = geometry->aperture_start & mask; 315 end = geometry->aperture_end & mask; 316 317 order = __ffs(host->domain->pgsize_bitmap); 318 init_iova_domain(&host->iova, 1UL << order, start >> order); 319 host->iova_end = end; 320 } 321 322 skip_iommu: 323 err = host1x_channel_list_init(&host->channel_list, 324 host->info->nb_channels); 325 if (err) { 326 dev_err(&pdev->dev, "failed to initialize channel list\n"); 327 goto fail_detach_device; 328 } 329 330 err = clk_prepare_enable(host->clk); 331 if (err < 0) { 332 dev_err(&pdev->dev, "failed to enable clock\n"); 333 goto fail_free_channels; 334 } 335 336 err = reset_control_deassert(host->rst); 337 if (err < 0) { 338 dev_err(&pdev->dev, "failed to deassert reset: %d\n", err); 339 goto fail_unprepare_disable; 340 } 341 342 err = host1x_syncpt_init(host); 343 if (err) { 344 dev_err(&pdev->dev, "failed to initialize syncpts\n"); 345 goto fail_reset_assert; 346 } 347 348 err = host1x_intr_init(host, syncpt_irq); 349 if (err) { 350 dev_err(&pdev->dev, "failed to initialize interrupts\n"); 351 goto fail_deinit_syncpt; 352 } 353 354 host1x_debug_init(host); 355 356 if (host->info->has_hypervisor) 357 host1x_setup_sid_table(host); 358 359 err = host1x_register(host); 360 if (err < 0) 361 goto fail_deinit_intr; 362 363 return 0; 364 365 fail_deinit_intr: 366 host1x_intr_deinit(host); 367 fail_deinit_syncpt: 368 host1x_syncpt_deinit(host); 369 fail_reset_assert: 370 reset_control_assert(host->rst); 371 fail_unprepare_disable: 372 clk_disable_unprepare(host->clk); 373 fail_free_channels: 374 host1x_channel_list_free(&host->channel_list); 375 fail_detach_device: 376 if (host->group && host->domain) { 377 put_iova_domain(&host->iova); 378 iommu_detach_group(host->domain, host->group); 379 } 380 fail_free_domain: 381 if (host->domain) 382 iommu_domain_free(host->domain); 383 put_cache: 384 if (host->group) 385 iova_cache_put(); 386 put_group: 387 iommu_group_put(host->group); 388 389 return err; 390 } 391 392 static int host1x_remove(struct platform_device *pdev) 393 { 394 struct host1x *host = platform_get_drvdata(pdev); 395 396 host1x_unregister(host); 397 host1x_debug_deinit(host); 398 host1x_intr_deinit(host); 399 host1x_syncpt_deinit(host); 400 reset_control_assert(host->rst); 401 clk_disable_unprepare(host->clk); 402 403 if (host->domain) { 404 put_iova_domain(&host->iova); 405 iommu_detach_group(host->domain, host->group); 406 iommu_domain_free(host->domain); 407 iova_cache_put(); 408 iommu_group_put(host->group); 409 } 410 411 return 0; 412 } 413 414 static struct platform_driver tegra_host1x_driver = { 415 .driver = { 416 .name = "tegra-host1x", 417 .of_match_table = host1x_of_match, 418 }, 419 .probe = host1x_probe, 420 .remove = host1x_remove, 421 }; 422 423 static struct platform_driver * const drivers[] = { 424 &tegra_host1x_driver, 425 &tegra_mipi_driver, 426 }; 427 428 static int __init tegra_host1x_init(void) 429 { 430 int err; 431 432 err = bus_register(&host1x_bus_type); 433 if (err < 0) 434 return err; 435 436 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 437 if (err < 0) 438 bus_unregister(&host1x_bus_type); 439 440 return err; 441 } 442 module_init(tegra_host1x_init); 443 444 static void __exit tegra_host1x_exit(void) 445 { 446 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 447 bus_unregister(&host1x_bus_type); 448 } 449 module_exit(tegra_host1x_exit); 450 451 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); 452 MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>"); 453 MODULE_DESCRIPTION("Host1x driver for Tegra products"); 454 MODULE_LICENSE("GPL"); 455