xref: /openbmc/linux/drivers/gpu/drm/xlnx/zynqmp_dpsub.h (revision 52c2cf1471b35eda9a29c8dfdee5c687909e126a)
1d76271d2SHyun Kwon /* SPDX-License-Identifier: GPL-2.0 */
2d76271d2SHyun Kwon /*
3d76271d2SHyun Kwon  * ZynqMP DPSUB Subsystem Driver
4d76271d2SHyun Kwon  *
5d76271d2SHyun Kwon  * Copyright (C) 2017 - 2020 Xilinx, Inc.
6d76271d2SHyun Kwon  *
7d76271d2SHyun Kwon  * Authors:
8d76271d2SHyun Kwon  * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9d76271d2SHyun Kwon  * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10d76271d2SHyun Kwon  */
11d76271d2SHyun Kwon 
12d76271d2SHyun Kwon #ifndef _ZYNQMP_DPSUB_H_
13d76271d2SHyun Kwon #define _ZYNQMP_DPSUB_H_
14d76271d2SHyun Kwon 
15d76271d2SHyun Kwon struct clk;
16d76271d2SHyun Kwon struct device;
17e8e35733SLaurent Pinchart struct drm_bridge;
18d76271d2SHyun Kwon struct zynqmp_disp;
19ee1229b3SLaurent Pinchart struct zynqmp_disp_layer;
20d76271d2SHyun Kwon struct zynqmp_dp;
21d189835fSLaurent Pinchart struct zynqmp_dpsub_drm;
22d76271d2SHyun Kwon 
2388beb8ccSLaurent Pinchart #define ZYNQMP_DPSUB_NUM_LAYERS				2
2488beb8ccSLaurent Pinchart 
25*52c2cf14SLaurent Pinchart enum zynqmp_dpsub_port {
26*52c2cf14SLaurent Pinchart 	ZYNQMP_DPSUB_PORT_LIVE_VIDEO,
27*52c2cf14SLaurent Pinchart 	ZYNQMP_DPSUB_PORT_LIVE_GFX,
28*52c2cf14SLaurent Pinchart 	ZYNQMP_DPSUB_PORT_LIVE_AUDIO,
29*52c2cf14SLaurent Pinchart 	ZYNQMP_DPSUB_PORT_OUT_VIDEO,
30*52c2cf14SLaurent Pinchart 	ZYNQMP_DPSUB_PORT_OUT_AUDIO,
31*52c2cf14SLaurent Pinchart 	ZYNQMP_DPSUB_PORT_OUT_DP,
32*52c2cf14SLaurent Pinchart 	ZYNQMP_DPSUB_NUM_PORTS,
33*52c2cf14SLaurent Pinchart };
34*52c2cf14SLaurent Pinchart 
35d76271d2SHyun Kwon enum zynqmp_dpsub_format {
36d76271d2SHyun Kwon 	ZYNQMP_DPSUB_FORMAT_RGB,
37d76271d2SHyun Kwon 	ZYNQMP_DPSUB_FORMAT_YCRCB444,
38d76271d2SHyun Kwon 	ZYNQMP_DPSUB_FORMAT_YCRCB422,
39d76271d2SHyun Kwon 	ZYNQMP_DPSUB_FORMAT_YONLY,
40d76271d2SHyun Kwon };
41d76271d2SHyun Kwon 
42d76271d2SHyun Kwon /**
43d76271d2SHyun Kwon  * struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem
44d76271d2SHyun Kwon  * @dev: The physical device
45d76271d2SHyun Kwon  * @apb_clk: The APB clock
461682ade6SLaurent Pinchart  * @vid_clk: Video clock
471682ade6SLaurent Pinchart  * @vid_clk_from_ps: True of the video clock comes from PS, false from PL
48c979296eSLaurent Pinchart  * @aud_clk: Audio clock
49c979296eSLaurent Pinchart  * @aud_clk_from_ps: True of the audio clock comes from PS, false from PL
50*52c2cf14SLaurent Pinchart  * @connected_ports: Bitmask of connected ports in the device tree
51d189835fSLaurent Pinchart  * @drm: The DRM/KMS device data
52e8e35733SLaurent Pinchart  * @bridge: The DP encoder bridge
53d76271d2SHyun Kwon  * @disp: The display controller
54d76271d2SHyun Kwon  * @dp: The DisplayPort controller
55d76271d2SHyun Kwon  * @dma_align: DMA alignment constraint (must be a power of 2)
56d76271d2SHyun Kwon  */
57d76271d2SHyun Kwon struct zynqmp_dpsub {
58d76271d2SHyun Kwon 	struct device *dev;
59d76271d2SHyun Kwon 
60d76271d2SHyun Kwon 	struct clk *apb_clk;
611682ade6SLaurent Pinchart 	struct clk *vid_clk;
621682ade6SLaurent Pinchart 	bool vid_clk_from_ps;
63c979296eSLaurent Pinchart 	struct clk *aud_clk;
64c979296eSLaurent Pinchart 	bool aud_clk_from_ps;
65d76271d2SHyun Kwon 
66*52c2cf14SLaurent Pinchart 	unsigned int connected_ports;
67*52c2cf14SLaurent Pinchart 
68d189835fSLaurent Pinchart 	struct zynqmp_dpsub_drm *drm;
69e8e35733SLaurent Pinchart 	struct drm_bridge *bridge;
70e8e35733SLaurent Pinchart 
71d76271d2SHyun Kwon 	struct zynqmp_disp *disp;
72ee1229b3SLaurent Pinchart 	struct zynqmp_disp_layer *layers[ZYNQMP_DPSUB_NUM_LAYERS];
73d76271d2SHyun Kwon 	struct zynqmp_dp *dp;
74d76271d2SHyun Kwon 
75d76271d2SHyun Kwon 	unsigned int dma_align;
76d76271d2SHyun Kwon };
77d76271d2SHyun Kwon 
78c979296eSLaurent Pinchart bool zynqmp_dpsub_audio_enabled(struct zynqmp_dpsub *dpsub);
79c979296eSLaurent Pinchart unsigned int zynqmp_dpsub_get_audio_clk_rate(struct zynqmp_dpsub *dpsub);
80c979296eSLaurent Pinchart 
81d189835fSLaurent Pinchart void zynqmp_dpsub_release(struct zynqmp_dpsub *dpsub);
82d189835fSLaurent Pinchart 
83d76271d2SHyun Kwon #endif /* _ZYNQMP_DPSUB_H_ */
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