1d76271d2SHyun Kwon /* SPDX-License-Identifier: GPL-2.0 */ 2d76271d2SHyun Kwon /* 3d76271d2SHyun Kwon * ZynqMP DPSUB Subsystem Driver 4d76271d2SHyun Kwon * 5d76271d2SHyun Kwon * Copyright (C) 2017 - 2020 Xilinx, Inc. 6d76271d2SHyun Kwon * 7d76271d2SHyun Kwon * Authors: 8d76271d2SHyun Kwon * - Hyun Woo Kwon <hyun.kwon@xilinx.com> 9d76271d2SHyun Kwon * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10d76271d2SHyun Kwon */ 11d76271d2SHyun Kwon 12d76271d2SHyun Kwon #ifndef _ZYNQMP_DPSUB_H_ 13d76271d2SHyun Kwon #define _ZYNQMP_DPSUB_H_ 14d76271d2SHyun Kwon 15d76271d2SHyun Kwon struct clk; 16d76271d2SHyun Kwon struct device; 17e8e35733SLaurent Pinchart struct drm_bridge; 18d76271d2SHyun Kwon struct zynqmp_disp; 19ee1229b3SLaurent Pinchart struct zynqmp_disp_layer; 20d76271d2SHyun Kwon struct zynqmp_dp; 21d189835fSLaurent Pinchart struct zynqmp_dpsub_drm; 22d76271d2SHyun Kwon 2388beb8ccSLaurent Pinchart #define ZYNQMP_DPSUB_NUM_LAYERS 2 2488beb8ccSLaurent Pinchart 2552c2cf14SLaurent Pinchart enum zynqmp_dpsub_port { 2652c2cf14SLaurent Pinchart ZYNQMP_DPSUB_PORT_LIVE_VIDEO, 2752c2cf14SLaurent Pinchart ZYNQMP_DPSUB_PORT_LIVE_GFX, 2852c2cf14SLaurent Pinchart ZYNQMP_DPSUB_PORT_LIVE_AUDIO, 2952c2cf14SLaurent Pinchart ZYNQMP_DPSUB_PORT_OUT_VIDEO, 3052c2cf14SLaurent Pinchart ZYNQMP_DPSUB_PORT_OUT_AUDIO, 3152c2cf14SLaurent Pinchart ZYNQMP_DPSUB_PORT_OUT_DP, 3252c2cf14SLaurent Pinchart ZYNQMP_DPSUB_NUM_PORTS, 3352c2cf14SLaurent Pinchart }; 3452c2cf14SLaurent Pinchart 35d76271d2SHyun Kwon enum zynqmp_dpsub_format { 36d76271d2SHyun Kwon ZYNQMP_DPSUB_FORMAT_RGB, 37d76271d2SHyun Kwon ZYNQMP_DPSUB_FORMAT_YCRCB444, 38d76271d2SHyun Kwon ZYNQMP_DPSUB_FORMAT_YCRCB422, 39d76271d2SHyun Kwon ZYNQMP_DPSUB_FORMAT_YONLY, 40d76271d2SHyun Kwon }; 41d76271d2SHyun Kwon 42d76271d2SHyun Kwon /** 43d76271d2SHyun Kwon * struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem 44d76271d2SHyun Kwon * @dev: The physical device 45d76271d2SHyun Kwon * @apb_clk: The APB clock 461682ade6SLaurent Pinchart * @vid_clk: Video clock 471682ade6SLaurent Pinchart * @vid_clk_from_ps: True of the video clock comes from PS, false from PL 48c979296eSLaurent Pinchart * @aud_clk: Audio clock 49c979296eSLaurent Pinchart * @aud_clk_from_ps: True of the audio clock comes from PS, false from PL 5052c2cf14SLaurent Pinchart * @connected_ports: Bitmask of connected ports in the device tree 51*51ae3bd4SLaurent Pinchart * @dma_enabled: True if the DMA interface is enabled, false if the DPSUB is 52*51ae3bd4SLaurent Pinchart * driven by the live input 53d189835fSLaurent Pinchart * @drm: The DRM/KMS device data 54e8e35733SLaurent Pinchart * @bridge: The DP encoder bridge 55d76271d2SHyun Kwon * @disp: The display controller 56d76271d2SHyun Kwon * @dp: The DisplayPort controller 57d76271d2SHyun Kwon * @dma_align: DMA alignment constraint (must be a power of 2) 58d76271d2SHyun Kwon */ 59d76271d2SHyun Kwon struct zynqmp_dpsub { 60d76271d2SHyun Kwon struct device *dev; 61d76271d2SHyun Kwon 62d76271d2SHyun Kwon struct clk *apb_clk; 631682ade6SLaurent Pinchart struct clk *vid_clk; 641682ade6SLaurent Pinchart bool vid_clk_from_ps; 65c979296eSLaurent Pinchart struct clk *aud_clk; 66c979296eSLaurent Pinchart bool aud_clk_from_ps; 67d76271d2SHyun Kwon 6852c2cf14SLaurent Pinchart unsigned int connected_ports; 69*51ae3bd4SLaurent Pinchart bool dma_enabled; 7052c2cf14SLaurent Pinchart 71d189835fSLaurent Pinchart struct zynqmp_dpsub_drm *drm; 72e8e35733SLaurent Pinchart struct drm_bridge *bridge; 73e8e35733SLaurent Pinchart 74d76271d2SHyun Kwon struct zynqmp_disp *disp; 75ee1229b3SLaurent Pinchart struct zynqmp_disp_layer *layers[ZYNQMP_DPSUB_NUM_LAYERS]; 76d76271d2SHyun Kwon struct zynqmp_dp *dp; 77d76271d2SHyun Kwon 78d76271d2SHyun Kwon unsigned int dma_align; 79d76271d2SHyun Kwon }; 80d76271d2SHyun Kwon 81c979296eSLaurent Pinchart bool zynqmp_dpsub_audio_enabled(struct zynqmp_dpsub *dpsub); 82c979296eSLaurent Pinchart unsigned int zynqmp_dpsub_get_audio_clk_rate(struct zynqmp_dpsub *dpsub); 83c979296eSLaurent Pinchart 84d189835fSLaurent Pinchart void zynqmp_dpsub_release(struct zynqmp_dpsub *dpsub); 85d189835fSLaurent Pinchart 86d76271d2SHyun Kwon #endif /* _ZYNQMP_DPSUB_H_ */ 87