1d76271d2SHyun Kwon /* SPDX-License-Identifier: GPL-2.0 */ 2d76271d2SHyun Kwon /* 3d76271d2SHyun Kwon * ZynqMP Display Driver 4d76271d2SHyun Kwon * 5d76271d2SHyun Kwon * Copyright (C) 2017 - 2020 Xilinx, Inc. 6d76271d2SHyun Kwon * 7d76271d2SHyun Kwon * Authors: 8d76271d2SHyun Kwon * - Hyun Woo Kwon <hyun.kwon@xilinx.com> 9d76271d2SHyun Kwon * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10d76271d2SHyun Kwon */ 11d76271d2SHyun Kwon 12d76271d2SHyun Kwon #ifndef _ZYNQMP_DISP_H_ 13d76271d2SHyun Kwon #define _ZYNQMP_DISP_H_ 14d76271d2SHyun Kwon 15d76271d2SHyun Kwon #include <linux/types.h> 16d76271d2SHyun Kwon 17d76271d2SHyun Kwon /* 18d76271d2SHyun Kwon * 3840x2160 is advertised as the maximum resolution, but almost any 19d76271d2SHyun Kwon * resolutions under a 300Mhz pixel rate would work. Pick 4096x4096. 20d76271d2SHyun Kwon */ 21d76271d2SHyun Kwon #define ZYNQMP_DISP_MAX_WIDTH 4096 22d76271d2SHyun Kwon #define ZYNQMP_DISP_MAX_HEIGHT 4096 23d76271d2SHyun Kwon 24d76271d2SHyun Kwon /* The DPDMA is limited to 44 bit addressing. */ 25d76271d2SHyun Kwon #define ZYNQMP_DISP_MAX_DMA_BIT 44 26d76271d2SHyun Kwon 27d76271d2SHyun Kwon struct device; 28ee1229b3SLaurent Pinchart struct drm_format_info; 29ee1229b3SLaurent Pinchart struct drm_plane_state; 30d76271d2SHyun Kwon struct platform_device; 31d76271d2SHyun Kwon struct zynqmp_disp; 32ee1229b3SLaurent Pinchart struct zynqmp_disp_layer; 33d76271d2SHyun Kwon struct zynqmp_dpsub; 34d76271d2SHyun Kwon 3583a956d3SLaurent Pinchart /** 3683a956d3SLaurent Pinchart * enum zynqmp_dpsub_layer_id - Layer identifier 3783a956d3SLaurent Pinchart * @ZYNQMP_DPSUB_LAYER_VID: Video layer 3883a956d3SLaurent Pinchart * @ZYNQMP_DPSUB_LAYER_GFX: Graphics layer 3983a956d3SLaurent Pinchart */ 4083a956d3SLaurent Pinchart enum zynqmp_dpsub_layer_id { 4183a956d3SLaurent Pinchart ZYNQMP_DPSUB_LAYER_VID, 4283a956d3SLaurent Pinchart ZYNQMP_DPSUB_LAYER_GFX, 4383a956d3SLaurent Pinchart }; 4483a956d3SLaurent Pinchart 45*3662bbfcSLaurent Pinchart /** 46*3662bbfcSLaurent Pinchart * enum zynqmp_dpsub_layer_mode - Layer mode 47*3662bbfcSLaurent Pinchart * @ZYNQMP_DPSUB_LAYER_NONLIVE: non-live (memory) mode 48*3662bbfcSLaurent Pinchart * @ZYNQMP_DPSUB_LAYER_LIVE: live (stream) mode 49*3662bbfcSLaurent Pinchart */ 50*3662bbfcSLaurent Pinchart enum zynqmp_dpsub_layer_mode { 51*3662bbfcSLaurent Pinchart ZYNQMP_DPSUB_LAYER_NONLIVE, 52*3662bbfcSLaurent Pinchart ZYNQMP_DPSUB_LAYER_LIVE, 53*3662bbfcSLaurent Pinchart }; 54*3662bbfcSLaurent Pinchart 5583a956d3SLaurent Pinchart void zynqmp_disp_enable(struct zynqmp_disp *disp); 5683a956d3SLaurent Pinchart void zynqmp_disp_disable(struct zynqmp_disp *disp); 5783a956d3SLaurent Pinchart int zynqmp_disp_setup_clock(struct zynqmp_disp *disp, 5883a956d3SLaurent Pinchart unsigned long mode_clock); 5983a956d3SLaurent Pinchart 60ee1229b3SLaurent Pinchart void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp *disp, 61ee1229b3SLaurent Pinchart bool enable, u32 alpha); 62d76271d2SHyun Kwon 63ee1229b3SLaurent Pinchart u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer, 64ee1229b3SLaurent Pinchart unsigned int *num_formats); 65*3662bbfcSLaurent Pinchart void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer, 66*3662bbfcSLaurent Pinchart enum zynqmp_dpsub_layer_mode mode); 67ee1229b3SLaurent Pinchart void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer); 68ee1229b3SLaurent Pinchart void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, 69ee1229b3SLaurent Pinchart const struct drm_format_info *info); 70ee1229b3SLaurent Pinchart int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer, 71ee1229b3SLaurent Pinchart struct drm_plane_state *state); 72ee1229b3SLaurent Pinchart 736ca91bb4SLaurent Pinchart int zynqmp_disp_probe(struct zynqmp_dpsub *dpsub); 74d76271d2SHyun Kwon void zynqmp_disp_remove(struct zynqmp_dpsub *dpsub); 75d76271d2SHyun Kwon 76d76271d2SHyun Kwon #endif /* _ZYNQMP_DISP_H_ */ 77