xref: /openbmc/linux/drivers/gpu/drm/v3d/v3d_drv.c (revision eee9a2e0ad7c4c1fe5fa286dddf822116370f0c7)
157692c94SEric Anholt // SPDX-License-Identifier: GPL-2.0+
257692c94SEric Anholt /* Copyright (C) 2014-2018 Broadcom */
357692c94SEric Anholt 
457692c94SEric Anholt /**
557692c94SEric Anholt  * DOC: Broadcom V3D Graphics Driver
657692c94SEric Anholt  *
757692c94SEric Anholt  * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs.
857692c94SEric Anholt  * For V3D 2.x support, see the VC4 driver.
957692c94SEric Anholt  *
10d223f98fSEric Anholt  * The V3D GPU includes a tiled render (composed of a bin and render
11d223f98fSEric Anholt  * pipelines), the TFU (texture formatting unit), and the CSD (compute
12d223f98fSEric Anholt  * shader dispatch).
1357692c94SEric Anholt  */
1457692c94SEric Anholt 
1557692c94SEric Anholt #include <linux/clk.h>
1657692c94SEric Anholt #include <linux/device.h>
17220989e7SSam Ravnborg #include <linux/dma-mapping.h>
1857692c94SEric Anholt #include <linux/io.h>
1957692c94SEric Anholt #include <linux/module.h>
2057692c94SEric Anholt #include <linux/of_platform.h>
2157692c94SEric Anholt #include <linux/platform_device.h>
2257692c94SEric Anholt #include <linux/pm_runtime.h>
23eea9b97bSEric Anholt #include <linux/reset.h>
24220989e7SSam Ravnborg 
25220989e7SSam Ravnborg #include <drm/drm_drv.h>
2657692c94SEric Anholt #include <drm/drm_fb_cma_helper.h>
2757692c94SEric Anholt #include <drm/drm_fb_helper.h>
28220989e7SSam Ravnborg #include <uapi/drm/v3d_drm.h>
2957692c94SEric Anholt 
3057692c94SEric Anholt #include "v3d_drv.h"
3157692c94SEric Anholt #include "v3d_regs.h"
3257692c94SEric Anholt 
3357692c94SEric Anholt #define DRIVER_NAME "v3d"
3457692c94SEric Anholt #define DRIVER_DESC "Broadcom V3D graphics"
3557692c94SEric Anholt #define DRIVER_DATE "20180419"
3657692c94SEric Anholt #define DRIVER_MAJOR 1
3757692c94SEric Anholt #define DRIVER_MINOR 0
3857692c94SEric Anholt #define DRIVER_PATCHLEVEL 0
3957692c94SEric Anholt 
4057692c94SEric Anholt #ifdef CONFIG_PM
4157692c94SEric Anholt static int v3d_runtime_suspend(struct device *dev)
4257692c94SEric Anholt {
4357692c94SEric Anholt 	struct drm_device *drm = dev_get_drvdata(dev);
4457692c94SEric Anholt 	struct v3d_dev *v3d = to_v3d_dev(drm);
4557692c94SEric Anholt 
4657692c94SEric Anholt 	v3d_irq_disable(v3d);
4757692c94SEric Anholt 
4857692c94SEric Anholt 	clk_disable_unprepare(v3d->clk);
4957692c94SEric Anholt 
5057692c94SEric Anholt 	return 0;
5157692c94SEric Anholt }
5257692c94SEric Anholt 
5357692c94SEric Anholt static int v3d_runtime_resume(struct device *dev)
5457692c94SEric Anholt {
5557692c94SEric Anholt 	struct drm_device *drm = dev_get_drvdata(dev);
5657692c94SEric Anholt 	struct v3d_dev *v3d = to_v3d_dev(drm);
5757692c94SEric Anholt 	int ret;
5857692c94SEric Anholt 
5957692c94SEric Anholt 	ret = clk_prepare_enable(v3d->clk);
6057692c94SEric Anholt 	if (ret != 0)
6157692c94SEric Anholt 		return ret;
6257692c94SEric Anholt 
6357692c94SEric Anholt 	/* XXX: VPM base */
6457692c94SEric Anholt 
6557692c94SEric Anholt 	v3d_mmu_set_page_table(v3d);
6657692c94SEric Anholt 	v3d_irq_enable(v3d);
6757692c94SEric Anholt 
6857692c94SEric Anholt 	return 0;
6957692c94SEric Anholt }
7057692c94SEric Anholt #endif
7157692c94SEric Anholt 
7257692c94SEric Anholt static const struct dev_pm_ops v3d_v3d_pm_ops = {
7357692c94SEric Anholt 	SET_RUNTIME_PM_OPS(v3d_runtime_suspend, v3d_runtime_resume, NULL)
7457692c94SEric Anholt };
7557692c94SEric Anholt 
7657692c94SEric Anholt static int v3d_get_param_ioctl(struct drm_device *dev, void *data,
7757692c94SEric Anholt 			       struct drm_file *file_priv)
7857692c94SEric Anholt {
7957692c94SEric Anholt 	struct v3d_dev *v3d = to_v3d_dev(dev);
8057692c94SEric Anholt 	struct drm_v3d_get_param *args = data;
8157692c94SEric Anholt 	int ret;
8257692c94SEric Anholt 	static const u32 reg_map[] = {
8357692c94SEric Anholt 		[DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG,
8457692c94SEric Anholt 		[DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1,
8557692c94SEric Anholt 		[DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2,
8657692c94SEric Anholt 		[DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3,
8757692c94SEric Anholt 		[DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0,
8857692c94SEric Anholt 		[DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1,
8957692c94SEric Anholt 		[DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2,
9057692c94SEric Anholt 	};
9157692c94SEric Anholt 
9257692c94SEric Anholt 	if (args->pad != 0)
9357692c94SEric Anholt 		return -EINVAL;
9457692c94SEric Anholt 
9557692c94SEric Anholt 	/* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need
9657692c94SEric Anholt 	 * to explicitly allow it in the "the register in our
9757692c94SEric Anholt 	 * parameter map" check.
9857692c94SEric Anholt 	 */
9957692c94SEric Anholt 	if (args->param < ARRAY_SIZE(reg_map) &&
10057692c94SEric Anholt 	    (reg_map[args->param] ||
10157692c94SEric Anholt 	     args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) {
10257692c94SEric Anholt 		u32 offset = reg_map[args->param];
10357692c94SEric Anholt 
10457692c94SEric Anholt 		if (args->value != 0)
10557692c94SEric Anholt 			return -EINVAL;
10657692c94SEric Anholt 
10757692c94SEric Anholt 		ret = pm_runtime_get_sync(v3d->dev);
1083c77ff8fSKangjie Lu 		if (ret < 0)
1093c77ff8fSKangjie Lu 			return ret;
11057692c94SEric Anholt 		if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 &&
11157692c94SEric Anholt 		    args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) {
11257692c94SEric Anholt 			args->value = V3D_CORE_READ(0, offset);
11357692c94SEric Anholt 		} else {
11457692c94SEric Anholt 			args->value = V3D_READ(offset);
11557692c94SEric Anholt 		}
11657692c94SEric Anholt 		pm_runtime_mark_last_busy(v3d->dev);
11757692c94SEric Anholt 		pm_runtime_put_autosuspend(v3d->dev);
11857692c94SEric Anholt 		return 0;
11957692c94SEric Anholt 	}
12057692c94SEric Anholt 
12157692c94SEric Anholt 
1221584f16cSEric Anholt 	switch (args->param) {
1231584f16cSEric Anholt 	case DRM_V3D_PARAM_SUPPORTS_TFU:
1241584f16cSEric Anholt 		args->value = 1;
1251584f16cSEric Anholt 		return 0;
126d223f98fSEric Anholt 	case DRM_V3D_PARAM_SUPPORTS_CSD:
127d223f98fSEric Anholt 		args->value = v3d_has_csd(v3d);
128d223f98fSEric Anholt 		return 0;
129455d56ceSIago Toral Quiroga 	case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH:
130455d56ceSIago Toral Quiroga 		args->value = 1;
131455d56ceSIago Toral Quiroga 		return 0;
1321584f16cSEric Anholt 	default:
13357692c94SEric Anholt 		DRM_DEBUG("Unknown parameter %d\n", args->param);
13457692c94SEric Anholt 		return -EINVAL;
13557692c94SEric Anholt 	}
1361584f16cSEric Anholt }
13757692c94SEric Anholt 
13857692c94SEric Anholt static int
13957692c94SEric Anholt v3d_open(struct drm_device *dev, struct drm_file *file)
14057692c94SEric Anholt {
14157692c94SEric Anholt 	struct v3d_dev *v3d = to_v3d_dev(dev);
14257692c94SEric Anholt 	struct v3d_file_priv *v3d_priv;
143aa16b6c6SNayan Deshmukh 	struct drm_sched_rq *rq;
14457692c94SEric Anholt 	int i;
14557692c94SEric Anholt 
14657692c94SEric Anholt 	v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL);
14757692c94SEric Anholt 	if (!v3d_priv)
14857692c94SEric Anholt 		return -ENOMEM;
14957692c94SEric Anholt 
15057692c94SEric Anholt 	v3d_priv->v3d = v3d;
15157692c94SEric Anholt 
15257692c94SEric Anholt 	for (i = 0; i < V3D_MAX_QUEUES; i++) {
153aa16b6c6SNayan Deshmukh 		rq = &v3d->queue[i].sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
154aa16b6c6SNayan Deshmukh 		drm_sched_entity_init(&v3d_priv->sched_entity[i], &rq, 1, NULL);
15557692c94SEric Anholt 	}
15657692c94SEric Anholt 
15757692c94SEric Anholt 	file->driver_priv = v3d_priv;
15857692c94SEric Anholt 
15957692c94SEric Anholt 	return 0;
16057692c94SEric Anholt }
16157692c94SEric Anholt 
16257692c94SEric Anholt static void
16357692c94SEric Anholt v3d_postclose(struct drm_device *dev, struct drm_file *file)
16457692c94SEric Anholt {
16557692c94SEric Anholt 	struct v3d_file_priv *v3d_priv = file->driver_priv;
16657692c94SEric Anholt 	enum v3d_queue q;
16757692c94SEric Anholt 
16857692c94SEric Anholt 	for (q = 0; q < V3D_MAX_QUEUES; q++) {
169cdc50176SNayan Deshmukh 		drm_sched_entity_destroy(&v3d_priv->sched_entity[q]);
17057692c94SEric Anholt 	}
17157692c94SEric Anholt 
17257692c94SEric Anholt 	kfree(v3d_priv);
17357692c94SEric Anholt }
17457692c94SEric Anholt 
175*eee9a2e0SGerd Hoffmann DEFINE_DRM_GEM_FOPS(v3d_drm_fops);
17657692c94SEric Anholt 
17757692c94SEric Anholt /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP
17857692c94SEric Anholt  * protection between clients.  Note that render nodes would be be
17957692c94SEric Anholt  * able to submit CLs that could access BOs from clients authenticated
1801584f16cSEric Anholt  * with the master node.  The TFU doesn't use the GMP, so it would
1811584f16cSEric Anholt  * need to stay DRM_AUTH until we do buffer size/offset validation.
18257692c94SEric Anholt  */
18357692c94SEric Anholt static const struct drm_ioctl_desc v3d_drm_ioctls[] = {
18457692c94SEric Anholt 	DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
18557692c94SEric Anholt 	DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW),
18657692c94SEric Anholt 	DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW),
18757692c94SEric Anholt 	DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW),
18857692c94SEric Anholt 	DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW),
18957692c94SEric Anholt 	DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW),
1901584f16cSEric Anholt 	DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
191d223f98fSEric Anholt 	DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
19257692c94SEric Anholt };
19357692c94SEric Anholt 
19457692c94SEric Anholt static struct drm_driver v3d_drm_driver = {
19557692c94SEric Anholt 	.driver_features = (DRIVER_GEM |
19657692c94SEric Anholt 			    DRIVER_RENDER |
19757692c94SEric Anholt 			    DRIVER_SYNCOBJ),
19857692c94SEric Anholt 
19957692c94SEric Anholt 	.open = v3d_open,
20057692c94SEric Anholt 	.postclose = v3d_postclose,
20157692c94SEric Anholt 
20257692c94SEric Anholt #if defined(CONFIG_DEBUG_FS)
20357692c94SEric Anholt 	.debugfs_init = v3d_debugfs_init,
20457692c94SEric Anholt #endif
20557692c94SEric Anholt 
20640609d48SEric Anholt 	.gem_create_object = v3d_create_object,
20757692c94SEric Anholt 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
20857692c94SEric Anholt 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
20957692c94SEric Anholt 	.gem_prime_import_sg_table = v3d_prime_import_sg_table,
21040609d48SEric Anholt 	.gem_prime_mmap = drm_gem_prime_mmap,
21157692c94SEric Anholt 
21257692c94SEric Anholt 	.ioctls = v3d_drm_ioctls,
21357692c94SEric Anholt 	.num_ioctls = ARRAY_SIZE(v3d_drm_ioctls),
21457692c94SEric Anholt 	.fops = &v3d_drm_fops,
21557692c94SEric Anholt 
21657692c94SEric Anholt 	.name = DRIVER_NAME,
21757692c94SEric Anholt 	.desc = DRIVER_DESC,
21857692c94SEric Anholt 	.date = DRIVER_DATE,
21957692c94SEric Anholt 	.major = DRIVER_MAJOR,
22057692c94SEric Anholt 	.minor = DRIVER_MINOR,
22157692c94SEric Anholt 	.patchlevel = DRIVER_PATCHLEVEL,
22257692c94SEric Anholt };
22357692c94SEric Anholt 
22457692c94SEric Anholt static const struct of_device_id v3d_of_match[] = {
22557692c94SEric Anholt 	{ .compatible = "brcm,7268-v3d" },
22657692c94SEric Anholt 	{ .compatible = "brcm,7278-v3d" },
22757692c94SEric Anholt 	{},
22857692c94SEric Anholt };
22957692c94SEric Anholt MODULE_DEVICE_TABLE(of, v3d_of_match);
23057692c94SEric Anholt 
23157692c94SEric Anholt static int
23257692c94SEric Anholt map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)
23357692c94SEric Anholt {
23457692c94SEric Anholt 	struct resource *res =
23557692c94SEric Anholt 		platform_get_resource_byname(v3d->pdev, IORESOURCE_MEM, name);
23657692c94SEric Anholt 
23757692c94SEric Anholt 	*regs = devm_ioremap_resource(v3d->dev, res);
23857692c94SEric Anholt 	return PTR_ERR_OR_ZERO(*regs);
23957692c94SEric Anholt }
24057692c94SEric Anholt 
24157692c94SEric Anholt static int v3d_platform_drm_probe(struct platform_device *pdev)
24257692c94SEric Anholt {
24357692c94SEric Anholt 	struct device *dev = &pdev->dev;
24457692c94SEric Anholt 	struct drm_device *drm;
24557692c94SEric Anholt 	struct v3d_dev *v3d;
24657692c94SEric Anholt 	int ret;
247091d6283SEric Anholt 	u32 mmu_debug;
24857692c94SEric Anholt 	u32 ident1;
24957692c94SEric Anholt 
25057692c94SEric Anholt 
25157692c94SEric Anholt 	v3d = kzalloc(sizeof(*v3d), GFP_KERNEL);
25257692c94SEric Anholt 	if (!v3d)
25357692c94SEric Anholt 		return -ENOMEM;
25457692c94SEric Anholt 	v3d->dev = dev;
25557692c94SEric Anholt 	v3d->pdev = pdev;
25657692c94SEric Anholt 	drm = &v3d->drm;
25757692c94SEric Anholt 
25857692c94SEric Anholt 	ret = map_regs(v3d, &v3d->hub_regs, "hub");
25957692c94SEric Anholt 	if (ret)
26057692c94SEric Anholt 		goto dev_free;
26157692c94SEric Anholt 
26257692c94SEric Anholt 	ret = map_regs(v3d, &v3d->core_regs[0], "core0");
26357692c94SEric Anholt 	if (ret)
26457692c94SEric Anholt 		goto dev_free;
26557692c94SEric Anholt 
266091d6283SEric Anholt 	mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
267091d6283SEric Anholt 	dev->coherent_dma_mask =
268091d6283SEric Anholt 		DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
26938c2c791SEric Anholt 	v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);
270091d6283SEric Anholt 
27157692c94SEric Anholt 	ident1 = V3D_READ(V3D_HUB_IDENT1);
27257692c94SEric Anholt 	v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
27357692c94SEric Anholt 		    V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
27457692c94SEric Anholt 	v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
27557692c94SEric Anholt 	WARN_ON(v3d->cores > 1); /* multicore not yet implemented */
27657692c94SEric Anholt 
277eea9b97bSEric Anholt 	v3d->reset = devm_reset_control_get_exclusive(dev, NULL);
278eea9b97bSEric Anholt 	if (IS_ERR(v3d->reset)) {
279eea9b97bSEric Anholt 		ret = PTR_ERR(v3d->reset);
280eea9b97bSEric Anholt 
281eea9b97bSEric Anholt 		if (ret == -EPROBE_DEFER)
282eea9b97bSEric Anholt 			goto dev_free;
283eea9b97bSEric Anholt 
284eea9b97bSEric Anholt 		v3d->reset = NULL;
285eea9b97bSEric Anholt 		ret = map_regs(v3d, &v3d->bridge_regs, "bridge");
286eea9b97bSEric Anholt 		if (ret) {
287eea9b97bSEric Anholt 			dev_err(dev,
288eea9b97bSEric Anholt 				"Failed to get reset control or bridge regs\n");
289eea9b97bSEric Anholt 			goto dev_free;
290eea9b97bSEric Anholt 		}
291eea9b97bSEric Anholt 	}
292eea9b97bSEric Anholt 
29357692c94SEric Anholt 	if (v3d->ver < 41) {
29457692c94SEric Anholt 		ret = map_regs(v3d, &v3d->gca_regs, "gca");
29557692c94SEric Anholt 		if (ret)
29657692c94SEric Anholt 			goto dev_free;
29757692c94SEric Anholt 	}
29857692c94SEric Anholt 
29957692c94SEric Anholt 	v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr,
30057692c94SEric Anholt 					GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
30157692c94SEric Anholt 	if (!v3d->mmu_scratch) {
30257692c94SEric Anholt 		dev_err(dev, "Failed to allocate MMU scratch page\n");
30357692c94SEric Anholt 		ret = -ENOMEM;
30457692c94SEric Anholt 		goto dev_free;
30557692c94SEric Anholt 	}
30657692c94SEric Anholt 
30757692c94SEric Anholt 	pm_runtime_use_autosuspend(dev);
30857692c94SEric Anholt 	pm_runtime_set_autosuspend_delay(dev, 50);
30957692c94SEric Anholt 	pm_runtime_enable(dev);
31057692c94SEric Anholt 
31157692c94SEric Anholt 	ret = drm_dev_init(&v3d->drm, &v3d_drm_driver, dev);
31257692c94SEric Anholt 	if (ret)
31357692c94SEric Anholt 		goto dma_free;
31457692c94SEric Anholt 
31557692c94SEric Anholt 	platform_set_drvdata(pdev, drm);
31657692c94SEric Anholt 	drm->dev_private = v3d;
31757692c94SEric Anholt 
31857692c94SEric Anholt 	ret = v3d_gem_init(drm);
31957692c94SEric Anholt 	if (ret)
32057692c94SEric Anholt 		goto dev_destroy;
32157692c94SEric Anholt 
322fc227715SEric Anholt 	ret = v3d_irq_init(v3d);
32357692c94SEric Anholt 	if (ret)
32457692c94SEric Anholt 		goto gem_destroy;
32557692c94SEric Anholt 
326fc227715SEric Anholt 	ret = drm_dev_register(drm, 0);
327fc227715SEric Anholt 	if (ret)
328fc227715SEric Anholt 		goto irq_disable;
329fc227715SEric Anholt 
33057692c94SEric Anholt 	return 0;
33157692c94SEric Anholt 
332fc227715SEric Anholt irq_disable:
333fc227715SEric Anholt 	v3d_irq_disable(v3d);
33457692c94SEric Anholt gem_destroy:
33557692c94SEric Anholt 	v3d_gem_destroy(drm);
33657692c94SEric Anholt dev_destroy:
33757692c94SEric Anholt 	drm_dev_put(drm);
33857692c94SEric Anholt dma_free:
33957692c94SEric Anholt 	dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
34057692c94SEric Anholt dev_free:
34157692c94SEric Anholt 	kfree(v3d);
34257692c94SEric Anholt 	return ret;
34357692c94SEric Anholt }
34457692c94SEric Anholt 
34557692c94SEric Anholt static int v3d_platform_drm_remove(struct platform_device *pdev)
34657692c94SEric Anholt {
34757692c94SEric Anholt 	struct drm_device *drm = platform_get_drvdata(pdev);
34857692c94SEric Anholt 	struct v3d_dev *v3d = to_v3d_dev(drm);
34957692c94SEric Anholt 
35057692c94SEric Anholt 	drm_dev_unregister(drm);
35157692c94SEric Anholt 
35257692c94SEric Anholt 	v3d_gem_destroy(drm);
35357692c94SEric Anholt 
35457692c94SEric Anholt 	drm_dev_put(drm);
35557692c94SEric Anholt 
35657692c94SEric Anholt 	dma_free_wc(v3d->dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
35757692c94SEric Anholt 
35857692c94SEric Anholt 	return 0;
35957692c94SEric Anholt }
36057692c94SEric Anholt 
36157692c94SEric Anholt static struct platform_driver v3d_platform_driver = {
36257692c94SEric Anholt 	.probe		= v3d_platform_drm_probe,
36357692c94SEric Anholt 	.remove		= v3d_platform_drm_remove,
36457692c94SEric Anholt 	.driver		= {
36557692c94SEric Anholt 		.name	= "v3d",
36657692c94SEric Anholt 		.of_match_table = v3d_of_match,
36757692c94SEric Anholt 	},
36857692c94SEric Anholt };
36957692c94SEric Anholt 
37057692c94SEric Anholt static int __init v3d_drm_register(void)
37157692c94SEric Anholt {
37257692c94SEric Anholt 	return platform_driver_register(&v3d_platform_driver);
37357692c94SEric Anholt }
37457692c94SEric Anholt 
37557692c94SEric Anholt static void __exit v3d_drm_unregister(void)
37657692c94SEric Anholt {
37757692c94SEric Anholt 	platform_driver_unregister(&v3d_platform_driver);
37857692c94SEric Anholt }
37957692c94SEric Anholt 
38057692c94SEric Anholt module_init(v3d_drm_register);
38157692c94SEric Anholt module_exit(v3d_drm_unregister);
38257692c94SEric Anholt 
38357692c94SEric Anholt MODULE_ALIAS("platform:v3d-drm");
38457692c94SEric Anholt MODULE_DESCRIPTION("Broadcom V3D DRM Driver");
38557692c94SEric Anholt MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
38657692c94SEric Anholt MODULE_LICENSE("GPL v2");
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