1*57692c94SEric Anholt // SPDX-License-Identifier: GPL-2.0+ 2*57692c94SEric Anholt /* Copyright (C) 2014-2018 Broadcom */ 3*57692c94SEric Anholt 4*57692c94SEric Anholt /** 5*57692c94SEric Anholt * DOC: Broadcom V3D Graphics Driver 6*57692c94SEric Anholt * 7*57692c94SEric Anholt * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs. 8*57692c94SEric Anholt * For V3D 2.x support, see the VC4 driver. 9*57692c94SEric Anholt * 10*57692c94SEric Anholt * Currently only single-core rendering using the binner and renderer 11*57692c94SEric Anholt * is supported. The TFU (texture formatting unit) and V3D 4.x's CSD 12*57692c94SEric Anholt * (compute shader dispatch) are not yet supported. 13*57692c94SEric Anholt */ 14*57692c94SEric Anholt 15*57692c94SEric Anholt #include <linux/clk.h> 16*57692c94SEric Anholt #include <linux/device.h> 17*57692c94SEric Anholt #include <linux/io.h> 18*57692c94SEric Anholt #include <linux/module.h> 19*57692c94SEric Anholt #include <linux/of_platform.h> 20*57692c94SEric Anholt #include <linux/platform_device.h> 21*57692c94SEric Anholt #include <linux/pm_runtime.h> 22*57692c94SEric Anholt #include <drm/drm_fb_cma_helper.h> 23*57692c94SEric Anholt #include <drm/drm_fb_helper.h> 24*57692c94SEric Anholt 25*57692c94SEric Anholt #include "uapi/drm/v3d_drm.h" 26*57692c94SEric Anholt #include "v3d_drv.h" 27*57692c94SEric Anholt #include "v3d_regs.h" 28*57692c94SEric Anholt 29*57692c94SEric Anholt #define DRIVER_NAME "v3d" 30*57692c94SEric Anholt #define DRIVER_DESC "Broadcom V3D graphics" 31*57692c94SEric Anholt #define DRIVER_DATE "20180419" 32*57692c94SEric Anholt #define DRIVER_MAJOR 1 33*57692c94SEric Anholt #define DRIVER_MINOR 0 34*57692c94SEric Anholt #define DRIVER_PATCHLEVEL 0 35*57692c94SEric Anholt 36*57692c94SEric Anholt #ifdef CONFIG_PM 37*57692c94SEric Anholt static int v3d_runtime_suspend(struct device *dev) 38*57692c94SEric Anholt { 39*57692c94SEric Anholt struct drm_device *drm = dev_get_drvdata(dev); 40*57692c94SEric Anholt struct v3d_dev *v3d = to_v3d_dev(drm); 41*57692c94SEric Anholt 42*57692c94SEric Anholt v3d_irq_disable(v3d); 43*57692c94SEric Anholt 44*57692c94SEric Anholt clk_disable_unprepare(v3d->clk); 45*57692c94SEric Anholt 46*57692c94SEric Anholt return 0; 47*57692c94SEric Anholt } 48*57692c94SEric Anholt 49*57692c94SEric Anholt static int v3d_runtime_resume(struct device *dev) 50*57692c94SEric Anholt { 51*57692c94SEric Anholt struct drm_device *drm = dev_get_drvdata(dev); 52*57692c94SEric Anholt struct v3d_dev *v3d = to_v3d_dev(drm); 53*57692c94SEric Anholt int ret; 54*57692c94SEric Anholt 55*57692c94SEric Anholt ret = clk_prepare_enable(v3d->clk); 56*57692c94SEric Anholt if (ret != 0) 57*57692c94SEric Anholt return ret; 58*57692c94SEric Anholt 59*57692c94SEric Anholt /* XXX: VPM base */ 60*57692c94SEric Anholt 61*57692c94SEric Anholt v3d_mmu_set_page_table(v3d); 62*57692c94SEric Anholt v3d_irq_enable(v3d); 63*57692c94SEric Anholt 64*57692c94SEric Anholt return 0; 65*57692c94SEric Anholt } 66*57692c94SEric Anholt #endif 67*57692c94SEric Anholt 68*57692c94SEric Anholt static const struct dev_pm_ops v3d_v3d_pm_ops = { 69*57692c94SEric Anholt SET_RUNTIME_PM_OPS(v3d_runtime_suspend, v3d_runtime_resume, NULL) 70*57692c94SEric Anholt }; 71*57692c94SEric Anholt 72*57692c94SEric Anholt static int v3d_get_param_ioctl(struct drm_device *dev, void *data, 73*57692c94SEric Anholt struct drm_file *file_priv) 74*57692c94SEric Anholt { 75*57692c94SEric Anholt struct v3d_dev *v3d = to_v3d_dev(dev); 76*57692c94SEric Anholt struct drm_v3d_get_param *args = data; 77*57692c94SEric Anholt int ret; 78*57692c94SEric Anholt static const u32 reg_map[] = { 79*57692c94SEric Anholt [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG, 80*57692c94SEric Anholt [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1, 81*57692c94SEric Anholt [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2, 82*57692c94SEric Anholt [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3, 83*57692c94SEric Anholt [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0, 84*57692c94SEric Anholt [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1, 85*57692c94SEric Anholt [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2, 86*57692c94SEric Anholt }; 87*57692c94SEric Anholt 88*57692c94SEric Anholt if (args->pad != 0) 89*57692c94SEric Anholt return -EINVAL; 90*57692c94SEric Anholt 91*57692c94SEric Anholt /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need 92*57692c94SEric Anholt * to explicitly allow it in the "the register in our 93*57692c94SEric Anholt * parameter map" check. 94*57692c94SEric Anholt */ 95*57692c94SEric Anholt if (args->param < ARRAY_SIZE(reg_map) && 96*57692c94SEric Anholt (reg_map[args->param] || 97*57692c94SEric Anholt args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) { 98*57692c94SEric Anholt u32 offset = reg_map[args->param]; 99*57692c94SEric Anholt 100*57692c94SEric Anholt if (args->value != 0) 101*57692c94SEric Anholt return -EINVAL; 102*57692c94SEric Anholt 103*57692c94SEric Anholt ret = pm_runtime_get_sync(v3d->dev); 104*57692c94SEric Anholt if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 && 105*57692c94SEric Anholt args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) { 106*57692c94SEric Anholt args->value = V3D_CORE_READ(0, offset); 107*57692c94SEric Anholt } else { 108*57692c94SEric Anholt args->value = V3D_READ(offset); 109*57692c94SEric Anholt } 110*57692c94SEric Anholt pm_runtime_mark_last_busy(v3d->dev); 111*57692c94SEric Anholt pm_runtime_put_autosuspend(v3d->dev); 112*57692c94SEric Anholt return 0; 113*57692c94SEric Anholt } 114*57692c94SEric Anholt 115*57692c94SEric Anholt /* Any params that aren't just register reads would go here. */ 116*57692c94SEric Anholt 117*57692c94SEric Anholt DRM_DEBUG("Unknown parameter %d\n", args->param); 118*57692c94SEric Anholt return -EINVAL; 119*57692c94SEric Anholt } 120*57692c94SEric Anholt 121*57692c94SEric Anholt static int 122*57692c94SEric Anholt v3d_open(struct drm_device *dev, struct drm_file *file) 123*57692c94SEric Anholt { 124*57692c94SEric Anholt struct v3d_dev *v3d = to_v3d_dev(dev); 125*57692c94SEric Anholt struct v3d_file_priv *v3d_priv; 126*57692c94SEric Anholt int i; 127*57692c94SEric Anholt 128*57692c94SEric Anholt v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL); 129*57692c94SEric Anholt if (!v3d_priv) 130*57692c94SEric Anholt return -ENOMEM; 131*57692c94SEric Anholt 132*57692c94SEric Anholt v3d_priv->v3d = v3d; 133*57692c94SEric Anholt 134*57692c94SEric Anholt for (i = 0; i < V3D_MAX_QUEUES; i++) { 135*57692c94SEric Anholt drm_sched_entity_init(&v3d->queue[i].sched, 136*57692c94SEric Anholt &v3d_priv->sched_entity[i], 137*57692c94SEric Anholt &v3d->queue[i].sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL], 138*57692c94SEric Anholt 32, NULL); 139*57692c94SEric Anholt } 140*57692c94SEric Anholt 141*57692c94SEric Anholt file->driver_priv = v3d_priv; 142*57692c94SEric Anholt 143*57692c94SEric Anholt return 0; 144*57692c94SEric Anholt } 145*57692c94SEric Anholt 146*57692c94SEric Anholt static void 147*57692c94SEric Anholt v3d_postclose(struct drm_device *dev, struct drm_file *file) 148*57692c94SEric Anholt { 149*57692c94SEric Anholt struct v3d_dev *v3d = to_v3d_dev(dev); 150*57692c94SEric Anholt struct v3d_file_priv *v3d_priv = file->driver_priv; 151*57692c94SEric Anholt enum v3d_queue q; 152*57692c94SEric Anholt 153*57692c94SEric Anholt for (q = 0; q < V3D_MAX_QUEUES; q++) { 154*57692c94SEric Anholt drm_sched_entity_fini(&v3d->queue[q].sched, 155*57692c94SEric Anholt &v3d_priv->sched_entity[q]); 156*57692c94SEric Anholt } 157*57692c94SEric Anholt 158*57692c94SEric Anholt kfree(v3d_priv); 159*57692c94SEric Anholt } 160*57692c94SEric Anholt 161*57692c94SEric Anholt static const struct file_operations v3d_drm_fops = { 162*57692c94SEric Anholt .owner = THIS_MODULE, 163*57692c94SEric Anholt .open = drm_open, 164*57692c94SEric Anholt .release = drm_release, 165*57692c94SEric Anholt .unlocked_ioctl = drm_ioctl, 166*57692c94SEric Anholt .mmap = v3d_mmap, 167*57692c94SEric Anholt .poll = drm_poll, 168*57692c94SEric Anholt .read = drm_read, 169*57692c94SEric Anholt .compat_ioctl = drm_compat_ioctl, 170*57692c94SEric Anholt .llseek = noop_llseek, 171*57692c94SEric Anholt }; 172*57692c94SEric Anholt 173*57692c94SEric Anholt /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP 174*57692c94SEric Anholt * protection between clients. Note that render nodes would be be 175*57692c94SEric Anholt * able to submit CLs that could access BOs from clients authenticated 176*57692c94SEric Anholt * with the master node. 177*57692c94SEric Anholt */ 178*57692c94SEric Anholt static const struct drm_ioctl_desc v3d_drm_ioctls[] = { 179*57692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 180*57692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW), 181*57692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW), 182*57692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW), 183*57692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW), 184*57692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW), 185*57692c94SEric Anholt }; 186*57692c94SEric Anholt 187*57692c94SEric Anholt static const struct vm_operations_struct v3d_vm_ops = { 188*57692c94SEric Anholt .fault = v3d_gem_fault, 189*57692c94SEric Anholt .open = drm_gem_vm_open, 190*57692c94SEric Anholt .close = drm_gem_vm_close, 191*57692c94SEric Anholt }; 192*57692c94SEric Anholt 193*57692c94SEric Anholt static struct drm_driver v3d_drm_driver = { 194*57692c94SEric Anholt .driver_features = (DRIVER_GEM | 195*57692c94SEric Anholt DRIVER_RENDER | 196*57692c94SEric Anholt DRIVER_PRIME | 197*57692c94SEric Anholt DRIVER_SYNCOBJ), 198*57692c94SEric Anholt 199*57692c94SEric Anholt .open = v3d_open, 200*57692c94SEric Anholt .postclose = v3d_postclose, 201*57692c94SEric Anholt 202*57692c94SEric Anholt #if defined(CONFIG_DEBUG_FS) 203*57692c94SEric Anholt .debugfs_init = v3d_debugfs_init, 204*57692c94SEric Anholt #endif 205*57692c94SEric Anholt 206*57692c94SEric Anholt .gem_free_object_unlocked = v3d_free_object, 207*57692c94SEric Anholt .gem_vm_ops = &v3d_vm_ops, 208*57692c94SEric Anholt 209*57692c94SEric Anholt .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 210*57692c94SEric Anholt .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 211*57692c94SEric Anholt .gem_prime_import = drm_gem_prime_import, 212*57692c94SEric Anholt .gem_prime_export = drm_gem_prime_export, 213*57692c94SEric Anholt .gem_prime_res_obj = v3d_prime_res_obj, 214*57692c94SEric Anholt .gem_prime_get_sg_table = v3d_prime_get_sg_table, 215*57692c94SEric Anholt .gem_prime_import_sg_table = v3d_prime_import_sg_table, 216*57692c94SEric Anholt .gem_prime_mmap = v3d_prime_mmap, 217*57692c94SEric Anholt 218*57692c94SEric Anholt .ioctls = v3d_drm_ioctls, 219*57692c94SEric Anholt .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls), 220*57692c94SEric Anholt .fops = &v3d_drm_fops, 221*57692c94SEric Anholt 222*57692c94SEric Anholt .name = DRIVER_NAME, 223*57692c94SEric Anholt .desc = DRIVER_DESC, 224*57692c94SEric Anholt .date = DRIVER_DATE, 225*57692c94SEric Anholt .major = DRIVER_MAJOR, 226*57692c94SEric Anholt .minor = DRIVER_MINOR, 227*57692c94SEric Anholt .patchlevel = DRIVER_PATCHLEVEL, 228*57692c94SEric Anholt }; 229*57692c94SEric Anholt 230*57692c94SEric Anholt static const struct of_device_id v3d_of_match[] = { 231*57692c94SEric Anholt { .compatible = "brcm,7268-v3d" }, 232*57692c94SEric Anholt { .compatible = "brcm,7278-v3d" }, 233*57692c94SEric Anholt {}, 234*57692c94SEric Anholt }; 235*57692c94SEric Anholt MODULE_DEVICE_TABLE(of, v3d_of_match); 236*57692c94SEric Anholt 237*57692c94SEric Anholt static int 238*57692c94SEric Anholt map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) 239*57692c94SEric Anholt { 240*57692c94SEric Anholt struct resource *res = 241*57692c94SEric Anholt platform_get_resource_byname(v3d->pdev, IORESOURCE_MEM, name); 242*57692c94SEric Anholt 243*57692c94SEric Anholt *regs = devm_ioremap_resource(v3d->dev, res); 244*57692c94SEric Anholt return PTR_ERR_OR_ZERO(*regs); 245*57692c94SEric Anholt } 246*57692c94SEric Anholt 247*57692c94SEric Anholt static int v3d_platform_drm_probe(struct platform_device *pdev) 248*57692c94SEric Anholt { 249*57692c94SEric Anholt struct device *dev = &pdev->dev; 250*57692c94SEric Anholt struct drm_device *drm; 251*57692c94SEric Anholt struct v3d_dev *v3d; 252*57692c94SEric Anholt int ret; 253*57692c94SEric Anholt u32 ident1; 254*57692c94SEric Anholt 255*57692c94SEric Anholt dev->coherent_dma_mask = DMA_BIT_MASK(36); 256*57692c94SEric Anholt 257*57692c94SEric Anholt v3d = kzalloc(sizeof(*v3d), GFP_KERNEL); 258*57692c94SEric Anholt if (!v3d) 259*57692c94SEric Anholt return -ENOMEM; 260*57692c94SEric Anholt v3d->dev = dev; 261*57692c94SEric Anholt v3d->pdev = pdev; 262*57692c94SEric Anholt drm = &v3d->drm; 263*57692c94SEric Anholt 264*57692c94SEric Anholt ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); 265*57692c94SEric Anholt if (ret) 266*57692c94SEric Anholt goto dev_free; 267*57692c94SEric Anholt 268*57692c94SEric Anholt ret = map_regs(v3d, &v3d->hub_regs, "hub"); 269*57692c94SEric Anholt if (ret) 270*57692c94SEric Anholt goto dev_free; 271*57692c94SEric Anholt 272*57692c94SEric Anholt ret = map_regs(v3d, &v3d->core_regs[0], "core0"); 273*57692c94SEric Anholt if (ret) 274*57692c94SEric Anholt goto dev_free; 275*57692c94SEric Anholt 276*57692c94SEric Anholt ident1 = V3D_READ(V3D_HUB_IDENT1); 277*57692c94SEric Anholt v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + 278*57692c94SEric Anholt V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV)); 279*57692c94SEric Anholt v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); 280*57692c94SEric Anholt WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ 281*57692c94SEric Anholt 282*57692c94SEric Anholt if (v3d->ver < 41) { 283*57692c94SEric Anholt ret = map_regs(v3d, &v3d->gca_regs, "gca"); 284*57692c94SEric Anholt if (ret) 285*57692c94SEric Anholt goto dev_free; 286*57692c94SEric Anholt } 287*57692c94SEric Anholt 288*57692c94SEric Anholt v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, 289*57692c94SEric Anholt GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 290*57692c94SEric Anholt if (!v3d->mmu_scratch) { 291*57692c94SEric Anholt dev_err(dev, "Failed to allocate MMU scratch page\n"); 292*57692c94SEric Anholt ret = -ENOMEM; 293*57692c94SEric Anholt goto dev_free; 294*57692c94SEric Anholt } 295*57692c94SEric Anholt 296*57692c94SEric Anholt pm_runtime_use_autosuspend(dev); 297*57692c94SEric Anholt pm_runtime_set_autosuspend_delay(dev, 50); 298*57692c94SEric Anholt pm_runtime_enable(dev); 299*57692c94SEric Anholt 300*57692c94SEric Anholt ret = drm_dev_init(&v3d->drm, &v3d_drm_driver, dev); 301*57692c94SEric Anholt if (ret) 302*57692c94SEric Anholt goto dma_free; 303*57692c94SEric Anholt 304*57692c94SEric Anholt platform_set_drvdata(pdev, drm); 305*57692c94SEric Anholt drm->dev_private = v3d; 306*57692c94SEric Anholt 307*57692c94SEric Anholt ret = v3d_gem_init(drm); 308*57692c94SEric Anholt if (ret) 309*57692c94SEric Anholt goto dev_destroy; 310*57692c94SEric Anholt 311*57692c94SEric Anholt v3d_irq_init(v3d); 312*57692c94SEric Anholt 313*57692c94SEric Anholt ret = drm_dev_register(drm, 0); 314*57692c94SEric Anholt if (ret) 315*57692c94SEric Anholt goto gem_destroy; 316*57692c94SEric Anholt 317*57692c94SEric Anholt return 0; 318*57692c94SEric Anholt 319*57692c94SEric Anholt gem_destroy: 320*57692c94SEric Anholt v3d_gem_destroy(drm); 321*57692c94SEric Anholt dev_destroy: 322*57692c94SEric Anholt drm_dev_put(drm); 323*57692c94SEric Anholt dma_free: 324*57692c94SEric Anholt dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 325*57692c94SEric Anholt dev_free: 326*57692c94SEric Anholt kfree(v3d); 327*57692c94SEric Anholt return ret; 328*57692c94SEric Anholt } 329*57692c94SEric Anholt 330*57692c94SEric Anholt static int v3d_platform_drm_remove(struct platform_device *pdev) 331*57692c94SEric Anholt { 332*57692c94SEric Anholt struct drm_device *drm = platform_get_drvdata(pdev); 333*57692c94SEric Anholt struct v3d_dev *v3d = to_v3d_dev(drm); 334*57692c94SEric Anholt 335*57692c94SEric Anholt drm_dev_unregister(drm); 336*57692c94SEric Anholt 337*57692c94SEric Anholt v3d_gem_destroy(drm); 338*57692c94SEric Anholt 339*57692c94SEric Anholt drm_dev_put(drm); 340*57692c94SEric Anholt 341*57692c94SEric Anholt dma_free_wc(v3d->dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 342*57692c94SEric Anholt 343*57692c94SEric Anholt return 0; 344*57692c94SEric Anholt } 345*57692c94SEric Anholt 346*57692c94SEric Anholt static struct platform_driver v3d_platform_driver = { 347*57692c94SEric Anholt .probe = v3d_platform_drm_probe, 348*57692c94SEric Anholt .remove = v3d_platform_drm_remove, 349*57692c94SEric Anholt .driver = { 350*57692c94SEric Anholt .name = "v3d", 351*57692c94SEric Anholt .of_match_table = v3d_of_match, 352*57692c94SEric Anholt }, 353*57692c94SEric Anholt }; 354*57692c94SEric Anholt 355*57692c94SEric Anholt static int __init v3d_drm_register(void) 356*57692c94SEric Anholt { 357*57692c94SEric Anholt return platform_driver_register(&v3d_platform_driver); 358*57692c94SEric Anholt } 359*57692c94SEric Anholt 360*57692c94SEric Anholt static void __exit v3d_drm_unregister(void) 361*57692c94SEric Anholt { 362*57692c94SEric Anholt platform_driver_unregister(&v3d_platform_driver); 363*57692c94SEric Anholt } 364*57692c94SEric Anholt 365*57692c94SEric Anholt module_init(v3d_drm_register); 366*57692c94SEric Anholt module_exit(v3d_drm_unregister); 367*57692c94SEric Anholt 368*57692c94SEric Anholt MODULE_ALIAS("platform:v3d-drm"); 369*57692c94SEric Anholt MODULE_DESCRIPTION("Broadcom V3D DRM Driver"); 370*57692c94SEric Anholt MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 371*57692c94SEric Anholt MODULE_LICENSE("GPL v2"); 372