157692c94SEric Anholt // SPDX-License-Identifier: GPL-2.0+ 257692c94SEric Anholt /* Copyright (C) 2014-2018 Broadcom */ 357692c94SEric Anholt 457692c94SEric Anholt /** 557692c94SEric Anholt * DOC: Broadcom V3D Graphics Driver 657692c94SEric Anholt * 757692c94SEric Anholt * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs. 857692c94SEric Anholt * For V3D 2.x support, see the VC4 driver. 957692c94SEric Anholt * 10d223f98fSEric Anholt * The V3D GPU includes a tiled render (composed of a bin and render 11d223f98fSEric Anholt * pipelines), the TFU (texture formatting unit), and the CSD (compute 12d223f98fSEric Anholt * shader dispatch). 1357692c94SEric Anholt */ 1457692c94SEric Anholt 1557692c94SEric Anholt #include <linux/clk.h> 1657692c94SEric Anholt #include <linux/device.h> 17220989e7SSam Ravnborg #include <linux/dma-mapping.h> 1857692c94SEric Anholt #include <linux/io.h> 1957692c94SEric Anholt #include <linux/module.h> 2057692c94SEric Anholt #include <linux/of_platform.h> 2157692c94SEric Anholt #include <linux/platform_device.h> 2257692c94SEric Anholt #include <linux/pm_runtime.h> 23eea9b97bSEric Anholt #include <linux/reset.h> 24220989e7SSam Ravnborg 25220989e7SSam Ravnborg #include <drm/drm_drv.h> 2657692c94SEric Anholt #include <drm/drm_fb_cma_helper.h> 2757692c94SEric Anholt #include <drm/drm_fb_helper.h> 28ea3aa620SDaniel Vetter #include <drm/drm_managed.h> 29220989e7SSam Ravnborg #include <uapi/drm/v3d_drm.h> 3057692c94SEric Anholt 3157692c94SEric Anholt #include "v3d_drv.h" 3257692c94SEric Anholt #include "v3d_regs.h" 3357692c94SEric Anholt 3457692c94SEric Anholt #define DRIVER_NAME "v3d" 3557692c94SEric Anholt #define DRIVER_DESC "Broadcom V3D graphics" 3657692c94SEric Anholt #define DRIVER_DATE "20180419" 3757692c94SEric Anholt #define DRIVER_MAJOR 1 3857692c94SEric Anholt #define DRIVER_MINOR 0 3957692c94SEric Anholt #define DRIVER_PATCHLEVEL 0 4057692c94SEric Anholt 4157692c94SEric Anholt static int v3d_get_param_ioctl(struct drm_device *dev, void *data, 4257692c94SEric Anholt struct drm_file *file_priv) 4357692c94SEric Anholt { 4457692c94SEric Anholt struct v3d_dev *v3d = to_v3d_dev(dev); 4557692c94SEric Anholt struct drm_v3d_get_param *args = data; 4657692c94SEric Anholt int ret; 4757692c94SEric Anholt static const u32 reg_map[] = { 4857692c94SEric Anholt [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG, 4957692c94SEric Anholt [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1, 5057692c94SEric Anholt [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2, 5157692c94SEric Anholt [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3, 5257692c94SEric Anholt [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0, 5357692c94SEric Anholt [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1, 5457692c94SEric Anholt [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2, 5557692c94SEric Anholt }; 5657692c94SEric Anholt 5757692c94SEric Anholt if (args->pad != 0) 5857692c94SEric Anholt return -EINVAL; 5957692c94SEric Anholt 6057692c94SEric Anholt /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need 6157692c94SEric Anholt * to explicitly allow it in the "the register in our 6257692c94SEric Anholt * parameter map" check. 6357692c94SEric Anholt */ 6457692c94SEric Anholt if (args->param < ARRAY_SIZE(reg_map) && 6557692c94SEric Anholt (reg_map[args->param] || 6657692c94SEric Anholt args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) { 6757692c94SEric Anholt u32 offset = reg_map[args->param]; 6857692c94SEric Anholt 6957692c94SEric Anholt if (args->value != 0) 7057692c94SEric Anholt return -EINVAL; 7157692c94SEric Anholt 72bc662528SDaniel Vetter ret = pm_runtime_get_sync(v3d->drm.dev); 733c77ff8fSKangjie Lu if (ret < 0) 743c77ff8fSKangjie Lu return ret; 7557692c94SEric Anholt if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 && 7657692c94SEric Anholt args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) { 7757692c94SEric Anholt args->value = V3D_CORE_READ(0, offset); 7857692c94SEric Anholt } else { 7957692c94SEric Anholt args->value = V3D_READ(offset); 8057692c94SEric Anholt } 81bc662528SDaniel Vetter pm_runtime_mark_last_busy(v3d->drm.dev); 82bc662528SDaniel Vetter pm_runtime_put_autosuspend(v3d->drm.dev); 8357692c94SEric Anholt return 0; 8457692c94SEric Anholt } 8557692c94SEric Anholt 861584f16cSEric Anholt switch (args->param) { 871584f16cSEric Anholt case DRM_V3D_PARAM_SUPPORTS_TFU: 881584f16cSEric Anholt args->value = 1; 891584f16cSEric Anholt return 0; 90d223f98fSEric Anholt case DRM_V3D_PARAM_SUPPORTS_CSD: 91d223f98fSEric Anholt args->value = v3d_has_csd(v3d); 92d223f98fSEric Anholt return 0; 93455d56ceSIago Toral Quiroga case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH: 94455d56ceSIago Toral Quiroga args->value = 1; 95455d56ceSIago Toral Quiroga return 0; 9626a4dc29SJuan A. Suarez Romero case DRM_V3D_PARAM_SUPPORTS_PERFMON: 9726a4dc29SJuan A. Suarez Romero args->value = (v3d->ver >= 40); 9826a4dc29SJuan A. Suarez Romero return 0; 99e4165ae8SMelissa Wen case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT: 100e4165ae8SMelissa Wen args->value = 1; 101e4165ae8SMelissa Wen return 0; 1021584f16cSEric Anholt default: 10357692c94SEric Anholt DRM_DEBUG("Unknown parameter %d\n", args->param); 10457692c94SEric Anholt return -EINVAL; 10557692c94SEric Anholt } 1061584f16cSEric Anholt } 10757692c94SEric Anholt 10857692c94SEric Anholt static int 10957692c94SEric Anholt v3d_open(struct drm_device *dev, struct drm_file *file) 11057692c94SEric Anholt { 11157692c94SEric Anholt struct v3d_dev *v3d = to_v3d_dev(dev); 11257692c94SEric Anholt struct v3d_file_priv *v3d_priv; 113b3ac1766SNirmoy Das struct drm_gpu_scheduler *sched; 11457692c94SEric Anholt int i; 11557692c94SEric Anholt 11657692c94SEric Anholt v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL); 11757692c94SEric Anholt if (!v3d_priv) 11857692c94SEric Anholt return -ENOMEM; 11957692c94SEric Anholt 12057692c94SEric Anholt v3d_priv->v3d = v3d; 12157692c94SEric Anholt 12257692c94SEric Anholt for (i = 0; i < V3D_MAX_QUEUES; i++) { 123b3ac1766SNirmoy Das sched = &v3d->queue[i].sched; 124b3ac1766SNirmoy Das drm_sched_entity_init(&v3d_priv->sched_entity[i], 125b3ac1766SNirmoy Das DRM_SCHED_PRIORITY_NORMAL, &sched, 126b3ac1766SNirmoy Das 1, NULL); 12757692c94SEric Anholt } 12857692c94SEric Anholt 12926a4dc29SJuan A. Suarez Romero v3d_perfmon_open_file(v3d_priv); 13057692c94SEric Anholt file->driver_priv = v3d_priv; 13157692c94SEric Anholt 13257692c94SEric Anholt return 0; 13357692c94SEric Anholt } 13457692c94SEric Anholt 13557692c94SEric Anholt static void 13657692c94SEric Anholt v3d_postclose(struct drm_device *dev, struct drm_file *file) 13757692c94SEric Anholt { 13857692c94SEric Anholt struct v3d_file_priv *v3d_priv = file->driver_priv; 13957692c94SEric Anholt enum v3d_queue q; 14057692c94SEric Anholt 141e4165ae8SMelissa Wen for (q = 0; q < V3D_MAX_QUEUES; q++) 142cdc50176SNayan Deshmukh drm_sched_entity_destroy(&v3d_priv->sched_entity[q]); 14357692c94SEric Anholt 14426a4dc29SJuan A. Suarez Romero v3d_perfmon_close_file(v3d_priv); 14557692c94SEric Anholt kfree(v3d_priv); 14657692c94SEric Anholt } 14757692c94SEric Anholt 148eee9a2e0SGerd Hoffmann DEFINE_DRM_GEM_FOPS(v3d_drm_fops); 14957692c94SEric Anholt 15057692c94SEric Anholt /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP 151bb3425efSMelissa Wen * protection between clients. Note that render nodes would be 15257692c94SEric Anholt * able to submit CLs that could access BOs from clients authenticated 1531584f16cSEric Anholt * with the master node. The TFU doesn't use the GMP, so it would 1541584f16cSEric Anholt * need to stay DRM_AUTH until we do buffer size/offset validation. 15557692c94SEric Anholt */ 15657692c94SEric Anholt static const struct drm_ioctl_desc v3d_drm_ioctls[] = { 15757692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 15857692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW), 15957692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW), 16057692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW), 16157692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW), 16257692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW), 1631584f16cSEric Anholt DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 164d223f98fSEric Anholt DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 16526a4dc29SJuan A. Suarez Romero DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW), 16626a4dc29SJuan A. Suarez Romero DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW), 16726a4dc29SJuan A. Suarez Romero DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW), 16857692c94SEric Anholt }; 16957692c94SEric Anholt 17070a59dd8SDaniel Vetter static const struct drm_driver v3d_drm_driver = { 17157692c94SEric Anholt .driver_features = (DRIVER_GEM | 17257692c94SEric Anholt DRIVER_RENDER | 17357692c94SEric Anholt DRIVER_SYNCOBJ), 17457692c94SEric Anholt 17557692c94SEric Anholt .open = v3d_open, 17657692c94SEric Anholt .postclose = v3d_postclose, 17757692c94SEric Anholt 17857692c94SEric Anholt #if defined(CONFIG_DEBUG_FS) 17957692c94SEric Anholt .debugfs_init = v3d_debugfs_init, 18057692c94SEric Anholt #endif 18157692c94SEric Anholt 18240609d48SEric Anholt .gem_create_object = v3d_create_object, 18357692c94SEric Anholt .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 18457692c94SEric Anholt .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 18557692c94SEric Anholt .gem_prime_import_sg_table = v3d_prime_import_sg_table, 18640609d48SEric Anholt .gem_prime_mmap = drm_gem_prime_mmap, 18757692c94SEric Anholt 18857692c94SEric Anholt .ioctls = v3d_drm_ioctls, 18957692c94SEric Anholt .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls), 19057692c94SEric Anholt .fops = &v3d_drm_fops, 19157692c94SEric Anholt 19257692c94SEric Anholt .name = DRIVER_NAME, 19357692c94SEric Anholt .desc = DRIVER_DESC, 19457692c94SEric Anholt .date = DRIVER_DATE, 19557692c94SEric Anholt .major = DRIVER_MAJOR, 19657692c94SEric Anholt .minor = DRIVER_MINOR, 19757692c94SEric Anholt .patchlevel = DRIVER_PATCHLEVEL, 19857692c94SEric Anholt }; 19957692c94SEric Anholt 20057692c94SEric Anholt static const struct of_device_id v3d_of_match[] = { 20157692c94SEric Anholt { .compatible = "brcm,7268-v3d" }, 20257692c94SEric Anholt { .compatible = "brcm,7278-v3d" }, 20357692c94SEric Anholt {}, 20457692c94SEric Anholt }; 20557692c94SEric Anholt MODULE_DEVICE_TABLE(of, v3d_of_match); 20657692c94SEric Anholt 20757692c94SEric Anholt static int 20857692c94SEric Anholt map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) 20957692c94SEric Anholt { 210c3c7d70bSCai Huoqing *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name); 21157692c94SEric Anholt return PTR_ERR_OR_ZERO(*regs); 21257692c94SEric Anholt } 21357692c94SEric Anholt 21457692c94SEric Anholt static int v3d_platform_drm_probe(struct platform_device *pdev) 21557692c94SEric Anholt { 21657692c94SEric Anholt struct device *dev = &pdev->dev; 21757692c94SEric Anholt struct drm_device *drm; 21857692c94SEric Anholt struct v3d_dev *v3d; 21957692c94SEric Anholt int ret; 220091d6283SEric Anholt u32 mmu_debug; 22157692c94SEric Anholt u32 ident1; 222*4a391561SJiasheng Jiang u64 mask; 22357692c94SEric Anholt 224235b7e7dSDaniel Vetter v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm); 225235b7e7dSDaniel Vetter if (IS_ERR(v3d)) 226235b7e7dSDaniel Vetter return PTR_ERR(v3d); 227235b7e7dSDaniel Vetter 22857692c94SEric Anholt drm = &v3d->drm; 22957692c94SEric Anholt 230ea3aa620SDaniel Vetter platform_set_drvdata(pdev, drm); 231ea3aa620SDaniel Vetter 23257692c94SEric Anholt ret = map_regs(v3d, &v3d->hub_regs, "hub"); 23357692c94SEric Anholt if (ret) 234235b7e7dSDaniel Vetter return ret; 23557692c94SEric Anholt 23657692c94SEric Anholt ret = map_regs(v3d, &v3d->core_regs[0], "core0"); 23757692c94SEric Anholt if (ret) 238235b7e7dSDaniel Vetter return ret; 23957692c94SEric Anholt 240091d6283SEric Anholt mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO); 241*4a391561SJiasheng Jiang mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)); 242*4a391561SJiasheng Jiang ret = dma_set_mask_and_coherent(dev, mask); 243*4a391561SJiasheng Jiang if (ret) 244*4a391561SJiasheng Jiang return ret; 245*4a391561SJiasheng Jiang 24638c2c791SEric Anholt v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH); 247091d6283SEric Anholt 24857692c94SEric Anholt ident1 = V3D_READ(V3D_HUB_IDENT1); 24957692c94SEric Anholt v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + 25057692c94SEric Anholt V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV)); 25157692c94SEric Anholt v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); 25257692c94SEric Anholt WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ 25357692c94SEric Anholt 254eea9b97bSEric Anholt v3d->reset = devm_reset_control_get_exclusive(dev, NULL); 255eea9b97bSEric Anholt if (IS_ERR(v3d->reset)) { 256eea9b97bSEric Anholt ret = PTR_ERR(v3d->reset); 257eea9b97bSEric Anholt 258eea9b97bSEric Anholt if (ret == -EPROBE_DEFER) 259235b7e7dSDaniel Vetter return ret; 260eea9b97bSEric Anholt 261eea9b97bSEric Anholt v3d->reset = NULL; 262eea9b97bSEric Anholt ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); 263eea9b97bSEric Anholt if (ret) { 264eea9b97bSEric Anholt dev_err(dev, 265eea9b97bSEric Anholt "Failed to get reset control or bridge regs\n"); 266235b7e7dSDaniel Vetter return ret; 267eea9b97bSEric Anholt } 268eea9b97bSEric Anholt } 269eea9b97bSEric Anholt 27057692c94SEric Anholt if (v3d->ver < 41) { 27157692c94SEric Anholt ret = map_regs(v3d, &v3d->gca_regs, "gca"); 27257692c94SEric Anholt if (ret) 273235b7e7dSDaniel Vetter return ret; 27457692c94SEric Anholt } 27557692c94SEric Anholt 27657692c94SEric Anholt v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, 27757692c94SEric Anholt GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 27857692c94SEric Anholt if (!v3d->mmu_scratch) { 27957692c94SEric Anholt dev_err(dev, "Failed to allocate MMU scratch page\n"); 280235b7e7dSDaniel Vetter return -ENOMEM; 28157692c94SEric Anholt } 28257692c94SEric Anholt 28357692c94SEric Anholt pm_runtime_use_autosuspend(dev); 28457692c94SEric Anholt pm_runtime_set_autosuspend_delay(dev, 50); 28557692c94SEric Anholt pm_runtime_enable(dev); 28657692c94SEric Anholt 28757692c94SEric Anholt ret = v3d_gem_init(drm); 28857692c94SEric Anholt if (ret) 289ea3aa620SDaniel Vetter goto dma_free; 29057692c94SEric Anholt 291fc227715SEric Anholt ret = v3d_irq_init(v3d); 29257692c94SEric Anholt if (ret) 29357692c94SEric Anholt goto gem_destroy; 29457692c94SEric Anholt 295fc227715SEric Anholt ret = drm_dev_register(drm, 0); 296fc227715SEric Anholt if (ret) 297fc227715SEric Anholt goto irq_disable; 298fc227715SEric Anholt 29957692c94SEric Anholt return 0; 30057692c94SEric Anholt 301fc227715SEric Anholt irq_disable: 302fc227715SEric Anholt v3d_irq_disable(v3d); 30357692c94SEric Anholt gem_destroy: 30457692c94SEric Anholt v3d_gem_destroy(drm); 30557692c94SEric Anholt dma_free: 30657692c94SEric Anholt dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 30757692c94SEric Anholt return ret; 30857692c94SEric Anholt } 30957692c94SEric Anholt 31057692c94SEric Anholt static int v3d_platform_drm_remove(struct platform_device *pdev) 31157692c94SEric Anholt { 31257692c94SEric Anholt struct drm_device *drm = platform_get_drvdata(pdev); 31357692c94SEric Anholt struct v3d_dev *v3d = to_v3d_dev(drm); 31457692c94SEric Anholt 31557692c94SEric Anholt drm_dev_unregister(drm); 31657692c94SEric Anholt 31757692c94SEric Anholt v3d_gem_destroy(drm); 31857692c94SEric Anholt 319bc662528SDaniel Vetter dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch, 320bc662528SDaniel Vetter v3d->mmu_scratch_paddr); 32157692c94SEric Anholt 32257692c94SEric Anholt return 0; 32357692c94SEric Anholt } 32457692c94SEric Anholt 32557692c94SEric Anholt static struct platform_driver v3d_platform_driver = { 32657692c94SEric Anholt .probe = v3d_platform_drm_probe, 32757692c94SEric Anholt .remove = v3d_platform_drm_remove, 32857692c94SEric Anholt .driver = { 32957692c94SEric Anholt .name = "v3d", 33057692c94SEric Anholt .of_match_table = v3d_of_match, 33157692c94SEric Anholt }, 33257692c94SEric Anholt }; 33357692c94SEric Anholt 334ad28cd69SQinglang Miao module_platform_driver(v3d_platform_driver); 33557692c94SEric Anholt 33657692c94SEric Anholt MODULE_ALIAS("platform:v3d-drm"); 33757692c94SEric Anholt MODULE_DESCRIPTION("Broadcom V3D DRM Driver"); 33857692c94SEric Anholt MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 33957692c94SEric Anholt MODULE_LICENSE("GPL v2"); 340