xref: /openbmc/linux/drivers/gpu/drm/v3d/v3d_drv.c (revision 334dd38a3878a8fba1cfaa3c715163226de3cddc)
157692c94SEric Anholt // SPDX-License-Identifier: GPL-2.0+
257692c94SEric Anholt /* Copyright (C) 2014-2018 Broadcom */
357692c94SEric Anholt 
457692c94SEric Anholt /**
557692c94SEric Anholt  * DOC: Broadcom V3D Graphics Driver
657692c94SEric Anholt  *
757692c94SEric Anholt  * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs.
857692c94SEric Anholt  * For V3D 2.x support, see the VC4 driver.
957692c94SEric Anholt  *
10d223f98fSEric Anholt  * The V3D GPU includes a tiled render (composed of a bin and render
11d223f98fSEric Anholt  * pipelines), the TFU (texture formatting unit), and the CSD (compute
12d223f98fSEric Anholt  * shader dispatch).
1357692c94SEric Anholt  */
1457692c94SEric Anholt 
1557692c94SEric Anholt #include <linux/clk.h>
1657692c94SEric Anholt #include <linux/device.h>
17220989e7SSam Ravnborg #include <linux/dma-mapping.h>
1857692c94SEric Anholt #include <linux/io.h>
1957692c94SEric Anholt #include <linux/module.h>
2057692c94SEric Anholt #include <linux/of_platform.h>
2157692c94SEric Anholt #include <linux/platform_device.h>
2257692c94SEric Anholt #include <linux/pm_runtime.h>
23eea9b97bSEric Anholt #include <linux/reset.h>
24220989e7SSam Ravnborg 
25220989e7SSam Ravnborg #include <drm/drm_drv.h>
2657692c94SEric Anholt #include <drm/drm_fb_cma_helper.h>
2757692c94SEric Anholt #include <drm/drm_fb_helper.h>
28ea3aa620SDaniel Vetter #include <drm/drm_managed.h>
29220989e7SSam Ravnborg #include <uapi/drm/v3d_drm.h>
3057692c94SEric Anholt 
3157692c94SEric Anholt #include "v3d_drv.h"
3257692c94SEric Anholt #include "v3d_regs.h"
3357692c94SEric Anholt 
3457692c94SEric Anholt #define DRIVER_NAME "v3d"
3557692c94SEric Anholt #define DRIVER_DESC "Broadcom V3D graphics"
3657692c94SEric Anholt #define DRIVER_DATE "20180419"
3757692c94SEric Anholt #define DRIVER_MAJOR 1
3857692c94SEric Anholt #define DRIVER_MINOR 0
3957692c94SEric Anholt #define DRIVER_PATCHLEVEL 0
4057692c94SEric Anholt 
4157692c94SEric Anholt static int v3d_get_param_ioctl(struct drm_device *dev, void *data,
4257692c94SEric Anholt 			       struct drm_file *file_priv)
4357692c94SEric Anholt {
4457692c94SEric Anholt 	struct v3d_dev *v3d = to_v3d_dev(dev);
4557692c94SEric Anholt 	struct drm_v3d_get_param *args = data;
4657692c94SEric Anholt 	int ret;
4757692c94SEric Anholt 	static const u32 reg_map[] = {
4857692c94SEric Anholt 		[DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG,
4957692c94SEric Anholt 		[DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1,
5057692c94SEric Anholt 		[DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2,
5157692c94SEric Anholt 		[DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3,
5257692c94SEric Anholt 		[DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0,
5357692c94SEric Anholt 		[DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1,
5457692c94SEric Anholt 		[DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2,
5557692c94SEric Anholt 	};
5657692c94SEric Anholt 
5757692c94SEric Anholt 	if (args->pad != 0)
5857692c94SEric Anholt 		return -EINVAL;
5957692c94SEric Anholt 
6057692c94SEric Anholt 	/* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need
6157692c94SEric Anholt 	 * to explicitly allow it in the "the register in our
6257692c94SEric Anholt 	 * parameter map" check.
6357692c94SEric Anholt 	 */
6457692c94SEric Anholt 	if (args->param < ARRAY_SIZE(reg_map) &&
6557692c94SEric Anholt 	    (reg_map[args->param] ||
6657692c94SEric Anholt 	     args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) {
6757692c94SEric Anholt 		u32 offset = reg_map[args->param];
6857692c94SEric Anholt 
6957692c94SEric Anholt 		if (args->value != 0)
7057692c94SEric Anholt 			return -EINVAL;
7157692c94SEric Anholt 
72bc662528SDaniel Vetter 		ret = pm_runtime_get_sync(v3d->drm.dev);
733c77ff8fSKangjie Lu 		if (ret < 0)
743c77ff8fSKangjie Lu 			return ret;
7557692c94SEric Anholt 		if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 &&
7657692c94SEric Anholt 		    args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) {
7757692c94SEric Anholt 			args->value = V3D_CORE_READ(0, offset);
7857692c94SEric Anholt 		} else {
7957692c94SEric Anholt 			args->value = V3D_READ(offset);
8057692c94SEric Anholt 		}
81bc662528SDaniel Vetter 		pm_runtime_mark_last_busy(v3d->drm.dev);
82bc662528SDaniel Vetter 		pm_runtime_put_autosuspend(v3d->drm.dev);
8357692c94SEric Anholt 		return 0;
8457692c94SEric Anholt 	}
8557692c94SEric Anholt 
8657692c94SEric Anholt 
871584f16cSEric Anholt 	switch (args->param) {
881584f16cSEric Anholt 	case DRM_V3D_PARAM_SUPPORTS_TFU:
891584f16cSEric Anholt 		args->value = 1;
901584f16cSEric Anholt 		return 0;
91d223f98fSEric Anholt 	case DRM_V3D_PARAM_SUPPORTS_CSD:
92d223f98fSEric Anholt 		args->value = v3d_has_csd(v3d);
93d223f98fSEric Anholt 		return 0;
94455d56ceSIago Toral Quiroga 	case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH:
95455d56ceSIago Toral Quiroga 		args->value = 1;
96455d56ceSIago Toral Quiroga 		return 0;
971584f16cSEric Anholt 	default:
9857692c94SEric Anholt 		DRM_DEBUG("Unknown parameter %d\n", args->param);
9957692c94SEric Anholt 		return -EINVAL;
10057692c94SEric Anholt 	}
1011584f16cSEric Anholt }
10257692c94SEric Anholt 
10357692c94SEric Anholt static int
10457692c94SEric Anholt v3d_open(struct drm_device *dev, struct drm_file *file)
10557692c94SEric Anholt {
10657692c94SEric Anholt 	struct v3d_dev *v3d = to_v3d_dev(dev);
10757692c94SEric Anholt 	struct v3d_file_priv *v3d_priv;
108b3ac1766SNirmoy Das 	struct drm_gpu_scheduler *sched;
10957692c94SEric Anholt 	int i;
11057692c94SEric Anholt 
11157692c94SEric Anholt 	v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL);
11257692c94SEric Anholt 	if (!v3d_priv)
11357692c94SEric Anholt 		return -ENOMEM;
11457692c94SEric Anholt 
11557692c94SEric Anholt 	v3d_priv->v3d = v3d;
11657692c94SEric Anholt 
11757692c94SEric Anholt 	for (i = 0; i < V3D_MAX_QUEUES; i++) {
118b3ac1766SNirmoy Das 		sched = &v3d->queue[i].sched;
119b3ac1766SNirmoy Das 		drm_sched_entity_init(&v3d_priv->sched_entity[i],
120b3ac1766SNirmoy Das 				      DRM_SCHED_PRIORITY_NORMAL, &sched,
121b3ac1766SNirmoy Das 				      1, NULL);
12257692c94SEric Anholt 	}
12357692c94SEric Anholt 
12457692c94SEric Anholt 	file->driver_priv = v3d_priv;
12557692c94SEric Anholt 
12657692c94SEric Anholt 	return 0;
12757692c94SEric Anholt }
12857692c94SEric Anholt 
12957692c94SEric Anholt static void
13057692c94SEric Anholt v3d_postclose(struct drm_device *dev, struct drm_file *file)
13157692c94SEric Anholt {
13257692c94SEric Anholt 	struct v3d_file_priv *v3d_priv = file->driver_priv;
13357692c94SEric Anholt 	enum v3d_queue q;
13457692c94SEric Anholt 
13557692c94SEric Anholt 	for (q = 0; q < V3D_MAX_QUEUES; q++) {
136cdc50176SNayan Deshmukh 		drm_sched_entity_destroy(&v3d_priv->sched_entity[q]);
13757692c94SEric Anholt 	}
13857692c94SEric Anholt 
13957692c94SEric Anholt 	kfree(v3d_priv);
14057692c94SEric Anholt }
14157692c94SEric Anholt 
142eee9a2e0SGerd Hoffmann DEFINE_DRM_GEM_FOPS(v3d_drm_fops);
14357692c94SEric Anholt 
14457692c94SEric Anholt /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP
14557692c94SEric Anholt  * protection between clients.  Note that render nodes would be be
14657692c94SEric Anholt  * able to submit CLs that could access BOs from clients authenticated
1471584f16cSEric Anholt  * with the master node.  The TFU doesn't use the GMP, so it would
1481584f16cSEric Anholt  * need to stay DRM_AUTH until we do buffer size/offset validation.
14957692c94SEric Anholt  */
15057692c94SEric Anholt static const struct drm_ioctl_desc v3d_drm_ioctls[] = {
15157692c94SEric Anholt 	DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
15257692c94SEric Anholt 	DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW),
15357692c94SEric Anholt 	DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW),
15457692c94SEric Anholt 	DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW),
15557692c94SEric Anholt 	DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW),
15657692c94SEric Anholt 	DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW),
1571584f16cSEric Anholt 	DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
158d223f98fSEric Anholt 	DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
15957692c94SEric Anholt };
16057692c94SEric Anholt 
16170a59dd8SDaniel Vetter static const struct drm_driver v3d_drm_driver = {
16257692c94SEric Anholt 	.driver_features = (DRIVER_GEM |
16357692c94SEric Anholt 			    DRIVER_RENDER |
16457692c94SEric Anholt 			    DRIVER_SYNCOBJ),
16557692c94SEric Anholt 
16657692c94SEric Anholt 	.open = v3d_open,
16757692c94SEric Anholt 	.postclose = v3d_postclose,
16857692c94SEric Anholt 
16957692c94SEric Anholt #if defined(CONFIG_DEBUG_FS)
17057692c94SEric Anholt 	.debugfs_init = v3d_debugfs_init,
17157692c94SEric Anholt #endif
17257692c94SEric Anholt 
17340609d48SEric Anholt 	.gem_create_object = v3d_create_object,
17457692c94SEric Anholt 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
17557692c94SEric Anholt 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
17657692c94SEric Anholt 	.gem_prime_import_sg_table = v3d_prime_import_sg_table,
17740609d48SEric Anholt 	.gem_prime_mmap = drm_gem_prime_mmap,
17857692c94SEric Anholt 
17957692c94SEric Anholt 	.ioctls = v3d_drm_ioctls,
18057692c94SEric Anholt 	.num_ioctls = ARRAY_SIZE(v3d_drm_ioctls),
18157692c94SEric Anholt 	.fops = &v3d_drm_fops,
18257692c94SEric Anholt 
18357692c94SEric Anholt 	.name = DRIVER_NAME,
18457692c94SEric Anholt 	.desc = DRIVER_DESC,
18557692c94SEric Anholt 	.date = DRIVER_DATE,
18657692c94SEric Anholt 	.major = DRIVER_MAJOR,
18757692c94SEric Anholt 	.minor = DRIVER_MINOR,
18857692c94SEric Anholt 	.patchlevel = DRIVER_PATCHLEVEL,
18957692c94SEric Anholt };
19057692c94SEric Anholt 
19157692c94SEric Anholt static const struct of_device_id v3d_of_match[] = {
19257692c94SEric Anholt 	{ .compatible = "brcm,7268-v3d" },
19357692c94SEric Anholt 	{ .compatible = "brcm,7278-v3d" },
19457692c94SEric Anholt 	{},
19557692c94SEric Anholt };
19657692c94SEric Anholt MODULE_DEVICE_TABLE(of, v3d_of_match);
19757692c94SEric Anholt 
19857692c94SEric Anholt static int
19957692c94SEric Anholt map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)
20057692c94SEric Anholt {
20157692c94SEric Anholt 	struct resource *res =
2020df3ac76SDaniel Vetter 		platform_get_resource_byname(v3d_to_pdev(v3d), IORESOURCE_MEM, name);
20357692c94SEric Anholt 
204bc662528SDaniel Vetter 	*regs = devm_ioremap_resource(v3d->drm.dev, res);
20557692c94SEric Anholt 	return PTR_ERR_OR_ZERO(*regs);
20657692c94SEric Anholt }
20757692c94SEric Anholt 
20857692c94SEric Anholt static int v3d_platform_drm_probe(struct platform_device *pdev)
20957692c94SEric Anholt {
21057692c94SEric Anholt 	struct device *dev = &pdev->dev;
21157692c94SEric Anholt 	struct drm_device *drm;
21257692c94SEric Anholt 	struct v3d_dev *v3d;
21357692c94SEric Anholt 	int ret;
214091d6283SEric Anholt 	u32 mmu_debug;
21557692c94SEric Anholt 	u32 ident1;
21657692c94SEric Anholt 
21757692c94SEric Anholt 
218235b7e7dSDaniel Vetter 	v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm);
219235b7e7dSDaniel Vetter 	if (IS_ERR(v3d))
220235b7e7dSDaniel Vetter 		return PTR_ERR(v3d);
221235b7e7dSDaniel Vetter 
22257692c94SEric Anholt 	drm = &v3d->drm;
22357692c94SEric Anholt 
224ea3aa620SDaniel Vetter 	platform_set_drvdata(pdev, drm);
225ea3aa620SDaniel Vetter 
22657692c94SEric Anholt 	ret = map_regs(v3d, &v3d->hub_regs, "hub");
22757692c94SEric Anholt 	if (ret)
228235b7e7dSDaniel Vetter 		return ret;
22957692c94SEric Anholt 
23057692c94SEric Anholt 	ret = map_regs(v3d, &v3d->core_regs[0], "core0");
23157692c94SEric Anholt 	if (ret)
232235b7e7dSDaniel Vetter 		return ret;
23357692c94SEric Anholt 
234091d6283SEric Anholt 	mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
235*334dd38aSPhil Elwell 	dma_set_mask_and_coherent(dev,
236*334dd38aSPhil Elwell 		DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)));
23738c2c791SEric Anholt 	v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);
238091d6283SEric Anholt 
23957692c94SEric Anholt 	ident1 = V3D_READ(V3D_HUB_IDENT1);
24057692c94SEric Anholt 	v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
24157692c94SEric Anholt 		    V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
24257692c94SEric Anholt 	v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
24357692c94SEric Anholt 	WARN_ON(v3d->cores > 1); /* multicore not yet implemented */
24457692c94SEric Anholt 
245eea9b97bSEric Anholt 	v3d->reset = devm_reset_control_get_exclusive(dev, NULL);
246eea9b97bSEric Anholt 	if (IS_ERR(v3d->reset)) {
247eea9b97bSEric Anholt 		ret = PTR_ERR(v3d->reset);
248eea9b97bSEric Anholt 
249eea9b97bSEric Anholt 		if (ret == -EPROBE_DEFER)
250235b7e7dSDaniel Vetter 			return ret;
251eea9b97bSEric Anholt 
252eea9b97bSEric Anholt 		v3d->reset = NULL;
253eea9b97bSEric Anholt 		ret = map_regs(v3d, &v3d->bridge_regs, "bridge");
254eea9b97bSEric Anholt 		if (ret) {
255eea9b97bSEric Anholt 			dev_err(dev,
256eea9b97bSEric Anholt 				"Failed to get reset control or bridge regs\n");
257235b7e7dSDaniel Vetter 			return ret;
258eea9b97bSEric Anholt 		}
259eea9b97bSEric Anholt 	}
260eea9b97bSEric Anholt 
26157692c94SEric Anholt 	if (v3d->ver < 41) {
26257692c94SEric Anholt 		ret = map_regs(v3d, &v3d->gca_regs, "gca");
26357692c94SEric Anholt 		if (ret)
264235b7e7dSDaniel Vetter 			return ret;
26557692c94SEric Anholt 	}
26657692c94SEric Anholt 
26757692c94SEric Anholt 	v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr,
26857692c94SEric Anholt 					GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
26957692c94SEric Anholt 	if (!v3d->mmu_scratch) {
27057692c94SEric Anholt 		dev_err(dev, "Failed to allocate MMU scratch page\n");
271235b7e7dSDaniel Vetter 		return -ENOMEM;
27257692c94SEric Anholt 	}
27357692c94SEric Anholt 
27457692c94SEric Anholt 	pm_runtime_use_autosuspend(dev);
27557692c94SEric Anholt 	pm_runtime_set_autosuspend_delay(dev, 50);
27657692c94SEric Anholt 	pm_runtime_enable(dev);
27757692c94SEric Anholt 
27857692c94SEric Anholt 	ret = v3d_gem_init(drm);
27957692c94SEric Anholt 	if (ret)
280ea3aa620SDaniel Vetter 		goto dma_free;
28157692c94SEric Anholt 
282fc227715SEric Anholt 	ret = v3d_irq_init(v3d);
28357692c94SEric Anholt 	if (ret)
28457692c94SEric Anholt 		goto gem_destroy;
28557692c94SEric Anholt 
286fc227715SEric Anholt 	ret = drm_dev_register(drm, 0);
287fc227715SEric Anholt 	if (ret)
288fc227715SEric Anholt 		goto irq_disable;
289fc227715SEric Anholt 
29057692c94SEric Anholt 	return 0;
29157692c94SEric Anholt 
292fc227715SEric Anholt irq_disable:
293fc227715SEric Anholt 	v3d_irq_disable(v3d);
29457692c94SEric Anholt gem_destroy:
29557692c94SEric Anholt 	v3d_gem_destroy(drm);
29657692c94SEric Anholt dma_free:
29757692c94SEric Anholt 	dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
29857692c94SEric Anholt 	return ret;
29957692c94SEric Anholt }
30057692c94SEric Anholt 
30157692c94SEric Anholt static int v3d_platform_drm_remove(struct platform_device *pdev)
30257692c94SEric Anholt {
30357692c94SEric Anholt 	struct drm_device *drm = platform_get_drvdata(pdev);
30457692c94SEric Anholt 	struct v3d_dev *v3d = to_v3d_dev(drm);
30557692c94SEric Anholt 
30657692c94SEric Anholt 	drm_dev_unregister(drm);
30757692c94SEric Anholt 
30857692c94SEric Anholt 	v3d_gem_destroy(drm);
30957692c94SEric Anholt 
310bc662528SDaniel Vetter 	dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch,
311bc662528SDaniel Vetter 		    v3d->mmu_scratch_paddr);
31257692c94SEric Anholt 
31357692c94SEric Anholt 	return 0;
31457692c94SEric Anholt }
31557692c94SEric Anholt 
31657692c94SEric Anholt static struct platform_driver v3d_platform_driver = {
31757692c94SEric Anholt 	.probe		= v3d_platform_drm_probe,
31857692c94SEric Anholt 	.remove		= v3d_platform_drm_remove,
31957692c94SEric Anholt 	.driver		= {
32057692c94SEric Anholt 		.name	= "v3d",
32157692c94SEric Anholt 		.of_match_table = v3d_of_match,
32257692c94SEric Anholt 	},
32357692c94SEric Anholt };
32457692c94SEric Anholt 
325ad28cd69SQinglang Miao module_platform_driver(v3d_platform_driver);
32657692c94SEric Anholt 
32757692c94SEric Anholt MODULE_ALIAS("platform:v3d-drm");
32857692c94SEric Anholt MODULE_DESCRIPTION("Broadcom V3D DRM Driver");
32957692c94SEric Anholt MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
33057692c94SEric Anholt MODULE_LICENSE("GPL v2");
331