157692c94SEric Anholt // SPDX-License-Identifier: GPL-2.0+
257692c94SEric Anholt /* Copyright (C) 2014-2018 Broadcom */
357692c94SEric Anholt
457692c94SEric Anholt /**
557692c94SEric Anholt * DOC: Broadcom V3D Graphics Driver
657692c94SEric Anholt *
757692c94SEric Anholt * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs.
857692c94SEric Anholt * For V3D 2.x support, see the VC4 driver.
957692c94SEric Anholt *
10d223f98fSEric Anholt * The V3D GPU includes a tiled render (composed of a bin and render
11d223f98fSEric Anholt * pipelines), the TFU (texture formatting unit), and the CSD (compute
12d223f98fSEric Anholt * shader dispatch).
1357692c94SEric Anholt */
1457692c94SEric Anholt
1557692c94SEric Anholt #include <linux/clk.h>
1657692c94SEric Anholt #include <linux/device.h>
17220989e7SSam Ravnborg #include <linux/dma-mapping.h>
1857692c94SEric Anholt #include <linux/io.h>
1957692c94SEric Anholt #include <linux/module.h>
2057692c94SEric Anholt #include <linux/of_platform.h>
2157692c94SEric Anholt #include <linux/platform_device.h>
22eea9b97bSEric Anholt #include <linux/reset.h>
23220989e7SSam Ravnborg
24220989e7SSam Ravnborg #include <drm/drm_drv.h>
25ea3aa620SDaniel Vetter #include <drm/drm_managed.h>
26220989e7SSam Ravnborg #include <uapi/drm/v3d_drm.h>
2757692c94SEric Anholt
2857692c94SEric Anholt #include "v3d_drv.h"
2957692c94SEric Anholt #include "v3d_regs.h"
3057692c94SEric Anholt
3157692c94SEric Anholt #define DRIVER_NAME "v3d"
3257692c94SEric Anholt #define DRIVER_DESC "Broadcom V3D graphics"
3357692c94SEric Anholt #define DRIVER_DATE "20180419"
3457692c94SEric Anholt #define DRIVER_MAJOR 1
3557692c94SEric Anholt #define DRIVER_MINOR 0
3657692c94SEric Anholt #define DRIVER_PATCHLEVEL 0
3757692c94SEric Anholt
v3d_get_param_ioctl(struct drm_device * dev,void * data,struct drm_file * file_priv)3857692c94SEric Anholt static int v3d_get_param_ioctl(struct drm_device *dev, void *data,
3957692c94SEric Anholt struct drm_file *file_priv)
4057692c94SEric Anholt {
4157692c94SEric Anholt struct v3d_dev *v3d = to_v3d_dev(dev);
4257692c94SEric Anholt struct drm_v3d_get_param *args = data;
4357692c94SEric Anholt static const u32 reg_map[] = {
4457692c94SEric Anholt [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG,
4557692c94SEric Anholt [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1,
4657692c94SEric Anholt [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2,
4757692c94SEric Anholt [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3,
4857692c94SEric Anholt [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0,
4957692c94SEric Anholt [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1,
5057692c94SEric Anholt [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2,
5157692c94SEric Anholt };
5257692c94SEric Anholt
5357692c94SEric Anholt if (args->pad != 0)
5457692c94SEric Anholt return -EINVAL;
5557692c94SEric Anholt
5657692c94SEric Anholt /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need
5757692c94SEric Anholt * to explicitly allow it in the "the register in our
5857692c94SEric Anholt * parameter map" check.
5957692c94SEric Anholt */
6057692c94SEric Anholt if (args->param < ARRAY_SIZE(reg_map) &&
6157692c94SEric Anholt (reg_map[args->param] ||
6257692c94SEric Anholt args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) {
6357692c94SEric Anholt u32 offset = reg_map[args->param];
6457692c94SEric Anholt
6557692c94SEric Anholt if (args->value != 0)
6657692c94SEric Anholt return -EINVAL;
6757692c94SEric Anholt
6857692c94SEric Anholt if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 &&
6957692c94SEric Anholt args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) {
7057692c94SEric Anholt args->value = V3D_CORE_READ(0, offset);
7157692c94SEric Anholt } else {
7257692c94SEric Anholt args->value = V3D_READ(offset);
7357692c94SEric Anholt }
7457692c94SEric Anholt return 0;
7557692c94SEric Anholt }
7657692c94SEric Anholt
771584f16cSEric Anholt switch (args->param) {
781584f16cSEric Anholt case DRM_V3D_PARAM_SUPPORTS_TFU:
791584f16cSEric Anholt args->value = 1;
801584f16cSEric Anholt return 0;
81d223f98fSEric Anholt case DRM_V3D_PARAM_SUPPORTS_CSD:
82d223f98fSEric Anholt args->value = v3d_has_csd(v3d);
83d223f98fSEric Anholt return 0;
84455d56ceSIago Toral Quiroga case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH:
85455d56ceSIago Toral Quiroga args->value = 1;
86455d56ceSIago Toral Quiroga return 0;
8726a4dc29SJuan A. Suarez Romero case DRM_V3D_PARAM_SUPPORTS_PERFMON:
8826a4dc29SJuan A. Suarez Romero args->value = (v3d->ver >= 40);
8926a4dc29SJuan A. Suarez Romero return 0;
90e4165ae8SMelissa Wen case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT:
91e4165ae8SMelissa Wen args->value = 1;
92e4165ae8SMelissa Wen return 0;
931584f16cSEric Anholt default:
9457692c94SEric Anholt DRM_DEBUG("Unknown parameter %d\n", args->param);
9557692c94SEric Anholt return -EINVAL;
9657692c94SEric Anholt }
971584f16cSEric Anholt }
9857692c94SEric Anholt
9957692c94SEric Anholt static int
v3d_open(struct drm_device * dev,struct drm_file * file)10057692c94SEric Anholt v3d_open(struct drm_device *dev, struct drm_file *file)
10157692c94SEric Anholt {
10257692c94SEric Anholt struct v3d_dev *v3d = to_v3d_dev(dev);
10357692c94SEric Anholt struct v3d_file_priv *v3d_priv;
104b3ac1766SNirmoy Das struct drm_gpu_scheduler *sched;
10557692c94SEric Anholt int i;
10657692c94SEric Anholt
10757692c94SEric Anholt v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL);
10857692c94SEric Anholt if (!v3d_priv)
10957692c94SEric Anholt return -ENOMEM;
11057692c94SEric Anholt
11157692c94SEric Anholt v3d_priv->v3d = v3d;
11257692c94SEric Anholt
11357692c94SEric Anholt for (i = 0; i < V3D_MAX_QUEUES; i++) {
114b3ac1766SNirmoy Das sched = &v3d->queue[i].sched;
115b3ac1766SNirmoy Das drm_sched_entity_init(&v3d_priv->sched_entity[i],
116b3ac1766SNirmoy Das DRM_SCHED_PRIORITY_NORMAL, &sched,
117b3ac1766SNirmoy Das 1, NULL);
11857692c94SEric Anholt }
11957692c94SEric Anholt
12026a4dc29SJuan A. Suarez Romero v3d_perfmon_open_file(v3d_priv);
12157692c94SEric Anholt file->driver_priv = v3d_priv;
12257692c94SEric Anholt
12357692c94SEric Anholt return 0;
12457692c94SEric Anholt }
12557692c94SEric Anholt
12657692c94SEric Anholt static void
v3d_postclose(struct drm_device * dev,struct drm_file * file)12757692c94SEric Anholt v3d_postclose(struct drm_device *dev, struct drm_file *file)
12857692c94SEric Anholt {
12957692c94SEric Anholt struct v3d_file_priv *v3d_priv = file->driver_priv;
13057692c94SEric Anholt enum v3d_queue q;
13157692c94SEric Anholt
132e4165ae8SMelissa Wen for (q = 0; q < V3D_MAX_QUEUES; q++)
133cdc50176SNayan Deshmukh drm_sched_entity_destroy(&v3d_priv->sched_entity[q]);
13457692c94SEric Anholt
13526a4dc29SJuan A. Suarez Romero v3d_perfmon_close_file(v3d_priv);
13657692c94SEric Anholt kfree(v3d_priv);
13757692c94SEric Anholt }
13857692c94SEric Anholt
139eee9a2e0SGerd Hoffmann DEFINE_DRM_GEM_FOPS(v3d_drm_fops);
14057692c94SEric Anholt
14157692c94SEric Anholt /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP
142bb3425efSMelissa Wen * protection between clients. Note that render nodes would be
14357692c94SEric Anholt * able to submit CLs that could access BOs from clients authenticated
1441584f16cSEric Anholt * with the master node. The TFU doesn't use the GMP, so it would
1451584f16cSEric Anholt * need to stay DRM_AUTH until we do buffer size/offset validation.
14657692c94SEric Anholt */
14757692c94SEric Anholt static const struct drm_ioctl_desc v3d_drm_ioctls[] = {
14857692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
14957692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW),
15057692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW),
15157692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW),
15257692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW),
15357692c94SEric Anholt DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW),
1541584f16cSEric Anholt DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
155d223f98fSEric Anholt DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
15626a4dc29SJuan A. Suarez Romero DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW),
15726a4dc29SJuan A. Suarez Romero DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW),
15826a4dc29SJuan A. Suarez Romero DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW),
15957692c94SEric Anholt };
16057692c94SEric Anholt
16170a59dd8SDaniel Vetter static const struct drm_driver v3d_drm_driver = {
16257692c94SEric Anholt .driver_features = (DRIVER_GEM |
16357692c94SEric Anholt DRIVER_RENDER |
16457692c94SEric Anholt DRIVER_SYNCOBJ),
16557692c94SEric Anholt
16657692c94SEric Anholt .open = v3d_open,
16757692c94SEric Anholt .postclose = v3d_postclose,
16857692c94SEric Anholt
16957692c94SEric Anholt #if defined(CONFIG_DEBUG_FS)
17057692c94SEric Anholt .debugfs_init = v3d_debugfs_init,
17157692c94SEric Anholt #endif
17257692c94SEric Anholt
17340609d48SEric Anholt .gem_create_object = v3d_create_object,
17457692c94SEric Anholt .gem_prime_import_sg_table = v3d_prime_import_sg_table,
17557692c94SEric Anholt
17657692c94SEric Anholt .ioctls = v3d_drm_ioctls,
17757692c94SEric Anholt .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls),
17857692c94SEric Anholt .fops = &v3d_drm_fops,
17957692c94SEric Anholt
18057692c94SEric Anholt .name = DRIVER_NAME,
18157692c94SEric Anholt .desc = DRIVER_DESC,
18257692c94SEric Anholt .date = DRIVER_DATE,
18357692c94SEric Anholt .major = DRIVER_MAJOR,
18457692c94SEric Anholt .minor = DRIVER_MINOR,
18557692c94SEric Anholt .patchlevel = DRIVER_PATCHLEVEL,
18657692c94SEric Anholt };
18757692c94SEric Anholt
18857692c94SEric Anholt static const struct of_device_id v3d_of_match[] = {
189e5a06898SPeter Robinson { .compatible = "brcm,2711-v3d" },
19057692c94SEric Anholt { .compatible = "brcm,7268-v3d" },
19157692c94SEric Anholt { .compatible = "brcm,7278-v3d" },
19257692c94SEric Anholt {},
19357692c94SEric Anholt };
19457692c94SEric Anholt MODULE_DEVICE_TABLE(of, v3d_of_match);
19557692c94SEric Anholt
19657692c94SEric Anholt static int
map_regs(struct v3d_dev * v3d,void __iomem ** regs,const char * name)19757692c94SEric Anholt map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)
19857692c94SEric Anholt {
199c3c7d70bSCai Huoqing *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name);
20057692c94SEric Anholt return PTR_ERR_OR_ZERO(*regs);
20157692c94SEric Anholt }
20257692c94SEric Anholt
v3d_platform_drm_probe(struct platform_device * pdev)20357692c94SEric Anholt static int v3d_platform_drm_probe(struct platform_device *pdev)
20457692c94SEric Anholt {
20557692c94SEric Anholt struct device *dev = &pdev->dev;
20657692c94SEric Anholt struct drm_device *drm;
20757692c94SEric Anholt struct v3d_dev *v3d;
20857692c94SEric Anholt int ret;
209091d6283SEric Anholt u32 mmu_debug;
21057692c94SEric Anholt u32 ident1;
2114a391561SJiasheng Jiang u64 mask;
21257692c94SEric Anholt
213235b7e7dSDaniel Vetter v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm);
214235b7e7dSDaniel Vetter if (IS_ERR(v3d))
215235b7e7dSDaniel Vetter return PTR_ERR(v3d);
216235b7e7dSDaniel Vetter
21757692c94SEric Anholt drm = &v3d->drm;
21857692c94SEric Anholt
219ea3aa620SDaniel Vetter platform_set_drvdata(pdev, drm);
220ea3aa620SDaniel Vetter
22157692c94SEric Anholt ret = map_regs(v3d, &v3d->hub_regs, "hub");
22257692c94SEric Anholt if (ret)
223235b7e7dSDaniel Vetter return ret;
22457692c94SEric Anholt
22557692c94SEric Anholt ret = map_regs(v3d, &v3d->core_regs[0], "core0");
22657692c94SEric Anholt if (ret)
227235b7e7dSDaniel Vetter return ret;
22857692c94SEric Anholt
229091d6283SEric Anholt mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
2304a391561SJiasheng Jiang mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
2314a391561SJiasheng Jiang ret = dma_set_mask_and_coherent(dev, mask);
2324a391561SJiasheng Jiang if (ret)
2334a391561SJiasheng Jiang return ret;
2344a391561SJiasheng Jiang
23538c2c791SEric Anholt v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);
236091d6283SEric Anholt
23757692c94SEric Anholt ident1 = V3D_READ(V3D_HUB_IDENT1);
23857692c94SEric Anholt v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
23957692c94SEric Anholt V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
24057692c94SEric Anholt v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
24157692c94SEric Anholt WARN_ON(v3d->cores > 1); /* multicore not yet implemented */
24257692c94SEric Anholt
243eea9b97bSEric Anholt v3d->reset = devm_reset_control_get_exclusive(dev, NULL);
244eea9b97bSEric Anholt if (IS_ERR(v3d->reset)) {
245eea9b97bSEric Anholt ret = PTR_ERR(v3d->reset);
246eea9b97bSEric Anholt
247eea9b97bSEric Anholt if (ret == -EPROBE_DEFER)
248235b7e7dSDaniel Vetter return ret;
249eea9b97bSEric Anholt
250eea9b97bSEric Anholt v3d->reset = NULL;
251eea9b97bSEric Anholt ret = map_regs(v3d, &v3d->bridge_regs, "bridge");
252eea9b97bSEric Anholt if (ret) {
253eea9b97bSEric Anholt dev_err(dev,
254eea9b97bSEric Anholt "Failed to get reset control or bridge regs\n");
255235b7e7dSDaniel Vetter return ret;
256eea9b97bSEric Anholt }
257eea9b97bSEric Anholt }
258eea9b97bSEric Anholt
25957692c94SEric Anholt if (v3d->ver < 41) {
26057692c94SEric Anholt ret = map_regs(v3d, &v3d->gca_regs, "gca");
26157692c94SEric Anholt if (ret)
262235b7e7dSDaniel Vetter return ret;
26357692c94SEric Anholt }
26457692c94SEric Anholt
26557692c94SEric Anholt v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr,
26657692c94SEric Anholt GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
26757692c94SEric Anholt if (!v3d->mmu_scratch) {
26857692c94SEric Anholt dev_err(dev, "Failed to allocate MMU scratch page\n");
269235b7e7dSDaniel Vetter return -ENOMEM;
27057692c94SEric Anholt }
27157692c94SEric Anholt
27257692c94SEric Anholt ret = v3d_gem_init(drm);
27357692c94SEric Anholt if (ret)
274ea3aa620SDaniel Vetter goto dma_free;
27557692c94SEric Anholt
276fc227715SEric Anholt ret = v3d_irq_init(v3d);
27757692c94SEric Anholt if (ret)
27857692c94SEric Anholt goto gem_destroy;
27957692c94SEric Anholt
280fc227715SEric Anholt ret = drm_dev_register(drm, 0);
281fc227715SEric Anholt if (ret)
282fc227715SEric Anholt goto irq_disable;
283fc227715SEric Anholt
28457692c94SEric Anholt return 0;
28557692c94SEric Anholt
286fc227715SEric Anholt irq_disable:
287fc227715SEric Anholt v3d_irq_disable(v3d);
28857692c94SEric Anholt gem_destroy:
28957692c94SEric Anholt v3d_gem_destroy(drm);
29057692c94SEric Anholt dma_free:
29157692c94SEric Anholt dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
29257692c94SEric Anholt return ret;
29357692c94SEric Anholt }
29457692c94SEric Anholt
v3d_platform_drm_remove(struct platform_device * pdev)295*b9578128SUwe Kleine-König static void v3d_platform_drm_remove(struct platform_device *pdev)
29657692c94SEric Anholt {
29757692c94SEric Anholt struct drm_device *drm = platform_get_drvdata(pdev);
29857692c94SEric Anholt struct v3d_dev *v3d = to_v3d_dev(drm);
29957692c94SEric Anholt
30057692c94SEric Anholt drm_dev_unregister(drm);
30157692c94SEric Anholt
30257692c94SEric Anholt v3d_gem_destroy(drm);
30357692c94SEric Anholt
304bc662528SDaniel Vetter dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch,
305bc662528SDaniel Vetter v3d->mmu_scratch_paddr);
30657692c94SEric Anholt }
30757692c94SEric Anholt
30857692c94SEric Anholt static struct platform_driver v3d_platform_driver = {
30957692c94SEric Anholt .probe = v3d_platform_drm_probe,
310*b9578128SUwe Kleine-König .remove_new = v3d_platform_drm_remove,
31157692c94SEric Anholt .driver = {
31257692c94SEric Anholt .name = "v3d",
31357692c94SEric Anholt .of_match_table = v3d_of_match,
31457692c94SEric Anholt },
31557692c94SEric Anholt };
31657692c94SEric Anholt
317ad28cd69SQinglang Miao module_platform_driver(v3d_platform_driver);
31857692c94SEric Anholt
31957692c94SEric Anholt MODULE_ALIAS("platform:v3d-drm");
32057692c94SEric Anholt MODULE_DESCRIPTION("Broadcom V3D DRM Driver");
32157692c94SEric Anholt MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
32257692c94SEric Anholt MODULE_LICENSE("GPL v2");
323