132a1795fSJyri Sarha /* SPDX-License-Identifier: GPL-2.0 */
232a1795fSJyri Sarha /*
39410113fSAlexander A. Klimov * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
432a1795fSJyri Sarha * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
532a1795fSJyri Sarha */
632a1795fSJyri Sarha
732a1795fSJyri Sarha #ifndef __TIDSS_IRQ_H__
832a1795fSJyri Sarha #define __TIDSS_IRQ_H__
932a1795fSJyri Sarha
1032a1795fSJyri Sarha #include <linux/types.h>
1132a1795fSJyri Sarha
1232a1795fSJyri Sarha #include "tidss_drv.h"
1332a1795fSJyri Sarha
1432a1795fSJyri Sarha /*
1532a1795fSJyri Sarha * The IRQ status from various DISPC IRQ registers are packed into a single
1632a1795fSJyri Sarha * value, where the bits are defined as follows:
1732a1795fSJyri Sarha *
1832a1795fSJyri Sarha * bit group |dev|wb |mrg0|mrg1|mrg2|mrg3|plane0-3| <unused> |
1932a1795fSJyri Sarha * bit use |D |fou|FEOL|FEOL|FEOL|FEOL| UUUU | |
2032a1795fSJyri Sarha * bit number|0 |1-3|4-7 |8-11| 12-19 | 20-23 | 24-31 |
2132a1795fSJyri Sarha *
2232a1795fSJyri Sarha * device bits: D = OCP error
2332a1795fSJyri Sarha * WB bits: f = frame done wb, o = wb buffer overflow,
2432a1795fSJyri Sarha * u = wb buffer uncomplete
2532a1795fSJyri Sarha * vp bits: F = frame done, E = vsync even, O = vsync odd, L = sync lost
2632a1795fSJyri Sarha * plane bits: U = fifo underflow
2732a1795fSJyri Sarha */
2832a1795fSJyri Sarha
2932a1795fSJyri Sarha #define DSS_IRQ_DEVICE_OCP_ERR BIT(0)
3032a1795fSJyri Sarha
3132a1795fSJyri Sarha #define DSS_IRQ_DEVICE_FRAMEDONEWB BIT(1)
3232a1795fSJyri Sarha #define DSS_IRQ_DEVICE_WBBUFFEROVERFLOW BIT(2)
3332a1795fSJyri Sarha #define DSS_IRQ_DEVICE_WBUNCOMPLETEERROR BIT(3)
3432a1795fSJyri Sarha #define DSS_IRQ_DEVICE_WB_MASK GENMASK(3, 1)
3532a1795fSJyri Sarha
3632a1795fSJyri Sarha #define DSS_IRQ_VP_BIT_N(ch, bit) (4 + 4 * (ch) + (bit))
3732a1795fSJyri Sarha #define DSS_IRQ_PLANE_BIT_N(plane, bit) \
3832a1795fSJyri Sarha (DSS_IRQ_VP_BIT_N(TIDSS_MAX_PORTS, 0) + 1 * (plane) + (bit))
3932a1795fSJyri Sarha
4032a1795fSJyri Sarha #define DSS_IRQ_VP_BIT(ch, bit) BIT(DSS_IRQ_VP_BIT_N((ch), (bit)))
4132a1795fSJyri Sarha #define DSS_IRQ_PLANE_BIT(plane, bit) \
4232a1795fSJyri Sarha BIT(DSS_IRQ_PLANE_BIT_N((plane), (bit)))
4332a1795fSJyri Sarha
DSS_IRQ_VP_MASK(u32 ch)4432a1795fSJyri Sarha static inline dispc_irq_t DSS_IRQ_VP_MASK(u32 ch)
4532a1795fSJyri Sarha {
4632a1795fSJyri Sarha return GENMASK(DSS_IRQ_VP_BIT_N((ch), 3), DSS_IRQ_VP_BIT_N((ch), 0));
4732a1795fSJyri Sarha }
4832a1795fSJyri Sarha
DSS_IRQ_PLANE_MASK(u32 plane)4932a1795fSJyri Sarha static inline dispc_irq_t DSS_IRQ_PLANE_MASK(u32 plane)
5032a1795fSJyri Sarha {
5132a1795fSJyri Sarha return GENMASK(DSS_IRQ_PLANE_BIT_N((plane), 0),
5232a1795fSJyri Sarha DSS_IRQ_PLANE_BIT_N((plane), 0));
5332a1795fSJyri Sarha }
5432a1795fSJyri Sarha
5532a1795fSJyri Sarha #define DSS_IRQ_VP_FRAME_DONE(ch) DSS_IRQ_VP_BIT((ch), 0)
5632a1795fSJyri Sarha #define DSS_IRQ_VP_VSYNC_EVEN(ch) DSS_IRQ_VP_BIT((ch), 1)
5732a1795fSJyri Sarha #define DSS_IRQ_VP_VSYNC_ODD(ch) DSS_IRQ_VP_BIT((ch), 2)
5832a1795fSJyri Sarha #define DSS_IRQ_VP_SYNC_LOST(ch) DSS_IRQ_VP_BIT((ch), 3)
5932a1795fSJyri Sarha
6032a1795fSJyri Sarha #define DSS_IRQ_PLANE_FIFO_UNDERFLOW(plane) DSS_IRQ_PLANE_BIT((plane), 0)
6132a1795fSJyri Sarha
6232a1795fSJyri Sarha struct drm_crtc;
6332a1795fSJyri Sarha struct drm_device;
6432a1795fSJyri Sarha
6532a1795fSJyri Sarha struct tidss_device;
6632a1795fSJyri Sarha
6732a1795fSJyri Sarha void tidss_irq_enable_vblank(struct drm_crtc *crtc);
6832a1795fSJyri Sarha void tidss_irq_disable_vblank(struct drm_crtc *crtc);
6932a1795fSJyri Sarha
70*5518572dSThomas Zimmermann int tidss_irq_install(struct drm_device *ddev, unsigned int irq);
7132a1795fSJyri Sarha void tidss_irq_uninstall(struct drm_device *ddev);
7232a1795fSJyri Sarha
7332a1795fSJyri Sarha void tidss_irq_resume(struct tidss_device *tidss);
7432a1795fSJyri Sarha
7532a1795fSJyri Sarha #endif
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