xref: /openbmc/linux/drivers/gpu/drm/tidss/tidss_crtc.h (revision 32a1795f57eecc3974901760400618571c9d357f)
1*32a1795fSJyri Sarha /* SPDX-License-Identifier: GPL-2.0 */
2*32a1795fSJyri Sarha /*
3*32a1795fSJyri Sarha  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
4*32a1795fSJyri Sarha  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5*32a1795fSJyri Sarha  */
6*32a1795fSJyri Sarha 
7*32a1795fSJyri Sarha #ifndef __TIDSS_CRTC_H__
8*32a1795fSJyri Sarha #define __TIDSS_CRTC_H__
9*32a1795fSJyri Sarha 
10*32a1795fSJyri Sarha #include <linux/completion.h>
11*32a1795fSJyri Sarha #include <linux/wait.h>
12*32a1795fSJyri Sarha 
13*32a1795fSJyri Sarha #include <drm/drm_crtc.h>
14*32a1795fSJyri Sarha 
15*32a1795fSJyri Sarha #define to_tidss_crtc(c) container_of((c), struct tidss_crtc, crtc)
16*32a1795fSJyri Sarha 
17*32a1795fSJyri Sarha struct tidss_device;
18*32a1795fSJyri Sarha 
19*32a1795fSJyri Sarha struct tidss_crtc {
20*32a1795fSJyri Sarha 	struct drm_crtc crtc;
21*32a1795fSJyri Sarha 
22*32a1795fSJyri Sarha 	u32 hw_videoport;
23*32a1795fSJyri Sarha 
24*32a1795fSJyri Sarha 	struct drm_pending_vblank_event *event;
25*32a1795fSJyri Sarha 
26*32a1795fSJyri Sarha 	struct completion framedone_completion;
27*32a1795fSJyri Sarha };
28*32a1795fSJyri Sarha 
29*32a1795fSJyri Sarha #define to_tidss_crtc_state(x) container_of(x, struct tidss_crtc_state, base)
30*32a1795fSJyri Sarha 
31*32a1795fSJyri Sarha struct tidss_crtc_state {
32*32a1795fSJyri Sarha 	/* Must be first. */
33*32a1795fSJyri Sarha 	struct drm_crtc_state base;
34*32a1795fSJyri Sarha 
35*32a1795fSJyri Sarha 	u32 bus_format;
36*32a1795fSJyri Sarha 	u32 bus_flags;
37*32a1795fSJyri Sarha };
38*32a1795fSJyri Sarha 
39*32a1795fSJyri Sarha void tidss_crtc_vblank_irq(struct drm_crtc *crtc);
40*32a1795fSJyri Sarha void tidss_crtc_framedone_irq(struct drm_crtc *crtc);
41*32a1795fSJyri Sarha void tidss_crtc_error_irq(struct drm_crtc *crtc, u64 irqstatus);
42*32a1795fSJyri Sarha 
43*32a1795fSJyri Sarha struct tidss_crtc *tidss_crtc_create(struct tidss_device *tidss,
44*32a1795fSJyri Sarha 				     u32 hw_videoport,
45*32a1795fSJyri Sarha 				     struct drm_plane *primary);
46*32a1795fSJyri Sarha #endif
47