1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, NVIDIA Corporation. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/host1x.h> 9 #include <linux/iommu.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/reset.h> 17 18 #include <soc/tegra/pmc.h> 19 20 #include "drm.h" 21 #include "falcon.h" 22 #include "vic.h" 23 24 struct vic_config { 25 const char *firmware; 26 unsigned int version; 27 bool supports_sid; 28 }; 29 30 struct vic { 31 struct falcon falcon; 32 bool booted; 33 34 void __iomem *regs; 35 struct tegra_drm_client client; 36 struct host1x_channel *channel; 37 struct device *dev; 38 struct clk *clk; 39 struct reset_control *rst; 40 41 /* Platform configuration */ 42 const struct vic_config *config; 43 }; 44 45 static inline struct vic *to_vic(struct tegra_drm_client *client) 46 { 47 return container_of(client, struct vic, client); 48 } 49 50 static void vic_writel(struct vic *vic, u32 value, unsigned int offset) 51 { 52 writel(value, vic->regs + offset); 53 } 54 55 static int vic_runtime_resume(struct device *dev) 56 { 57 struct vic *vic = dev_get_drvdata(dev); 58 int err; 59 60 err = clk_prepare_enable(vic->clk); 61 if (err < 0) 62 return err; 63 64 usleep_range(10, 20); 65 66 err = reset_control_deassert(vic->rst); 67 if (err < 0) 68 goto disable; 69 70 usleep_range(10, 20); 71 72 return 0; 73 74 disable: 75 clk_disable_unprepare(vic->clk); 76 return err; 77 } 78 79 static int vic_runtime_suspend(struct device *dev) 80 { 81 struct vic *vic = dev_get_drvdata(dev); 82 int err; 83 84 err = reset_control_assert(vic->rst); 85 if (err < 0) 86 return err; 87 88 usleep_range(2000, 4000); 89 90 clk_disable_unprepare(vic->clk); 91 92 vic->booted = false; 93 94 return 0; 95 } 96 97 static int vic_boot(struct vic *vic) 98 { 99 #ifdef CONFIG_IOMMU_API 100 struct iommu_fwspec *spec = dev_iommu_fwspec_get(vic->dev); 101 #endif 102 u32 fce_ucode_size, fce_bin_data_offset; 103 void *hdr; 104 int err = 0; 105 106 if (vic->booted) 107 return 0; 108 109 #ifdef CONFIG_IOMMU_API 110 if (vic->config->supports_sid && spec) { 111 u32 value; 112 113 value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | 114 TRANSCFG_ATT(0, TRANSCFG_SID_HW); 115 vic_writel(vic, value, VIC_TFBIF_TRANSCFG); 116 117 if (spec->num_ids > 0) { 118 value = spec->ids[0] & 0xffff; 119 120 vic_writel(vic, value, VIC_THI_STREAMID0); 121 vic_writel(vic, value, VIC_THI_STREAMID1); 122 } 123 } 124 #endif 125 126 /* setup clockgating registers */ 127 vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) | 128 CG_IDLE_CG_EN | 129 CG_WAKEUP_DLY_CNT(4), 130 NV_PVIC_MISC_PRI_VIC_CG); 131 132 err = falcon_boot(&vic->falcon); 133 if (err < 0) 134 return err; 135 136 hdr = vic->falcon.firmware.vaddr; 137 fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET); 138 hdr = vic->falcon.firmware.vaddr + 139 *(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET); 140 fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET); 141 142 falcon_execute_method(&vic->falcon, VIC_SET_APPLICATION_ID, 1); 143 falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE, 144 fce_ucode_size); 145 falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_OFFSET, 146 (vic->falcon.firmware.paddr + fce_bin_data_offset) 147 >> 8); 148 149 err = falcon_wait_idle(&vic->falcon); 150 if (err < 0) { 151 dev_err(vic->dev, 152 "failed to set application ID and FCE base\n"); 153 return err; 154 } 155 156 vic->booted = true; 157 158 return 0; 159 } 160 161 static void *vic_falcon_alloc(struct falcon *falcon, size_t size, 162 dma_addr_t *iova) 163 { 164 struct tegra_drm *tegra = falcon->data; 165 166 return tegra_drm_alloc(tegra, size, iova); 167 } 168 169 static void vic_falcon_free(struct falcon *falcon, size_t size, 170 dma_addr_t iova, void *va) 171 { 172 struct tegra_drm *tegra = falcon->data; 173 174 return tegra_drm_free(tegra, size, va, iova); 175 } 176 177 static const struct falcon_ops vic_falcon_ops = { 178 .alloc = vic_falcon_alloc, 179 .free = vic_falcon_free 180 }; 181 182 static int vic_init(struct host1x_client *client) 183 { 184 struct tegra_drm_client *drm = host1x_to_drm_client(client); 185 struct drm_device *dev = dev_get_drvdata(client->parent); 186 struct tegra_drm *tegra = dev->dev_private; 187 struct vic *vic = to_vic(drm); 188 int err; 189 190 err = host1x_client_iommu_attach(client, false); 191 if (err < 0) { 192 dev_err(vic->dev, "failed to attach to domain: %d\n", err); 193 return err; 194 } 195 196 vic->channel = host1x_channel_request(client); 197 if (!vic->channel) { 198 err = -ENOMEM; 199 goto detach; 200 } 201 202 client->syncpts[0] = host1x_syncpt_request(client, 0); 203 if (!client->syncpts[0]) { 204 err = -ENOMEM; 205 goto free_channel; 206 } 207 208 err = tegra_drm_register_client(tegra, drm); 209 if (err < 0) 210 goto free_syncpt; 211 212 /* 213 * Inherit the DMA parameters (such as maximum segment size) from the 214 * parent device. 215 */ 216 client->dev->dma_parms = client->parent->dma_parms; 217 218 return 0; 219 220 free_syncpt: 221 host1x_syncpt_free(client->syncpts[0]); 222 free_channel: 223 host1x_channel_put(vic->channel); 224 detach: 225 host1x_client_iommu_detach(client); 226 227 return err; 228 } 229 230 static int vic_exit(struct host1x_client *client) 231 { 232 struct tegra_drm_client *drm = host1x_to_drm_client(client); 233 struct drm_device *dev = dev_get_drvdata(client->parent); 234 struct tegra_drm *tegra = dev->dev_private; 235 struct vic *vic = to_vic(drm); 236 int err; 237 238 /* avoid a dangling pointer just in case this disappears */ 239 client->dev->dma_parms = NULL; 240 241 err = tegra_drm_unregister_client(tegra, drm); 242 if (err < 0) 243 return err; 244 245 host1x_syncpt_free(client->syncpts[0]); 246 host1x_channel_put(vic->channel); 247 host1x_client_iommu_detach(client); 248 249 return 0; 250 } 251 252 static const struct host1x_client_ops vic_client_ops = { 253 .init = vic_init, 254 .exit = vic_exit, 255 }; 256 257 static int vic_load_firmware(struct vic *vic) 258 { 259 int err; 260 261 if (vic->falcon.data) 262 return 0; 263 264 vic->falcon.data = vic->client.drm; 265 266 err = falcon_read_firmware(&vic->falcon, vic->config->firmware); 267 if (err < 0) 268 goto cleanup; 269 270 err = falcon_load_firmware(&vic->falcon); 271 if (err < 0) 272 goto cleanup; 273 274 return 0; 275 276 cleanup: 277 vic->falcon.data = NULL; 278 return err; 279 } 280 281 static int vic_open_channel(struct tegra_drm_client *client, 282 struct tegra_drm_context *context) 283 { 284 struct vic *vic = to_vic(client); 285 int err; 286 287 err = pm_runtime_get_sync(vic->dev); 288 if (err < 0) 289 return err; 290 291 err = vic_load_firmware(vic); 292 if (err < 0) 293 goto rpm_put; 294 295 err = vic_boot(vic); 296 if (err < 0) 297 goto rpm_put; 298 299 context->channel = host1x_channel_get(vic->channel); 300 if (!context->channel) { 301 err = -ENOMEM; 302 goto rpm_put; 303 } 304 305 return 0; 306 307 rpm_put: 308 pm_runtime_put(vic->dev); 309 return err; 310 } 311 312 static void vic_close_channel(struct tegra_drm_context *context) 313 { 314 struct vic *vic = to_vic(context->client); 315 316 host1x_channel_put(context->channel); 317 318 pm_runtime_put(vic->dev); 319 } 320 321 static const struct tegra_drm_client_ops vic_ops = { 322 .open_channel = vic_open_channel, 323 .close_channel = vic_close_channel, 324 .submit = tegra_drm_submit, 325 }; 326 327 #define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin" 328 329 static const struct vic_config vic_t124_config = { 330 .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE, 331 .version = 0x40, 332 .supports_sid = false, 333 }; 334 335 #define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin" 336 337 static const struct vic_config vic_t210_config = { 338 .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE, 339 .version = 0x21, 340 .supports_sid = false, 341 }; 342 343 #define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin" 344 345 static const struct vic_config vic_t186_config = { 346 .firmware = NVIDIA_TEGRA_186_VIC_FIRMWARE, 347 .version = 0x18, 348 .supports_sid = true, 349 }; 350 351 #define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin" 352 353 static const struct vic_config vic_t194_config = { 354 .firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE, 355 .version = 0x19, 356 .supports_sid = true, 357 }; 358 359 static const struct of_device_id vic_match[] = { 360 { .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config }, 361 { .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config }, 362 { .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config }, 363 { .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config }, 364 { }, 365 }; 366 367 static int vic_probe(struct platform_device *pdev) 368 { 369 struct device *dev = &pdev->dev; 370 struct host1x_syncpt **syncpts; 371 struct resource *regs; 372 struct vic *vic; 373 int err; 374 375 /* inherit DMA mask from host1x parent */ 376 err = dma_coerce_mask_and_coherent(dev, *dev->parent->dma_mask); 377 if (err < 0) { 378 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 379 return err; 380 } 381 382 vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL); 383 if (!vic) 384 return -ENOMEM; 385 386 vic->config = of_device_get_match_data(dev); 387 388 syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL); 389 if (!syncpts) 390 return -ENOMEM; 391 392 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 393 if (!regs) { 394 dev_err(&pdev->dev, "failed to get registers\n"); 395 return -ENXIO; 396 } 397 398 vic->regs = devm_ioremap_resource(dev, regs); 399 if (IS_ERR(vic->regs)) 400 return PTR_ERR(vic->regs); 401 402 vic->clk = devm_clk_get(dev, NULL); 403 if (IS_ERR(vic->clk)) { 404 dev_err(&pdev->dev, "failed to get clock\n"); 405 return PTR_ERR(vic->clk); 406 } 407 408 if (!dev->pm_domain) { 409 vic->rst = devm_reset_control_get(dev, "vic"); 410 if (IS_ERR(vic->rst)) { 411 dev_err(&pdev->dev, "failed to get reset\n"); 412 return PTR_ERR(vic->rst); 413 } 414 } 415 416 vic->falcon.dev = dev; 417 vic->falcon.regs = vic->regs; 418 vic->falcon.ops = &vic_falcon_ops; 419 420 err = falcon_init(&vic->falcon); 421 if (err < 0) 422 return err; 423 424 platform_set_drvdata(pdev, vic); 425 426 INIT_LIST_HEAD(&vic->client.base.list); 427 vic->client.base.ops = &vic_client_ops; 428 vic->client.base.dev = dev; 429 vic->client.base.class = HOST1X_CLASS_VIC; 430 vic->client.base.syncpts = syncpts; 431 vic->client.base.num_syncpts = 1; 432 vic->dev = dev; 433 434 INIT_LIST_HEAD(&vic->client.list); 435 vic->client.version = vic->config->version; 436 vic->client.ops = &vic_ops; 437 438 err = host1x_client_register(&vic->client.base); 439 if (err < 0) { 440 dev_err(dev, "failed to register host1x client: %d\n", err); 441 goto exit_falcon; 442 } 443 444 pm_runtime_enable(&pdev->dev); 445 if (!pm_runtime_enabled(&pdev->dev)) { 446 err = vic_runtime_resume(&pdev->dev); 447 if (err < 0) 448 goto unregister_client; 449 } 450 451 return 0; 452 453 unregister_client: 454 host1x_client_unregister(&vic->client.base); 455 exit_falcon: 456 falcon_exit(&vic->falcon); 457 458 return err; 459 } 460 461 static int vic_remove(struct platform_device *pdev) 462 { 463 struct vic *vic = platform_get_drvdata(pdev); 464 int err; 465 466 err = host1x_client_unregister(&vic->client.base); 467 if (err < 0) { 468 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 469 err); 470 return err; 471 } 472 473 if (pm_runtime_enabled(&pdev->dev)) 474 pm_runtime_disable(&pdev->dev); 475 else 476 vic_runtime_suspend(&pdev->dev); 477 478 falcon_exit(&vic->falcon); 479 480 return 0; 481 } 482 483 static const struct dev_pm_ops vic_pm_ops = { 484 SET_RUNTIME_PM_OPS(vic_runtime_suspend, vic_runtime_resume, NULL) 485 }; 486 487 struct platform_driver tegra_vic_driver = { 488 .driver = { 489 .name = "tegra-vic", 490 .of_match_table = vic_match, 491 .pm = &vic_pm_ops 492 }, 493 .probe = vic_probe, 494 .remove = vic_remove, 495 }; 496 497 #if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) 498 MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE); 499 #endif 500 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) 501 MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE); 502 #endif 503 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) 504 MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE); 505 #endif 506 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) 507 MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE); 508 #endif 509