1 /* 2 * Copyright (C) 2013 NVIDIA Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/debugfs.h> 11 #include <linux/io.h> 12 #include <linux/platform_device.h> 13 #include <linux/reset.h> 14 #include <linux/tegra-powergate.h> 15 16 #include <drm/drm_dp_helper.h> 17 18 #include "dc.h" 19 #include "drm.h" 20 #include "sor.h" 21 22 struct tegra_sor { 23 struct host1x_client client; 24 struct tegra_output output; 25 struct device *dev; 26 27 void __iomem *regs; 28 29 struct reset_control *rst; 30 struct clk *clk_parent; 31 struct clk *clk_safe; 32 struct clk *clk_dp; 33 struct clk *clk; 34 35 struct tegra_dpaux *dpaux; 36 37 struct mutex lock; 38 bool enabled; 39 40 struct dentry *debugfs; 41 }; 42 43 static inline struct tegra_sor * 44 host1x_client_to_sor(struct host1x_client *client) 45 { 46 return container_of(client, struct tegra_sor, client); 47 } 48 49 static inline struct tegra_sor *to_sor(struct tegra_output *output) 50 { 51 return container_of(output, struct tegra_sor, output); 52 } 53 54 static inline unsigned long tegra_sor_readl(struct tegra_sor *sor, 55 unsigned long offset) 56 { 57 return readl(sor->regs + (offset << 2)); 58 } 59 60 static inline void tegra_sor_writel(struct tegra_sor *sor, unsigned long value, 61 unsigned long offset) 62 { 63 writel(value, sor->regs + (offset << 2)); 64 } 65 66 static int tegra_sor_dp_train_fast(struct tegra_sor *sor, 67 struct drm_dp_link *link) 68 { 69 unsigned long value; 70 unsigned int i; 71 u8 pattern; 72 int err; 73 74 /* setup lane parameters */ 75 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | 76 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) | 77 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) | 78 SOR_LANE_DRIVE_CURRENT_LANE0(0x40); 79 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT_0); 80 81 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | 82 SOR_LANE_PREEMPHASIS_LANE2(0x0f) | 83 SOR_LANE_PREEMPHASIS_LANE1(0x0f) | 84 SOR_LANE_PREEMPHASIS_LANE0(0x0f); 85 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS_0); 86 87 value = SOR_LANE_POST_CURSOR_LANE3(0x00) | 88 SOR_LANE_POST_CURSOR_LANE2(0x00) | 89 SOR_LANE_POST_CURSOR_LANE1(0x00) | 90 SOR_LANE_POST_CURSOR_LANE0(0x00); 91 tegra_sor_writel(sor, value, SOR_LANE_POST_CURSOR_0); 92 93 /* disable LVDS mode */ 94 tegra_sor_writel(sor, 0, SOR_LVDS); 95 96 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 97 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 98 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 99 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ 100 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 101 102 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 103 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 104 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; 105 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 106 107 usleep_range(10, 100); 108 109 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 110 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 111 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); 112 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 113 114 err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B); 115 if (err < 0) 116 return err; 117 118 for (i = 0, value = 0; i < link->num_lanes; i++) { 119 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 120 SOR_DP_TPG_SCRAMBLER_NONE | 121 SOR_DP_TPG_PATTERN_TRAIN1; 122 value = (value << 8) | lane; 123 } 124 125 tegra_sor_writel(sor, value, SOR_DP_TPG); 126 127 pattern = DP_TRAINING_PATTERN_1; 128 129 err = tegra_dpaux_train(sor->dpaux, link, pattern); 130 if (err < 0) 131 return err; 132 133 value = tegra_sor_readl(sor, SOR_DP_SPARE_0); 134 value |= SOR_DP_SPARE_SEQ_ENABLE; 135 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 136 value |= SOR_DP_SPARE_MACRO_SOR_CLK; 137 tegra_sor_writel(sor, value, SOR_DP_SPARE_0); 138 139 for (i = 0, value = 0; i < link->num_lanes; i++) { 140 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 141 SOR_DP_TPG_SCRAMBLER_NONE | 142 SOR_DP_TPG_PATTERN_TRAIN2; 143 value = (value << 8) | lane; 144 } 145 146 tegra_sor_writel(sor, value, SOR_DP_TPG); 147 148 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2; 149 150 err = tegra_dpaux_train(sor->dpaux, link, pattern); 151 if (err < 0) 152 return err; 153 154 for (i = 0, value = 0; i < link->num_lanes; i++) { 155 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 156 SOR_DP_TPG_SCRAMBLER_GALIOS | 157 SOR_DP_TPG_PATTERN_NONE; 158 value = (value << 8) | lane; 159 } 160 161 tegra_sor_writel(sor, value, SOR_DP_TPG); 162 163 pattern = DP_TRAINING_PATTERN_DISABLE; 164 165 err = tegra_dpaux_train(sor->dpaux, link, pattern); 166 if (err < 0) 167 return err; 168 169 return 0; 170 } 171 172 static void tegra_sor_super_update(struct tegra_sor *sor) 173 { 174 tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0); 175 tegra_sor_writel(sor, 1, SOR_SUPER_STATE_0); 176 tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0); 177 } 178 179 static void tegra_sor_update(struct tegra_sor *sor) 180 { 181 tegra_sor_writel(sor, 0, SOR_STATE_0); 182 tegra_sor_writel(sor, 1, SOR_STATE_0); 183 tegra_sor_writel(sor, 0, SOR_STATE_0); 184 } 185 186 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) 187 { 188 unsigned long value; 189 190 value = tegra_sor_readl(sor, SOR_PWM_DIV); 191 value &= ~SOR_PWM_DIV_MASK; 192 value |= 0x400; /* period */ 193 tegra_sor_writel(sor, value, SOR_PWM_DIV); 194 195 value = tegra_sor_readl(sor, SOR_PWM_CTL); 196 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; 197 value |= 0x400; /* duty cycle */ 198 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ 199 value |= SOR_PWM_CTL_TRIGGER; 200 tegra_sor_writel(sor, value, SOR_PWM_CTL); 201 202 timeout = jiffies + msecs_to_jiffies(timeout); 203 204 while (time_before(jiffies, timeout)) { 205 value = tegra_sor_readl(sor, SOR_PWM_CTL); 206 if ((value & SOR_PWM_CTL_TRIGGER) == 0) 207 return 0; 208 209 usleep_range(25, 100); 210 } 211 212 return -ETIMEDOUT; 213 } 214 215 static int tegra_sor_attach(struct tegra_sor *sor) 216 { 217 unsigned long value, timeout; 218 219 /* wake up in normal mode */ 220 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 221 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; 222 value |= SOR_SUPER_STATE_MODE_NORMAL; 223 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 224 tegra_sor_super_update(sor); 225 226 /* attach */ 227 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 228 value |= SOR_SUPER_STATE_ATTACHED; 229 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 230 tegra_sor_super_update(sor); 231 232 timeout = jiffies + msecs_to_jiffies(250); 233 234 while (time_before(jiffies, timeout)) { 235 value = tegra_sor_readl(sor, SOR_TEST); 236 if ((value & SOR_TEST_ATTACHED) != 0) 237 return 0; 238 239 usleep_range(25, 100); 240 } 241 242 return -ETIMEDOUT; 243 } 244 245 static int tegra_sor_wakeup(struct tegra_sor *sor) 246 { 247 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); 248 unsigned long value, timeout; 249 250 /* enable display controller outputs */ 251 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 252 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 253 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; 254 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 255 256 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 257 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 258 259 timeout = jiffies + msecs_to_jiffies(250); 260 261 /* wait for head to wake up */ 262 while (time_before(jiffies, timeout)) { 263 value = tegra_sor_readl(sor, SOR_TEST); 264 value &= SOR_TEST_HEAD_MODE_MASK; 265 266 if (value == SOR_TEST_HEAD_MODE_AWAKE) 267 return 0; 268 269 usleep_range(25, 100); 270 } 271 272 return -ETIMEDOUT; 273 } 274 275 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) 276 { 277 unsigned long value; 278 279 value = tegra_sor_readl(sor, SOR_PWR); 280 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; 281 tegra_sor_writel(sor, value, SOR_PWR); 282 283 timeout = jiffies + msecs_to_jiffies(timeout); 284 285 while (time_before(jiffies, timeout)) { 286 value = tegra_sor_readl(sor, SOR_PWR); 287 if ((value & SOR_PWR_TRIGGER) == 0) 288 return 0; 289 290 usleep_range(25, 100); 291 } 292 293 return -ETIMEDOUT; 294 } 295 296 static int tegra_output_sor_enable(struct tegra_output *output) 297 { 298 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); 299 struct drm_display_mode *mode = &dc->base.mode; 300 unsigned int vbe, vse, hbe, hse, vbs, hbs, i; 301 struct tegra_sor *sor = to_sor(output); 302 unsigned long value; 303 int err = 0; 304 305 mutex_lock(&sor->lock); 306 307 if (sor->enabled) 308 goto unlock; 309 310 err = clk_prepare_enable(sor->clk); 311 if (err < 0) 312 goto unlock; 313 314 reset_control_deassert(sor->rst); 315 316 if (sor->dpaux) { 317 err = tegra_dpaux_enable(sor->dpaux); 318 if (err < 0) 319 dev_err(sor->dev, "failed to enable DP: %d\n", err); 320 } 321 322 err = clk_set_parent(sor->clk, sor->clk_safe); 323 if (err < 0) 324 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 325 326 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 327 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 328 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 329 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 330 331 value = tegra_sor_readl(sor, SOR_PLL_2); 332 value &= ~SOR_PLL_2_BANDGAP_POWERDOWN; 333 tegra_sor_writel(sor, value, SOR_PLL_2); 334 usleep_range(20, 100); 335 336 value = tegra_sor_readl(sor, SOR_PLL_3); 337 value |= SOR_PLL_3_PLL_VDD_MODE_V3_3; 338 tegra_sor_writel(sor, value, SOR_PLL_3); 339 340 value = SOR_PLL_0_ICHPMP(0xf) | SOR_PLL_0_VCOCAP_RST | 341 SOR_PLL_0_PLLREG_LEVEL_V45 | SOR_PLL_0_RESISTOR_EXT; 342 tegra_sor_writel(sor, value, SOR_PLL_0); 343 344 value = tegra_sor_readl(sor, SOR_PLL_2); 345 value |= SOR_PLL_2_SEQ_PLLCAPPD; 346 value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; 347 value |= SOR_PLL_2_LVDS_ENABLE; 348 tegra_sor_writel(sor, value, SOR_PLL_2); 349 350 value = SOR_PLL_1_TERM_COMPOUT | SOR_PLL_1_TMDS_TERM; 351 tegra_sor_writel(sor, value, SOR_PLL_1); 352 353 while (true) { 354 value = tegra_sor_readl(sor, SOR_PLL_2); 355 if ((value & SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE) == 0) 356 break; 357 358 usleep_range(250, 1000); 359 } 360 361 value = tegra_sor_readl(sor, SOR_PLL_2); 362 value &= ~SOR_PLL_2_POWERDOWN_OVERRIDE; 363 value &= ~SOR_PLL_2_PORT_POWERDOWN; 364 tegra_sor_writel(sor, value, SOR_PLL_2); 365 366 /* 367 * power up 368 */ 369 370 /* set safe link bandwidth (1.62 Gbps) */ 371 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 372 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 373 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; 374 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 375 376 /* step 1 */ 377 value = tegra_sor_readl(sor, SOR_PLL_2); 378 value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL_2_PORT_POWERDOWN | 379 SOR_PLL_2_BANDGAP_POWERDOWN; 380 tegra_sor_writel(sor, value, SOR_PLL_2); 381 382 value = tegra_sor_readl(sor, SOR_PLL_0); 383 value |= SOR_PLL_0_VCOPD | SOR_PLL_0_POWER_OFF; 384 tegra_sor_writel(sor, value, SOR_PLL_0); 385 386 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 387 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 388 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 389 390 /* step 2 */ 391 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); 392 if (err < 0) { 393 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err); 394 goto unlock; 395 } 396 397 usleep_range(5, 100); 398 399 /* step 3 */ 400 value = tegra_sor_readl(sor, SOR_PLL_2); 401 value &= ~SOR_PLL_2_BANDGAP_POWERDOWN; 402 tegra_sor_writel(sor, value, SOR_PLL_2); 403 404 usleep_range(20, 100); 405 406 /* step 4 */ 407 value = tegra_sor_readl(sor, SOR_PLL_0); 408 value &= ~SOR_PLL_0_POWER_OFF; 409 value &= ~SOR_PLL_0_VCOPD; 410 tegra_sor_writel(sor, value, SOR_PLL_0); 411 412 value = tegra_sor_readl(sor, SOR_PLL_2); 413 value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; 414 tegra_sor_writel(sor, value, SOR_PLL_2); 415 416 usleep_range(200, 1000); 417 418 /* step 5 */ 419 value = tegra_sor_readl(sor, SOR_PLL_2); 420 value &= ~SOR_PLL_2_PORT_POWERDOWN; 421 tegra_sor_writel(sor, value, SOR_PLL_2); 422 423 /* switch to DP clock */ 424 err = clk_set_parent(sor->clk, sor->clk_dp); 425 if (err < 0) 426 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err); 427 428 /* power dplanes (XXX parameterize based on link?) */ 429 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 430 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 431 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; 432 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 433 434 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); 435 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 436 value |= SOR_DP_LINKCTL_LANE_COUNT(4); 437 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); 438 439 /* start lane sequencer */ 440 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 441 SOR_LANE_SEQ_CTL_POWER_STATE_UP; 442 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 443 444 while (true) { 445 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 446 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 447 break; 448 449 usleep_range(250, 1000); 450 } 451 452 /* set link bandwidth (2.7 GHz, XXX: parameterize based on link?) */ 453 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 454 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 455 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; 456 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 457 458 /* set linkctl */ 459 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); 460 value |= SOR_DP_LINKCTL_ENABLE; 461 462 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; 463 value |= SOR_DP_LINKCTL_TU_SIZE(59); /* XXX: don't hardcode? */ 464 465 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 466 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); 467 468 for (i = 0, value = 0; i < 4; i++) { 469 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 470 SOR_DP_TPG_SCRAMBLER_GALIOS | 471 SOR_DP_TPG_PATTERN_NONE; 472 value = (value << 8) | lane; 473 } 474 475 tegra_sor_writel(sor, value, SOR_DP_TPG); 476 477 value = tegra_sor_readl(sor, SOR_DP_CONFIG_0); 478 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; 479 value |= SOR_DP_CONFIG_WATERMARK(14); /* XXX: don't hardcode? */ 480 481 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; 482 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(47); /* XXX: don't hardcode? */ 483 484 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; 485 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(9); /* XXX: don't hardcode? */ 486 487 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; /* XXX: don't hardcode? */ 488 489 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; 490 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; /* XXX: don't hardcode? */ 491 tegra_sor_writel(sor, value, SOR_DP_CONFIG_0); 492 493 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); 494 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; 495 value |= 137; /* XXX: don't hardcode? */ 496 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); 497 498 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); 499 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; 500 value |= 2368; /* XXX: don't hardcode? */ 501 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); 502 503 /* enable pad calibration logic */ 504 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 505 value |= SOR_DP_PADCTL_PAD_CAL_PD; 506 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 507 508 if (sor->dpaux) { 509 /* FIXME: properly convert to struct drm_dp_aux */ 510 struct drm_dp_aux *aux = (struct drm_dp_aux *)sor->dpaux; 511 struct drm_dp_link link; 512 u8 rate, lanes; 513 514 err = drm_dp_link_probe(aux, &link); 515 if (err < 0) { 516 dev_err(sor->dev, "failed to probe eDP link: %d\n", 517 err); 518 goto unlock; 519 } 520 521 err = drm_dp_link_power_up(aux, &link); 522 if (err < 0) { 523 dev_err(sor->dev, "failed to power up eDP link: %d\n", 524 err); 525 goto unlock; 526 } 527 528 err = drm_dp_link_configure(aux, &link); 529 if (err < 0) { 530 dev_err(sor->dev, "failed to configure eDP link: %d\n", 531 err); 532 goto unlock; 533 } 534 535 rate = drm_dp_link_rate_to_bw_code(link.rate); 536 lanes = link.num_lanes; 537 538 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 539 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 540 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); 541 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 542 543 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); 544 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 545 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); 546 547 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 548 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 549 550 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); 551 552 /* disable training pattern generator */ 553 554 for (i = 0; i < link.num_lanes; i++) { 555 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 556 SOR_DP_TPG_SCRAMBLER_GALIOS | 557 SOR_DP_TPG_PATTERN_NONE; 558 value = (value << 8) | lane; 559 } 560 561 tegra_sor_writel(sor, value, SOR_DP_TPG); 562 563 err = tegra_sor_dp_train_fast(sor, &link); 564 if (err < 0) { 565 dev_err(sor->dev, "DP fast link training failed: %d\n", 566 err); 567 goto unlock; 568 } 569 570 dev_dbg(sor->dev, "fast link training succeeded\n"); 571 } 572 573 err = tegra_sor_power_up(sor, 250); 574 if (err < 0) { 575 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 576 goto unlock; 577 } 578 579 /* start display controller in continuous mode */ 580 value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS); 581 value |= WRITE_MUX; 582 tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS); 583 584 tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS); 585 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND); 586 587 value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS); 588 value &= ~WRITE_MUX; 589 tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS); 590 591 /* 592 * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete 593 * raster, associate with display controller) 594 */ 595 value = SOR_STATE_ASY_PIXELDEPTH_BPP_24_444 | 596 SOR_STATE_ASY_VSYNCPOL | 597 SOR_STATE_ASY_HSYNCPOL | 598 SOR_STATE_ASY_PROTOCOL_DP_A | 599 SOR_STATE_ASY_CRC_MODE_COMPLETE | 600 SOR_STATE_ASY_OWNER(dc->pipe + 1); 601 tegra_sor_writel(sor, value, SOR_STATE_1); 602 603 /* 604 * TODO: The video timing programming below doesn't seem to match the 605 * register definitions. 606 */ 607 608 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); 609 tegra_sor_writel(sor, value, SOR_HEAD_STATE_1(0)); 610 611 vse = mode->vsync_end - mode->vsync_start - 1; 612 hse = mode->hsync_end - mode->hsync_start - 1; 613 614 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); 615 tegra_sor_writel(sor, value, SOR_HEAD_STATE_2(0)); 616 617 vbe = vse + (mode->vsync_start - mode->vdisplay); 618 hbe = hse + (mode->hsync_start - mode->hdisplay); 619 620 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); 621 tegra_sor_writel(sor, value, SOR_HEAD_STATE_3(0)); 622 623 vbs = vbe + mode->vdisplay; 624 hbs = hbe + mode->hdisplay; 625 626 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); 627 tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0)); 628 629 /* XXX interlaced mode */ 630 tegra_sor_writel(sor, 0x00000001, SOR_HEAD_STATE_5(0)); 631 632 /* CSTM (LVDS, link A/B, upper) */ 633 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | 634 SOR_CSTM_UPPER; 635 tegra_sor_writel(sor, value, SOR_CSTM); 636 637 /* PWM setup */ 638 err = tegra_sor_setup_pwm(sor, 250); 639 if (err < 0) { 640 dev_err(sor->dev, "failed to setup PWM: %d\n", err); 641 goto unlock; 642 } 643 644 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 645 value |= SOR_ENABLE; 646 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 647 648 tegra_sor_update(sor); 649 650 err = tegra_sor_attach(sor); 651 if (err < 0) { 652 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 653 goto unlock; 654 } 655 656 err = tegra_sor_wakeup(sor); 657 if (err < 0) { 658 dev_err(sor->dev, "failed to enable DC: %d\n", err); 659 goto unlock; 660 } 661 662 sor->enabled = true; 663 664 unlock: 665 mutex_unlock(&sor->lock); 666 return err; 667 } 668 669 static int tegra_sor_detach(struct tegra_sor *sor) 670 { 671 unsigned long value, timeout; 672 673 /* switch to safe mode */ 674 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 675 value &= ~SOR_SUPER_STATE_MODE_NORMAL; 676 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 677 tegra_sor_super_update(sor); 678 679 timeout = jiffies + msecs_to_jiffies(250); 680 681 while (time_before(jiffies, timeout)) { 682 value = tegra_sor_readl(sor, SOR_PWR); 683 if (value & SOR_PWR_MODE_SAFE) 684 break; 685 } 686 687 if ((value & SOR_PWR_MODE_SAFE) == 0) 688 return -ETIMEDOUT; 689 690 /* go to sleep */ 691 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 692 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; 693 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 694 tegra_sor_super_update(sor); 695 696 /* detach */ 697 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 698 value &= ~SOR_SUPER_STATE_ATTACHED; 699 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 700 tegra_sor_super_update(sor); 701 702 timeout = jiffies + msecs_to_jiffies(250); 703 704 while (time_before(jiffies, timeout)) { 705 value = tegra_sor_readl(sor, SOR_TEST); 706 if ((value & SOR_TEST_ATTACHED) == 0) 707 break; 708 709 usleep_range(25, 100); 710 } 711 712 if ((value & SOR_TEST_ATTACHED) != 0) 713 return -ETIMEDOUT; 714 715 return 0; 716 } 717 718 static int tegra_sor_power_down(struct tegra_sor *sor) 719 { 720 unsigned long value, timeout; 721 int err; 722 723 value = tegra_sor_readl(sor, SOR_PWR); 724 value &= ~SOR_PWR_NORMAL_STATE_PU; 725 value |= SOR_PWR_TRIGGER; 726 tegra_sor_writel(sor, value, SOR_PWR); 727 728 timeout = jiffies + msecs_to_jiffies(250); 729 730 while (time_before(jiffies, timeout)) { 731 value = tegra_sor_readl(sor, SOR_PWR); 732 if ((value & SOR_PWR_TRIGGER) == 0) 733 return 0; 734 735 usleep_range(25, 100); 736 } 737 738 if ((value & SOR_PWR_TRIGGER) != 0) 739 return -ETIMEDOUT; 740 741 err = clk_set_parent(sor->clk, sor->clk_safe); 742 if (err < 0) 743 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 744 745 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 746 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 747 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); 748 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 749 750 /* stop lane sequencer */ 751 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 752 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; 753 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 754 755 timeout = jiffies + msecs_to_jiffies(250); 756 757 while (time_before(jiffies, timeout)) { 758 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 759 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 760 break; 761 762 usleep_range(25, 100); 763 } 764 765 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 766 return -ETIMEDOUT; 767 768 value = tegra_sor_readl(sor, SOR_PLL_2); 769 value |= SOR_PLL_2_PORT_POWERDOWN; 770 tegra_sor_writel(sor, value, SOR_PLL_2); 771 772 usleep_range(20, 100); 773 774 value = tegra_sor_readl(sor, SOR_PLL_0); 775 value |= SOR_PLL_0_POWER_OFF; 776 value |= SOR_PLL_0_VCOPD; 777 tegra_sor_writel(sor, value, SOR_PLL_0); 778 779 value = tegra_sor_readl(sor, SOR_PLL_2); 780 value |= SOR_PLL_2_SEQ_PLLCAPPD; 781 value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; 782 tegra_sor_writel(sor, value, SOR_PLL_2); 783 784 usleep_range(20, 100); 785 786 return 0; 787 } 788 789 static int tegra_output_sor_disable(struct tegra_output *output) 790 { 791 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); 792 struct tegra_sor *sor = to_sor(output); 793 unsigned long value; 794 int err = 0; 795 796 mutex_lock(&sor->lock); 797 798 if (!sor->enabled) 799 goto unlock; 800 801 err = tegra_sor_detach(sor); 802 if (err < 0) { 803 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 804 goto unlock; 805 } 806 807 tegra_sor_writel(sor, 0, SOR_STATE_1); 808 tegra_sor_update(sor); 809 810 /* 811 * The following accesses registers of the display controller, so make 812 * sure it's only executed when the output is attached to one. 813 */ 814 if (dc) { 815 /* 816 * XXX: We can't do this here because it causes the SOR to go 817 * into an erroneous state and the output will look scrambled 818 * the next time it is enabled. Presumably this is because we 819 * should be doing this only on the next VBLANK. A possible 820 * solution would be to queue a "power-off" event to trigger 821 * this code to be run during the next VBLANK. 822 */ 823 /* 824 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 825 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 826 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); 827 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 828 */ 829 830 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 831 value &= ~DISP_CTRL_MODE_MASK; 832 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 833 834 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 835 value &= ~SOR_ENABLE; 836 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 837 838 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 839 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 840 } 841 842 err = tegra_sor_power_down(sor); 843 if (err < 0) { 844 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 845 goto unlock; 846 } 847 848 if (sor->dpaux) { 849 err = tegra_dpaux_disable(sor->dpaux); 850 if (err < 0) { 851 dev_err(sor->dev, "failed to disable DP: %d\n", err); 852 goto unlock; 853 } 854 } 855 856 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS); 857 if (err < 0) { 858 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err); 859 goto unlock; 860 } 861 862 reset_control_assert(sor->rst); 863 clk_disable_unprepare(sor->clk); 864 865 sor->enabled = false; 866 867 unlock: 868 mutex_unlock(&sor->lock); 869 return err; 870 } 871 872 static int tegra_output_sor_setup_clock(struct tegra_output *output, 873 struct clk *clk, unsigned long pclk, 874 unsigned int *div) 875 { 876 struct tegra_sor *sor = to_sor(output); 877 int err; 878 879 err = clk_set_parent(clk, sor->clk_parent); 880 if (err < 0) { 881 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 882 return err; 883 } 884 885 err = clk_set_rate(sor->clk_parent, pclk); 886 if (err < 0) { 887 dev_err(sor->dev, "failed to set clock rate to %lu Hz\n", pclk); 888 return err; 889 } 890 891 *div = 0; 892 893 return 0; 894 } 895 896 static int tegra_output_sor_check_mode(struct tegra_output *output, 897 struct drm_display_mode *mode, 898 enum drm_mode_status *status) 899 { 900 /* 901 * FIXME: For now, always assume that the mode is okay. 902 */ 903 904 *status = MODE_OK; 905 906 return 0; 907 } 908 909 static enum drm_connector_status 910 tegra_output_sor_detect(struct tegra_output *output) 911 { 912 struct tegra_sor *sor = to_sor(output); 913 914 if (sor->dpaux) 915 return tegra_dpaux_detect(sor->dpaux); 916 917 return connector_status_unknown; 918 } 919 920 static const struct tegra_output_ops sor_ops = { 921 .enable = tegra_output_sor_enable, 922 .disable = tegra_output_sor_disable, 923 .setup_clock = tegra_output_sor_setup_clock, 924 .check_mode = tegra_output_sor_check_mode, 925 .detect = tegra_output_sor_detect, 926 }; 927 928 static int tegra_sor_crc_open(struct inode *inode, struct file *file) 929 { 930 file->private_data = inode->i_private; 931 932 return 0; 933 } 934 935 static int tegra_sor_crc_release(struct inode *inode, struct file *file) 936 { 937 return 0; 938 } 939 940 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) 941 { 942 u32 value; 943 944 timeout = jiffies + msecs_to_jiffies(timeout); 945 946 while (time_before(jiffies, timeout)) { 947 value = tegra_sor_readl(sor, SOR_CRC_A); 948 if (value & SOR_CRC_A_VALID) 949 return 0; 950 951 usleep_range(100, 200); 952 } 953 954 return -ETIMEDOUT; 955 } 956 957 static ssize_t tegra_sor_crc_read(struct file *file, char __user *buffer, 958 size_t size, loff_t *ppos) 959 { 960 struct tegra_sor *sor = file->private_data; 961 ssize_t num, err; 962 char buf[10]; 963 u32 value; 964 965 mutex_lock(&sor->lock); 966 967 if (!sor->enabled) { 968 err = -EAGAIN; 969 goto unlock; 970 } 971 972 value = tegra_sor_readl(sor, SOR_STATE_1); 973 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 974 tegra_sor_writel(sor, value, SOR_STATE_1); 975 976 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); 977 value |= SOR_CRC_CNTRL_ENABLE; 978 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); 979 980 value = tegra_sor_readl(sor, SOR_TEST); 981 value &= ~SOR_TEST_CRC_POST_SERIALIZE; 982 tegra_sor_writel(sor, value, SOR_TEST); 983 984 err = tegra_sor_crc_wait(sor, 100); 985 if (err < 0) 986 goto unlock; 987 988 tegra_sor_writel(sor, SOR_CRC_A_RESET, SOR_CRC_A); 989 value = tegra_sor_readl(sor, SOR_CRC_B); 990 991 num = scnprintf(buf, sizeof(buf), "%08x\n", value); 992 993 err = simple_read_from_buffer(buffer, size, ppos, buf, num); 994 995 unlock: 996 mutex_unlock(&sor->lock); 997 return err; 998 } 999 1000 static const struct file_operations tegra_sor_crc_fops = { 1001 .owner = THIS_MODULE, 1002 .open = tegra_sor_crc_open, 1003 .read = tegra_sor_crc_read, 1004 .release = tegra_sor_crc_release, 1005 }; 1006 1007 static int tegra_sor_debugfs_init(struct tegra_sor *sor, 1008 struct drm_minor *minor) 1009 { 1010 struct dentry *entry; 1011 int err = 0; 1012 1013 sor->debugfs = debugfs_create_dir("sor", minor->debugfs_root); 1014 if (!sor->debugfs) 1015 return -ENOMEM; 1016 1017 entry = debugfs_create_file("crc", 0644, sor->debugfs, sor, 1018 &tegra_sor_crc_fops); 1019 if (!entry) { 1020 dev_err(sor->dev, 1021 "cannot create /sys/kernel/debug/dri/%s/sor/crc\n", 1022 minor->debugfs_root->d_name.name); 1023 err = -ENOMEM; 1024 goto remove; 1025 } 1026 1027 return err; 1028 1029 remove: 1030 debugfs_remove(sor->debugfs); 1031 sor->debugfs = NULL; 1032 return err; 1033 } 1034 1035 static int tegra_sor_debugfs_exit(struct tegra_sor *sor) 1036 { 1037 debugfs_remove_recursive(sor->debugfs); 1038 sor->debugfs = NULL; 1039 1040 return 0; 1041 } 1042 1043 static int tegra_sor_init(struct host1x_client *client) 1044 { 1045 struct drm_device *drm = dev_get_drvdata(client->parent); 1046 struct tegra_sor *sor = host1x_client_to_sor(client); 1047 int err; 1048 1049 if (!sor->dpaux) 1050 return -ENODEV; 1051 1052 sor->output.type = TEGRA_OUTPUT_EDP; 1053 1054 sor->output.dev = sor->dev; 1055 sor->output.ops = &sor_ops; 1056 1057 err = tegra_output_init(drm, &sor->output); 1058 if (err < 0) { 1059 dev_err(sor->dev, "output setup failed: %d\n", err); 1060 return err; 1061 } 1062 1063 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1064 err = tegra_sor_debugfs_init(sor, drm->primary); 1065 if (err < 0) 1066 dev_err(sor->dev, "debugfs setup failed: %d\n", err); 1067 } 1068 1069 if (sor->dpaux) { 1070 err = tegra_dpaux_attach(sor->dpaux, &sor->output); 1071 if (err < 0) { 1072 dev_err(sor->dev, "failed to attach DP: %d\n", err); 1073 return err; 1074 } 1075 } 1076 1077 return 0; 1078 } 1079 1080 static int tegra_sor_exit(struct host1x_client *client) 1081 { 1082 struct tegra_sor *sor = host1x_client_to_sor(client); 1083 int err; 1084 1085 err = tegra_output_disable(&sor->output); 1086 if (err < 0) { 1087 dev_err(sor->dev, "output failed to disable: %d\n", err); 1088 return err; 1089 } 1090 1091 if (sor->dpaux) { 1092 err = tegra_dpaux_detach(sor->dpaux); 1093 if (err < 0) { 1094 dev_err(sor->dev, "failed to detach DP: %d\n", err); 1095 return err; 1096 } 1097 } 1098 1099 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1100 err = tegra_sor_debugfs_exit(sor); 1101 if (err < 0) 1102 dev_err(sor->dev, "debugfs cleanup failed: %d\n", err); 1103 } 1104 1105 err = tegra_output_exit(&sor->output); 1106 if (err < 0) { 1107 dev_err(sor->dev, "output cleanup failed: %d\n", err); 1108 return err; 1109 } 1110 1111 return 0; 1112 } 1113 1114 static const struct host1x_client_ops sor_client_ops = { 1115 .init = tegra_sor_init, 1116 .exit = tegra_sor_exit, 1117 }; 1118 1119 static int tegra_sor_probe(struct platform_device *pdev) 1120 { 1121 struct device_node *np; 1122 struct tegra_sor *sor; 1123 struct resource *regs; 1124 int err; 1125 1126 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); 1127 if (!sor) 1128 return -ENOMEM; 1129 1130 sor->output.dev = sor->dev = &pdev->dev; 1131 1132 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); 1133 if (np) { 1134 sor->dpaux = tegra_dpaux_find_by_of_node(np); 1135 of_node_put(np); 1136 1137 if (!sor->dpaux) 1138 return -EPROBE_DEFER; 1139 } 1140 1141 err = tegra_output_probe(&sor->output); 1142 if (err < 0) 1143 return err; 1144 1145 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1146 sor->regs = devm_ioremap_resource(&pdev->dev, regs); 1147 if (IS_ERR(sor->regs)) 1148 return PTR_ERR(sor->regs); 1149 1150 sor->rst = devm_reset_control_get(&pdev->dev, "sor"); 1151 if (IS_ERR(sor->rst)) 1152 return PTR_ERR(sor->rst); 1153 1154 sor->clk = devm_clk_get(&pdev->dev, NULL); 1155 if (IS_ERR(sor->clk)) 1156 return PTR_ERR(sor->clk); 1157 1158 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); 1159 if (IS_ERR(sor->clk_parent)) 1160 return PTR_ERR(sor->clk_parent); 1161 1162 err = clk_prepare_enable(sor->clk_parent); 1163 if (err < 0) 1164 return err; 1165 1166 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); 1167 if (IS_ERR(sor->clk_safe)) 1168 return PTR_ERR(sor->clk_safe); 1169 1170 err = clk_prepare_enable(sor->clk_safe); 1171 if (err < 0) 1172 return err; 1173 1174 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); 1175 if (IS_ERR(sor->clk_dp)) 1176 return PTR_ERR(sor->clk_dp); 1177 1178 err = clk_prepare_enable(sor->clk_dp); 1179 if (err < 0) 1180 return err; 1181 1182 INIT_LIST_HEAD(&sor->client.list); 1183 sor->client.ops = &sor_client_ops; 1184 sor->client.dev = &pdev->dev; 1185 1186 mutex_init(&sor->lock); 1187 1188 err = host1x_client_register(&sor->client); 1189 if (err < 0) { 1190 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1191 err); 1192 return err; 1193 } 1194 1195 platform_set_drvdata(pdev, sor); 1196 1197 return 0; 1198 } 1199 1200 static int tegra_sor_remove(struct platform_device *pdev) 1201 { 1202 struct tegra_sor *sor = platform_get_drvdata(pdev); 1203 int err; 1204 1205 err = host1x_client_unregister(&sor->client); 1206 if (err < 0) { 1207 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 1208 err); 1209 return err; 1210 } 1211 1212 clk_disable_unprepare(sor->clk_parent); 1213 clk_disable_unprepare(sor->clk_safe); 1214 clk_disable_unprepare(sor->clk_dp); 1215 clk_disable_unprepare(sor->clk); 1216 1217 return 0; 1218 } 1219 1220 static const struct of_device_id tegra_sor_of_match[] = { 1221 { .compatible = "nvidia,tegra124-sor", }, 1222 { }, 1223 }; 1224 1225 struct platform_driver tegra_sor_driver = { 1226 .driver = { 1227 .name = "tegra-sor", 1228 .of_match_table = tegra_sor_of_match, 1229 }, 1230 .probe = tegra_sor_probe, 1231 .remove = tegra_sor_remove, 1232 }; 1233