1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 26b6b6042SThierry Reding /* 36b6b6042SThierry Reding * Copyright (C) 2013 NVIDIA Corporation 46b6b6042SThierry Reding */ 56b6b6042SThierry Reding 66b6b6042SThierry Reding #include <linux/clk.h> 7b299221cSThierry Reding #include <linux/clk-provider.h> 8a82752e1SThierry Reding #include <linux/debugfs.h> 96fad8f66SThierry Reding #include <linux/gpio.h> 106b6b6042SThierry Reding #include <linux/io.h> 11eb1df694SSam Ravnborg #include <linux/module.h> 12459cc2c6SThierry Reding #include <linux/of_device.h> 136b6b6042SThierry Reding #include <linux/platform_device.h> 14aaff8bd2SThierry Reding #include <linux/pm_runtime.h> 15459cc2c6SThierry Reding #include <linux/regulator/consumer.h> 166b6b6042SThierry Reding #include <linux/reset.h> 17306a7f91SThierry Reding 187232398aSThierry Reding #include <soc/tegra/pmc.h> 196b6b6042SThierry Reding 204aa3df71SThierry Reding #include <drm/drm_atomic_helper.h> 21eb1df694SSam Ravnborg #include <drm/drm_debugfs.h> 226b6b6042SThierry Reding #include <drm/drm_dp_helper.h> 23eb1df694SSam Ravnborg #include <drm/drm_file.h> 246fad8f66SThierry Reding #include <drm/drm_panel.h> 2536e90221SThierry Reding #include <drm/drm_scdc_helper.h> 266b6b6042SThierry Reding 276b6b6042SThierry Reding #include "dc.h" 289a42c7c6SThierry Reding #include "dp.h" 296b6b6042SThierry Reding #include "drm.h" 30fad7b806SThierry Reding #include "hda.h" 316b6b6042SThierry Reding #include "sor.h" 32932f6529SThierry Reding #include "trace.h" 336b6b6042SThierry Reding 34459cc2c6SThierry Reding #define SOR_REKEY 0x38 35459cc2c6SThierry Reding 36459cc2c6SThierry Reding struct tegra_sor_hdmi_settings { 37459cc2c6SThierry Reding unsigned long frequency; 38459cc2c6SThierry Reding 39459cc2c6SThierry Reding u8 vcocap; 40c57997bcSThierry Reding u8 filter; 41459cc2c6SThierry Reding u8 ichpmp; 42459cc2c6SThierry Reding u8 loadadj; 43c57997bcSThierry Reding u8 tmds_termadj; 44c57997bcSThierry Reding u8 tx_pu_value; 45c57997bcSThierry Reding u8 bg_temp_coef; 46c57997bcSThierry Reding u8 bg_vref_level; 47c57997bcSThierry Reding u8 avdd10_level; 48c57997bcSThierry Reding u8 avdd14_level; 49c57997bcSThierry Reding u8 sparepll; 50459cc2c6SThierry Reding 51459cc2c6SThierry Reding u8 drive_current[4]; 52459cc2c6SThierry Reding u8 preemphasis[4]; 53459cc2c6SThierry Reding }; 54459cc2c6SThierry Reding 55459cc2c6SThierry Reding #if 1 56459cc2c6SThierry Reding static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 57459cc2c6SThierry Reding { 58459cc2c6SThierry Reding .frequency = 54000000, 59459cc2c6SThierry Reding .vcocap = 0x0, 60c57997bcSThierry Reding .filter = 0x0, 61459cc2c6SThierry Reding .ichpmp = 0x1, 62459cc2c6SThierry Reding .loadadj = 0x3, 63c57997bcSThierry Reding .tmds_termadj = 0x9, 64c57997bcSThierry Reding .tx_pu_value = 0x10, 65c57997bcSThierry Reding .bg_temp_coef = 0x3, 66c57997bcSThierry Reding .bg_vref_level = 0x8, 67c57997bcSThierry Reding .avdd10_level = 0x4, 68c57997bcSThierry Reding .avdd14_level = 0x4, 69c57997bcSThierry Reding .sparepll = 0x0, 70459cc2c6SThierry Reding .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 71459cc2c6SThierry Reding .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 72459cc2c6SThierry Reding }, { 73459cc2c6SThierry Reding .frequency = 75000000, 74459cc2c6SThierry Reding .vcocap = 0x3, 75c57997bcSThierry Reding .filter = 0x0, 76459cc2c6SThierry Reding .ichpmp = 0x1, 77459cc2c6SThierry Reding .loadadj = 0x3, 78c57997bcSThierry Reding .tmds_termadj = 0x9, 79c57997bcSThierry Reding .tx_pu_value = 0x40, 80c57997bcSThierry Reding .bg_temp_coef = 0x3, 81c57997bcSThierry Reding .bg_vref_level = 0x8, 82c57997bcSThierry Reding .avdd10_level = 0x4, 83c57997bcSThierry Reding .avdd14_level = 0x4, 84c57997bcSThierry Reding .sparepll = 0x0, 85459cc2c6SThierry Reding .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 86459cc2c6SThierry Reding .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 87459cc2c6SThierry Reding }, { 88459cc2c6SThierry Reding .frequency = 150000000, 89459cc2c6SThierry Reding .vcocap = 0x3, 90c57997bcSThierry Reding .filter = 0x0, 91459cc2c6SThierry Reding .ichpmp = 0x1, 92459cc2c6SThierry Reding .loadadj = 0x3, 93c57997bcSThierry Reding .tmds_termadj = 0x9, 94c57997bcSThierry Reding .tx_pu_value = 0x66, 95c57997bcSThierry Reding .bg_temp_coef = 0x3, 96c57997bcSThierry Reding .bg_vref_level = 0x8, 97c57997bcSThierry Reding .avdd10_level = 0x4, 98c57997bcSThierry Reding .avdd14_level = 0x4, 99c57997bcSThierry Reding .sparepll = 0x0, 100459cc2c6SThierry Reding .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 101459cc2c6SThierry Reding .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 102459cc2c6SThierry Reding }, { 103459cc2c6SThierry Reding .frequency = 300000000, 104459cc2c6SThierry Reding .vcocap = 0x3, 105c57997bcSThierry Reding .filter = 0x0, 106459cc2c6SThierry Reding .ichpmp = 0x1, 107459cc2c6SThierry Reding .loadadj = 0x3, 108c57997bcSThierry Reding .tmds_termadj = 0x9, 109c57997bcSThierry Reding .tx_pu_value = 0x66, 110c57997bcSThierry Reding .bg_temp_coef = 0x3, 111c57997bcSThierry Reding .bg_vref_level = 0xa, 112c57997bcSThierry Reding .avdd10_level = 0x4, 113c57997bcSThierry Reding .avdd14_level = 0x4, 114c57997bcSThierry Reding .sparepll = 0x0, 115459cc2c6SThierry Reding .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 116459cc2c6SThierry Reding .preemphasis = { 0x00, 0x17, 0x17, 0x17 }, 117459cc2c6SThierry Reding }, { 118459cc2c6SThierry Reding .frequency = 600000000, 119459cc2c6SThierry Reding .vcocap = 0x3, 120c57997bcSThierry Reding .filter = 0x0, 121459cc2c6SThierry Reding .ichpmp = 0x1, 122459cc2c6SThierry Reding .loadadj = 0x3, 123c57997bcSThierry Reding .tmds_termadj = 0x9, 124c57997bcSThierry Reding .tx_pu_value = 0x66, 125c57997bcSThierry Reding .bg_temp_coef = 0x3, 126c57997bcSThierry Reding .bg_vref_level = 0x8, 127c57997bcSThierry Reding .avdd10_level = 0x4, 128c57997bcSThierry Reding .avdd14_level = 0x4, 129c57997bcSThierry Reding .sparepll = 0x0, 130459cc2c6SThierry Reding .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 131459cc2c6SThierry Reding .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 132459cc2c6SThierry Reding }, 133459cc2c6SThierry Reding }; 134459cc2c6SThierry Reding #else 135459cc2c6SThierry Reding static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 136459cc2c6SThierry Reding { 137459cc2c6SThierry Reding .frequency = 75000000, 138459cc2c6SThierry Reding .vcocap = 0x3, 139c57997bcSThierry Reding .filter = 0x0, 140459cc2c6SThierry Reding .ichpmp = 0x1, 141459cc2c6SThierry Reding .loadadj = 0x3, 142c57997bcSThierry Reding .tmds_termadj = 0x9, 143c57997bcSThierry Reding .tx_pu_value = 0x40, 144c57997bcSThierry Reding .bg_temp_coef = 0x3, 145c57997bcSThierry Reding .bg_vref_level = 0x8, 146c57997bcSThierry Reding .avdd10_level = 0x4, 147c57997bcSThierry Reding .avdd14_level = 0x4, 148c57997bcSThierry Reding .sparepll = 0x0, 149459cc2c6SThierry Reding .drive_current = { 0x29, 0x29, 0x29, 0x29 }, 150459cc2c6SThierry Reding .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 151459cc2c6SThierry Reding }, { 152459cc2c6SThierry Reding .frequency = 150000000, 153459cc2c6SThierry Reding .vcocap = 0x3, 154c57997bcSThierry Reding .filter = 0x0, 155459cc2c6SThierry Reding .ichpmp = 0x1, 156459cc2c6SThierry Reding .loadadj = 0x3, 157c57997bcSThierry Reding .tmds_termadj = 0x9, 158c57997bcSThierry Reding .tx_pu_value = 0x66, 159c57997bcSThierry Reding .bg_temp_coef = 0x3, 160c57997bcSThierry Reding .bg_vref_level = 0x8, 161c57997bcSThierry Reding .avdd10_level = 0x4, 162c57997bcSThierry Reding .avdd14_level = 0x4, 163c57997bcSThierry Reding .sparepll = 0x0, 164459cc2c6SThierry Reding .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 165459cc2c6SThierry Reding .preemphasis = { 0x01, 0x02, 0x02, 0x02 }, 166459cc2c6SThierry Reding }, { 167459cc2c6SThierry Reding .frequency = 300000000, 168459cc2c6SThierry Reding .vcocap = 0x3, 169c57997bcSThierry Reding .filter = 0x0, 170459cc2c6SThierry Reding .ichpmp = 0x6, 171459cc2c6SThierry Reding .loadadj = 0x3, 172c57997bcSThierry Reding .tmds_termadj = 0x9, 173c57997bcSThierry Reding .tx_pu_value = 0x66, 174c57997bcSThierry Reding .bg_temp_coef = 0x3, 175c57997bcSThierry Reding .bg_vref_level = 0xf, 176c57997bcSThierry Reding .avdd10_level = 0x4, 177c57997bcSThierry Reding .avdd14_level = 0x4, 178c57997bcSThierry Reding .sparepll = 0x0, 179459cc2c6SThierry Reding .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 180459cc2c6SThierry Reding .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e }, 181459cc2c6SThierry Reding }, { 182459cc2c6SThierry Reding .frequency = 600000000, 183459cc2c6SThierry Reding .vcocap = 0x3, 184c57997bcSThierry Reding .filter = 0x0, 185459cc2c6SThierry Reding .ichpmp = 0xa, 186459cc2c6SThierry Reding .loadadj = 0x3, 187c57997bcSThierry Reding .tmds_termadj = 0xb, 188c57997bcSThierry Reding .tx_pu_value = 0x66, 189c57997bcSThierry Reding .bg_temp_coef = 0x3, 190c57997bcSThierry Reding .bg_vref_level = 0xe, 191c57997bcSThierry Reding .avdd10_level = 0x4, 192c57997bcSThierry Reding .avdd14_level = 0x4, 193c57997bcSThierry Reding .sparepll = 0x0, 194459cc2c6SThierry Reding .drive_current = { 0x35, 0x3e, 0x3e, 0x3e }, 195459cc2c6SThierry Reding .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f }, 196459cc2c6SThierry Reding }, 197459cc2c6SThierry Reding }; 198459cc2c6SThierry Reding #endif 199459cc2c6SThierry Reding 200c57997bcSThierry Reding static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = { 201c57997bcSThierry Reding { 202c57997bcSThierry Reding .frequency = 54000000, 203c57997bcSThierry Reding .vcocap = 0, 204c57997bcSThierry Reding .filter = 5, 205c57997bcSThierry Reding .ichpmp = 5, 206c57997bcSThierry Reding .loadadj = 3, 207c57997bcSThierry Reding .tmds_termadj = 0xf, 208c57997bcSThierry Reding .tx_pu_value = 0, 209c57997bcSThierry Reding .bg_temp_coef = 3, 210c57997bcSThierry Reding .bg_vref_level = 8, 211c57997bcSThierry Reding .avdd10_level = 4, 212c57997bcSThierry Reding .avdd14_level = 4, 213c57997bcSThierry Reding .sparepll = 0x54, 214c57997bcSThierry Reding .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 215c57997bcSThierry Reding .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 216c57997bcSThierry Reding }, { 217c57997bcSThierry Reding .frequency = 75000000, 218c57997bcSThierry Reding .vcocap = 1, 219c57997bcSThierry Reding .filter = 5, 220c57997bcSThierry Reding .ichpmp = 5, 221c57997bcSThierry Reding .loadadj = 3, 222c57997bcSThierry Reding .tmds_termadj = 0xf, 223c57997bcSThierry Reding .tx_pu_value = 0, 224c57997bcSThierry Reding .bg_temp_coef = 3, 225c57997bcSThierry Reding .bg_vref_level = 8, 226c57997bcSThierry Reding .avdd10_level = 4, 227c57997bcSThierry Reding .avdd14_level = 4, 228c57997bcSThierry Reding .sparepll = 0x44, 229c57997bcSThierry Reding .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 230c57997bcSThierry Reding .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 231c57997bcSThierry Reding }, { 232c57997bcSThierry Reding .frequency = 150000000, 233c57997bcSThierry Reding .vcocap = 3, 234c57997bcSThierry Reding .filter = 5, 235c57997bcSThierry Reding .ichpmp = 5, 236c57997bcSThierry Reding .loadadj = 3, 237c57997bcSThierry Reding .tmds_termadj = 15, 238c57997bcSThierry Reding .tx_pu_value = 0x66 /* 0 */, 239c57997bcSThierry Reding .bg_temp_coef = 3, 240c57997bcSThierry Reding .bg_vref_level = 8, 241c57997bcSThierry Reding .avdd10_level = 4, 242c57997bcSThierry Reding .avdd14_level = 4, 243c57997bcSThierry Reding .sparepll = 0x00, /* 0x34 */ 244c57997bcSThierry Reding .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, 245c57997bcSThierry Reding .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 246c57997bcSThierry Reding }, { 247c57997bcSThierry Reding .frequency = 300000000, 248c57997bcSThierry Reding .vcocap = 3, 249c57997bcSThierry Reding .filter = 5, 250c57997bcSThierry Reding .ichpmp = 5, 251c57997bcSThierry Reding .loadadj = 3, 252c57997bcSThierry Reding .tmds_termadj = 15, 253c57997bcSThierry Reding .tx_pu_value = 64, 254c57997bcSThierry Reding .bg_temp_coef = 3, 255c57997bcSThierry Reding .bg_vref_level = 8, 256c57997bcSThierry Reding .avdd10_level = 4, 257c57997bcSThierry Reding .avdd14_level = 4, 258c57997bcSThierry Reding .sparepll = 0x34, 259c57997bcSThierry Reding .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 260c57997bcSThierry Reding .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 261c57997bcSThierry Reding }, { 262c57997bcSThierry Reding .frequency = 600000000, 263c57997bcSThierry Reding .vcocap = 3, 264c57997bcSThierry Reding .filter = 5, 265c57997bcSThierry Reding .ichpmp = 5, 266c57997bcSThierry Reding .loadadj = 3, 267c57997bcSThierry Reding .tmds_termadj = 12, 268c57997bcSThierry Reding .tx_pu_value = 96, 269c57997bcSThierry Reding .bg_temp_coef = 3, 270c57997bcSThierry Reding .bg_vref_level = 8, 271c57997bcSThierry Reding .avdd10_level = 4, 272c57997bcSThierry Reding .avdd14_level = 4, 273c57997bcSThierry Reding .sparepll = 0x34, 274c57997bcSThierry Reding .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 275c57997bcSThierry Reding .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 276c57997bcSThierry Reding } 277c57997bcSThierry Reding }; 278c57997bcSThierry Reding 2799b6c14b8SThierry Reding static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = { 2809b6c14b8SThierry Reding { 2819b6c14b8SThierry Reding .frequency = 54000000, 2829b6c14b8SThierry Reding .vcocap = 0, 2839b6c14b8SThierry Reding .filter = 5, 2849b6c14b8SThierry Reding .ichpmp = 5, 2859b6c14b8SThierry Reding .loadadj = 3, 2869b6c14b8SThierry Reding .tmds_termadj = 0xf, 2879b6c14b8SThierry Reding .tx_pu_value = 0, 2889b6c14b8SThierry Reding .bg_temp_coef = 3, 2899b6c14b8SThierry Reding .bg_vref_level = 8, 2909b6c14b8SThierry Reding .avdd10_level = 4, 2919b6c14b8SThierry Reding .avdd14_level = 4, 2929b6c14b8SThierry Reding .sparepll = 0x54, 2939b6c14b8SThierry Reding .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 2949b6c14b8SThierry Reding .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 2959b6c14b8SThierry Reding }, { 2969b6c14b8SThierry Reding .frequency = 75000000, 2979b6c14b8SThierry Reding .vcocap = 1, 2989b6c14b8SThierry Reding .filter = 5, 2999b6c14b8SThierry Reding .ichpmp = 5, 3009b6c14b8SThierry Reding .loadadj = 3, 3019b6c14b8SThierry Reding .tmds_termadj = 0xf, 3029b6c14b8SThierry Reding .tx_pu_value = 0, 3039b6c14b8SThierry Reding .bg_temp_coef = 3, 3049b6c14b8SThierry Reding .bg_vref_level = 8, 3059b6c14b8SThierry Reding .avdd10_level = 4, 3069b6c14b8SThierry Reding .avdd14_level = 4, 3079b6c14b8SThierry Reding .sparepll = 0x44, 3089b6c14b8SThierry Reding .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 3099b6c14b8SThierry Reding .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 3109b6c14b8SThierry Reding }, { 3119b6c14b8SThierry Reding .frequency = 150000000, 3129b6c14b8SThierry Reding .vcocap = 3, 3139b6c14b8SThierry Reding .filter = 5, 3149b6c14b8SThierry Reding .ichpmp = 5, 3159b6c14b8SThierry Reding .loadadj = 3, 3169b6c14b8SThierry Reding .tmds_termadj = 15, 3179b6c14b8SThierry Reding .tx_pu_value = 0x66 /* 0 */, 3189b6c14b8SThierry Reding .bg_temp_coef = 3, 3199b6c14b8SThierry Reding .bg_vref_level = 8, 3209b6c14b8SThierry Reding .avdd10_level = 4, 3219b6c14b8SThierry Reding .avdd14_level = 4, 3229b6c14b8SThierry Reding .sparepll = 0x00, /* 0x34 */ 3239b6c14b8SThierry Reding .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, 3249b6c14b8SThierry Reding .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 3259b6c14b8SThierry Reding }, { 3269b6c14b8SThierry Reding .frequency = 300000000, 3279b6c14b8SThierry Reding .vcocap = 3, 3289b6c14b8SThierry Reding .filter = 5, 3299b6c14b8SThierry Reding .ichpmp = 5, 3309b6c14b8SThierry Reding .loadadj = 3, 3319b6c14b8SThierry Reding .tmds_termadj = 15, 3329b6c14b8SThierry Reding .tx_pu_value = 64, 3339b6c14b8SThierry Reding .bg_temp_coef = 3, 3349b6c14b8SThierry Reding .bg_vref_level = 8, 3359b6c14b8SThierry Reding .avdd10_level = 4, 3369b6c14b8SThierry Reding .avdd14_level = 4, 3379b6c14b8SThierry Reding .sparepll = 0x34, 3389b6c14b8SThierry Reding .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 3399b6c14b8SThierry Reding .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 3409b6c14b8SThierry Reding }, { 3419b6c14b8SThierry Reding .frequency = 600000000, 3429b6c14b8SThierry Reding .vcocap = 3, 3439b6c14b8SThierry Reding .filter = 5, 3449b6c14b8SThierry Reding .ichpmp = 5, 3459b6c14b8SThierry Reding .loadadj = 3, 3469b6c14b8SThierry Reding .tmds_termadj = 12, 3479b6c14b8SThierry Reding .tx_pu_value = 96, 3489b6c14b8SThierry Reding .bg_temp_coef = 3, 3499b6c14b8SThierry Reding .bg_vref_level = 8, 3509b6c14b8SThierry Reding .avdd10_level = 4, 3519b6c14b8SThierry Reding .avdd14_level = 4, 3529b6c14b8SThierry Reding .sparepll = 0x34, 3539b6c14b8SThierry Reding .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 3549b6c14b8SThierry Reding .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 3559b6c14b8SThierry Reding } 3569b6c14b8SThierry Reding }; 3579b6c14b8SThierry Reding 358880cee0bSThierry Reding struct tegra_sor_regs { 359880cee0bSThierry Reding unsigned int head_state0; 360880cee0bSThierry Reding unsigned int head_state1; 361880cee0bSThierry Reding unsigned int head_state2; 362880cee0bSThierry Reding unsigned int head_state3; 363880cee0bSThierry Reding unsigned int head_state4; 364880cee0bSThierry Reding unsigned int head_state5; 365880cee0bSThierry Reding unsigned int pll0; 366880cee0bSThierry Reding unsigned int pll1; 367880cee0bSThierry Reding unsigned int pll2; 368880cee0bSThierry Reding unsigned int pll3; 369880cee0bSThierry Reding unsigned int dp_padctl0; 370880cee0bSThierry Reding unsigned int dp_padctl2; 371880cee0bSThierry Reding }; 372880cee0bSThierry Reding 373459cc2c6SThierry Reding struct tegra_sor_soc { 374459cc2c6SThierry Reding bool supports_edp; 375459cc2c6SThierry Reding bool supports_lvds; 376459cc2c6SThierry Reding bool supports_hdmi; 377459cc2c6SThierry Reding bool supports_dp; 378459cc2c6SThierry Reding 379880cee0bSThierry Reding const struct tegra_sor_regs *regs; 380c57997bcSThierry Reding bool has_nvdisplay; 381880cee0bSThierry Reding 382459cc2c6SThierry Reding const struct tegra_sor_hdmi_settings *settings; 383459cc2c6SThierry Reding unsigned int num_settings; 38430b49435SThierry Reding 38530b49435SThierry Reding const u8 *xbar_cfg; 386c1763937SThierry Reding const u8 *lane_map; 387c1763937SThierry Reding 388c1763937SThierry Reding const u8 (*voltage_swing)[4][4]; 389c1763937SThierry Reding const u8 (*pre_emphasis)[4][4]; 390c1763937SThierry Reding const u8 (*post_cursor)[4][4]; 391c1763937SThierry Reding const u8 (*tx_pu)[4][4]; 392459cc2c6SThierry Reding }; 393459cc2c6SThierry Reding 394459cc2c6SThierry Reding struct tegra_sor; 395459cc2c6SThierry Reding 396459cc2c6SThierry Reding struct tegra_sor_ops { 397459cc2c6SThierry Reding const char *name; 398459cc2c6SThierry Reding int (*probe)(struct tegra_sor *sor); 399459cc2c6SThierry Reding int (*remove)(struct tegra_sor *sor); 400459cc2c6SThierry Reding }; 401459cc2c6SThierry Reding 4026b6b6042SThierry Reding struct tegra_sor { 4036b6b6042SThierry Reding struct host1x_client client; 4046b6b6042SThierry Reding struct tegra_output output; 4056b6b6042SThierry Reding struct device *dev; 4066b6b6042SThierry Reding 407459cc2c6SThierry Reding const struct tegra_sor_soc *soc; 4086b6b6042SThierry Reding void __iomem *regs; 409c57997bcSThierry Reding unsigned int index; 4108e2988a7SThierry Reding unsigned int irq; 4116b6b6042SThierry Reding 4126b6b6042SThierry Reding struct reset_control *rst; 4136b6b6042SThierry Reding struct clk *clk_parent; 4146b6b6042SThierry Reding struct clk *clk_safe; 415e1335e2fSThierry Reding struct clk *clk_out; 416e1335e2fSThierry Reding struct clk *clk_pad; 4176b6b6042SThierry Reding struct clk *clk_dp; 4186b6b6042SThierry Reding struct clk *clk; 4196b6b6042SThierry Reding 4206d6c815dSThierry Reding u8 xbar_cfg[5]; 4216d6c815dSThierry Reding 422c1763937SThierry Reding struct drm_dp_link link; 4239542c237SThierry Reding struct drm_dp_aux *aux; 4246b6b6042SThierry Reding 425dab16336SThierry Reding struct drm_info_list *debugfs_files; 426459cc2c6SThierry Reding 427459cc2c6SThierry Reding const struct tegra_sor_ops *ops; 428c57997bcSThierry Reding enum tegra_io_pad pad; 429459cc2c6SThierry Reding 430459cc2c6SThierry Reding /* for HDMI 2.0 */ 431459cc2c6SThierry Reding struct tegra_sor_hdmi_settings *settings; 432459cc2c6SThierry Reding unsigned int num_settings; 433459cc2c6SThierry Reding 434459cc2c6SThierry Reding struct regulator *avdd_io_supply; 435459cc2c6SThierry Reding struct regulator *vdd_pll_supply; 436459cc2c6SThierry Reding struct regulator *hdmi_supply; 43736e90221SThierry Reding 43836e90221SThierry Reding struct delayed_work scdc; 43936e90221SThierry Reding bool scdc_enabled; 4408e2988a7SThierry Reding 441fad7b806SThierry Reding struct tegra_hda_format format; 4426b6b6042SThierry Reding }; 4436b6b6042SThierry Reding 444c31efa7aSThierry Reding struct tegra_sor_state { 445c31efa7aSThierry Reding struct drm_connector_state base; 446c31efa7aSThierry Reding 44736e90221SThierry Reding unsigned int link_speed; 44836e90221SThierry Reding unsigned long pclk; 449c31efa7aSThierry Reding unsigned int bpc; 450c31efa7aSThierry Reding }; 451c31efa7aSThierry Reding 452c31efa7aSThierry Reding static inline struct tegra_sor_state * 453c31efa7aSThierry Reding to_sor_state(struct drm_connector_state *state) 454c31efa7aSThierry Reding { 455c31efa7aSThierry Reding return container_of(state, struct tegra_sor_state, base); 456c31efa7aSThierry Reding } 457c31efa7aSThierry Reding 45834fa183bSThierry Reding struct tegra_sor_config { 45934fa183bSThierry Reding u32 bits_per_pixel; 46034fa183bSThierry Reding 46134fa183bSThierry Reding u32 active_polarity; 46234fa183bSThierry Reding u32 active_count; 46334fa183bSThierry Reding u32 tu_size; 46434fa183bSThierry Reding u32 active_frac; 46534fa183bSThierry Reding u32 watermark; 4667890b576SThierry Reding 4677890b576SThierry Reding u32 hblank_symbols; 4687890b576SThierry Reding u32 vblank_symbols; 46934fa183bSThierry Reding }; 47034fa183bSThierry Reding 4716b6b6042SThierry Reding static inline struct tegra_sor * 4726b6b6042SThierry Reding host1x_client_to_sor(struct host1x_client *client) 4736b6b6042SThierry Reding { 4746b6b6042SThierry Reding return container_of(client, struct tegra_sor, client); 4756b6b6042SThierry Reding } 4766b6b6042SThierry Reding 4776b6b6042SThierry Reding static inline struct tegra_sor *to_sor(struct tegra_output *output) 4786b6b6042SThierry Reding { 4796b6b6042SThierry Reding return container_of(output, struct tegra_sor, output); 4806b6b6042SThierry Reding } 4816b6b6042SThierry Reding 4825c5f1301SThierry Reding static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) 4836b6b6042SThierry Reding { 484932f6529SThierry Reding u32 value = readl(sor->regs + (offset << 2)); 485932f6529SThierry Reding 486932f6529SThierry Reding trace_sor_readl(sor->dev, offset, value); 487932f6529SThierry Reding 488932f6529SThierry Reding return value; 4896b6b6042SThierry Reding } 4906b6b6042SThierry Reding 49128fe2076SThierry Reding static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, 4925c5f1301SThierry Reding unsigned int offset) 4936b6b6042SThierry Reding { 494932f6529SThierry Reding trace_sor_writel(sor->dev, offset, value); 4956b6b6042SThierry Reding writel(value, sor->regs + (offset << 2)); 4966b6b6042SThierry Reding } 4976b6b6042SThierry Reding 49825bb2cecSThierry Reding static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) 49925bb2cecSThierry Reding { 50025bb2cecSThierry Reding int err; 50125bb2cecSThierry Reding 50225bb2cecSThierry Reding clk_disable_unprepare(sor->clk); 50325bb2cecSThierry Reding 504e1335e2fSThierry Reding err = clk_set_parent(sor->clk_out, parent); 50525bb2cecSThierry Reding if (err < 0) 50625bb2cecSThierry Reding return err; 50725bb2cecSThierry Reding 50825bb2cecSThierry Reding err = clk_prepare_enable(sor->clk); 50925bb2cecSThierry Reding if (err < 0) 51025bb2cecSThierry Reding return err; 51125bb2cecSThierry Reding 51225bb2cecSThierry Reding return 0; 51325bb2cecSThierry Reding } 51425bb2cecSThierry Reding 515e1335e2fSThierry Reding struct tegra_clk_sor_pad { 516b299221cSThierry Reding struct clk_hw hw; 517b299221cSThierry Reding struct tegra_sor *sor; 518b299221cSThierry Reding }; 519b299221cSThierry Reding 520e1335e2fSThierry Reding static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw) 521b299221cSThierry Reding { 522e1335e2fSThierry Reding return container_of(hw, struct tegra_clk_sor_pad, hw); 523b299221cSThierry Reding } 524b299221cSThierry Reding 525e1335e2fSThierry Reding static const char * const tegra_clk_sor_pad_parents[] = { 526b299221cSThierry Reding "pll_d2_out0", "pll_dp" 527b299221cSThierry Reding }; 528b299221cSThierry Reding 529e1335e2fSThierry Reding static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index) 530b299221cSThierry Reding { 531e1335e2fSThierry Reding struct tegra_clk_sor_pad *pad = to_pad(hw); 532e1335e2fSThierry Reding struct tegra_sor *sor = pad->sor; 533b299221cSThierry Reding u32 value; 534b299221cSThierry Reding 535b299221cSThierry Reding value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 536b299221cSThierry Reding value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 537b299221cSThierry Reding 538b299221cSThierry Reding switch (index) { 539b299221cSThierry Reding case 0: 540b299221cSThierry Reding value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 541b299221cSThierry Reding break; 542b299221cSThierry Reding 543b299221cSThierry Reding case 1: 544b299221cSThierry Reding value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 545b299221cSThierry Reding break; 546b299221cSThierry Reding } 547b299221cSThierry Reding 548b299221cSThierry Reding tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 549b299221cSThierry Reding 550b299221cSThierry Reding return 0; 551b299221cSThierry Reding } 552b299221cSThierry Reding 553e1335e2fSThierry Reding static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw) 554b299221cSThierry Reding { 555e1335e2fSThierry Reding struct tegra_clk_sor_pad *pad = to_pad(hw); 556e1335e2fSThierry Reding struct tegra_sor *sor = pad->sor; 557b299221cSThierry Reding u8 parent = U8_MAX; 558b299221cSThierry Reding u32 value; 559b299221cSThierry Reding 560b299221cSThierry Reding value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 561b299221cSThierry Reding 562b299221cSThierry Reding switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { 563b299221cSThierry Reding case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK: 564b299221cSThierry Reding case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK: 565b299221cSThierry Reding parent = 0; 566b299221cSThierry Reding break; 567b299221cSThierry Reding 568b299221cSThierry Reding case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK: 569b299221cSThierry Reding case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK: 570b299221cSThierry Reding parent = 1; 571b299221cSThierry Reding break; 572b299221cSThierry Reding } 573b299221cSThierry Reding 574b299221cSThierry Reding return parent; 575b299221cSThierry Reding } 576b299221cSThierry Reding 577e1335e2fSThierry Reding static const struct clk_ops tegra_clk_sor_pad_ops = { 578e1335e2fSThierry Reding .set_parent = tegra_clk_sor_pad_set_parent, 579e1335e2fSThierry Reding .get_parent = tegra_clk_sor_pad_get_parent, 580b299221cSThierry Reding }; 581b299221cSThierry Reding 582e1335e2fSThierry Reding static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, 583b299221cSThierry Reding const char *name) 584b299221cSThierry Reding { 585e1335e2fSThierry Reding struct tegra_clk_sor_pad *pad; 586b299221cSThierry Reding struct clk_init_data init; 587b299221cSThierry Reding struct clk *clk; 588b299221cSThierry Reding 589e1335e2fSThierry Reding pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); 590e1335e2fSThierry Reding if (!pad) 591b299221cSThierry Reding return ERR_PTR(-ENOMEM); 592b299221cSThierry Reding 593e1335e2fSThierry Reding pad->sor = sor; 594b299221cSThierry Reding 595b299221cSThierry Reding init.name = name; 596b299221cSThierry Reding init.flags = 0; 597e1335e2fSThierry Reding init.parent_names = tegra_clk_sor_pad_parents; 598e1335e2fSThierry Reding init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents); 599e1335e2fSThierry Reding init.ops = &tegra_clk_sor_pad_ops; 600b299221cSThierry Reding 601e1335e2fSThierry Reding pad->hw.init = &init; 602b299221cSThierry Reding 603e1335e2fSThierry Reding clk = devm_clk_register(sor->dev, &pad->hw); 604b299221cSThierry Reding 605b299221cSThierry Reding return clk; 606b299221cSThierry Reding } 607b299221cSThierry Reding 608c1763937SThierry Reding static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes) 6096b6b6042SThierry Reding { 610c1763937SThierry Reding unsigned long timeout; 61128fe2076SThierry Reding u32 value; 6126b6b6042SThierry Reding 613c1763937SThierry Reding /* 614c1763937SThierry Reding * Clear or set the PD_TXD bit corresponding to each lane, depending 615c1763937SThierry Reding * on whether it is used or not. 616c1763937SThierry Reding */ 617880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 618c1763937SThierry Reding 619c1763937SThierry Reding if (lanes <= 2) 620c1763937SThierry Reding value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | 621c1763937SThierry Reding SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2])); 622c1763937SThierry Reding else 623c1763937SThierry Reding value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | 624c1763937SThierry Reding SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]); 625c1763937SThierry Reding 626c1763937SThierry Reding if (lanes <= 1) 627c1763937SThierry Reding value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); 628c1763937SThierry Reding else 629c1763937SThierry Reding value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); 630c1763937SThierry Reding 631c1763937SThierry Reding if (lanes == 0) 632c1763937SThierry Reding value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); 633c1763937SThierry Reding else 634c1763937SThierry Reding value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); 635c1763937SThierry Reding 636880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 6376b6b6042SThierry Reding 638c1763937SThierry Reding /* start lane sequencer */ 639c1763937SThierry Reding value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 640c1763937SThierry Reding SOR_LANE_SEQ_CTL_POWER_STATE_UP; 641c1763937SThierry Reding tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 642c1763937SThierry Reding 643c1763937SThierry Reding timeout = jiffies + msecs_to_jiffies(250); 644c1763937SThierry Reding 645c1763937SThierry Reding while (time_before(jiffies, timeout)) { 646c1763937SThierry Reding value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 647c1763937SThierry Reding if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 648c1763937SThierry Reding break; 649c1763937SThierry Reding 650c1763937SThierry Reding usleep_range(250, 1000); 651c1763937SThierry Reding } 652c1763937SThierry Reding 653c1763937SThierry Reding if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 654c1763937SThierry Reding return -ETIMEDOUT; 655c1763937SThierry Reding 656c1763937SThierry Reding return 0; 657c1763937SThierry Reding } 658c1763937SThierry Reding 659c1763937SThierry Reding static int tegra_sor_power_down_lanes(struct tegra_sor *sor) 660c1763937SThierry Reding { 661c1763937SThierry Reding unsigned long timeout; 662c1763937SThierry Reding u32 value; 663c1763937SThierry Reding 664c1763937SThierry Reding /* power down all lanes */ 665880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 666c1763937SThierry Reding value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 667c1763937SThierry Reding SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); 668880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 6696b6b6042SThierry Reding 670c1763937SThierry Reding /* start lane sequencer */ 671c1763937SThierry Reding value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | 672c1763937SThierry Reding SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; 673c1763937SThierry Reding tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 674c1763937SThierry Reding 675c1763937SThierry Reding timeout = jiffies + msecs_to_jiffies(250); 676c1763937SThierry Reding 677c1763937SThierry Reding while (time_before(jiffies, timeout)) { 678c1763937SThierry Reding value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 679c1763937SThierry Reding if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 680c1763937SThierry Reding break; 681c1763937SThierry Reding 682c1763937SThierry Reding usleep_range(25, 100); 683c1763937SThierry Reding } 684c1763937SThierry Reding 685c1763937SThierry Reding if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 686c1763937SThierry Reding return -ETIMEDOUT; 687c1763937SThierry Reding 688c1763937SThierry Reding return 0; 689c1763937SThierry Reding } 690c1763937SThierry Reding 691c1763937SThierry Reding static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes) 692c1763937SThierry Reding { 693c1763937SThierry Reding u32 value; 694c1763937SThierry Reding 695c1763937SThierry Reding /* pre-charge all used lanes */ 696c1763937SThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 697c1763937SThierry Reding 698c1763937SThierry Reding if (lanes <= 2) 699c1763937SThierry Reding value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | 700c1763937SThierry Reding SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2])); 701c1763937SThierry Reding else 702c1763937SThierry Reding value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | 703c1763937SThierry Reding SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]); 704c1763937SThierry Reding 705c1763937SThierry Reding if (lanes <= 1) 706c1763937SThierry Reding value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); 707c1763937SThierry Reding else 708c1763937SThierry Reding value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); 709c1763937SThierry Reding 710c1763937SThierry Reding if (lanes == 0) 711c1763937SThierry Reding value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); 712c1763937SThierry Reding else 713c1763937SThierry Reding value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); 714c1763937SThierry Reding 715c1763937SThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 716c1763937SThierry Reding 717c1763937SThierry Reding usleep_range(15, 100); 7186b6b6042SThierry Reding 719880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 7206b6b6042SThierry Reding value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 7216b6b6042SThierry Reding SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); 722880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 7236b6b6042SThierry Reding } 7246b6b6042SThierry Reding 725c1763937SThierry Reding static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor) 726c1763937SThierry Reding { 727c1763937SThierry Reding u32 mask = 0x08, adj = 0, value; 7286b6b6042SThierry Reding 729c1763937SThierry Reding /* enable pad calibration logic */ 730c1763937SThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 731c1763937SThierry Reding value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 732c1763937SThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 7336b6b6042SThierry Reding 734c1763937SThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll1); 735c1763937SThierry Reding value |= SOR_PLL1_TMDS_TERM; 736c1763937SThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll1); 7376b6b6042SThierry Reding 738c1763937SThierry Reding while (mask) { 739c1763937SThierry Reding adj |= mask; 7406b6b6042SThierry Reding 741c1763937SThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll1); 742c1763937SThierry Reding value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 743c1763937SThierry Reding value |= SOR_PLL1_TMDS_TERMADJ(adj); 744c1763937SThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll1); 745c1763937SThierry Reding 746c1763937SThierry Reding usleep_range(100, 200); 747c1763937SThierry Reding 748c1763937SThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll1); 749c1763937SThierry Reding if (value & SOR_PLL1_TERM_COMPOUT) 750c1763937SThierry Reding adj &= ~mask; 751c1763937SThierry Reding 752c1763937SThierry Reding mask >>= 1; 7536b6b6042SThierry Reding } 7546b6b6042SThierry Reding 755c1763937SThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll1); 756c1763937SThierry Reding value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 757c1763937SThierry Reding value |= SOR_PLL1_TMDS_TERMADJ(adj); 758c1763937SThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll1); 7596b6b6042SThierry Reding 760c1763937SThierry Reding /* disable pad calibration logic */ 761c1763937SThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 762c1763937SThierry Reding value |= SOR_DP_PADCTL_PAD_CAL_PD; 763c1763937SThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 764c1763937SThierry Reding } 7656b6b6042SThierry Reding 766c1763937SThierry Reding static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link) 767c1763937SThierry Reding { 768c1763937SThierry Reding struct tegra_sor *sor = container_of(link, struct tegra_sor, link); 769c1763937SThierry Reding u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0; 770c1763937SThierry Reding const struct tegra_sor_soc *soc = sor->soc; 771c1763937SThierry Reding u32 pattern = 0, tx_pu = 0, value; 772c1763937SThierry Reding unsigned int i; 7736b6b6042SThierry Reding 774c1763937SThierry Reding for (value = 0, i = 0; i < link->lanes; i++) { 775c1763937SThierry Reding u8 vs = link->train.request.voltage_swing[i]; 776c1763937SThierry Reding u8 pe = link->train.request.pre_emphasis[i]; 777c1763937SThierry Reding u8 pc = link->train.request.post_cursor[i]; 778c1763937SThierry Reding u8 shift = sor->soc->lane_map[i] << 3; 779c1763937SThierry Reding 780c1763937SThierry Reding voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift; 781c1763937SThierry Reding pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift; 782c1763937SThierry Reding post_cursor |= soc->post_cursor[pc][vs][pe] << shift; 783c1763937SThierry Reding 784c1763937SThierry Reding if (sor->soc->tx_pu[pc][vs][pe] > tx_pu) 785c1763937SThierry Reding tx_pu = sor->soc->tx_pu[pc][vs][pe]; 786c1763937SThierry Reding 787c1763937SThierry Reding switch (link->train.pattern) { 788c1763937SThierry Reding case DP_TRAINING_PATTERN_DISABLE: 789c1763937SThierry Reding value = SOR_DP_TPG_SCRAMBLER_GALIOS | 7906b6b6042SThierry Reding SOR_DP_TPG_PATTERN_NONE; 791c1763937SThierry Reding break; 792c1763937SThierry Reding 793c1763937SThierry Reding case DP_TRAINING_PATTERN_1: 794c1763937SThierry Reding value = SOR_DP_TPG_SCRAMBLER_NONE | 795c1763937SThierry Reding SOR_DP_TPG_PATTERN_TRAIN1; 796c1763937SThierry Reding break; 797c1763937SThierry Reding 798c1763937SThierry Reding case DP_TRAINING_PATTERN_2: 799c1763937SThierry Reding value = SOR_DP_TPG_SCRAMBLER_NONE | 800c1763937SThierry Reding SOR_DP_TPG_PATTERN_TRAIN2; 801c1763937SThierry Reding break; 802c1763937SThierry Reding 803c1763937SThierry Reding case DP_TRAINING_PATTERN_3: 804c1763937SThierry Reding value = SOR_DP_TPG_SCRAMBLER_NONE | 805c1763937SThierry Reding SOR_DP_TPG_PATTERN_TRAIN3; 806c1763937SThierry Reding break; 807c1763937SThierry Reding 808c1763937SThierry Reding default: 809c1763937SThierry Reding return -EINVAL; 8106b6b6042SThierry Reding } 8116b6b6042SThierry Reding 812c1763937SThierry Reding if (link->caps.channel_coding) 813c1763937SThierry Reding value |= SOR_DP_TPG_CHANNEL_CODING; 8146b6b6042SThierry Reding 815c1763937SThierry Reding pattern = pattern << 8 | value; 816c1763937SThierry Reding } 8176b6b6042SThierry Reding 818c1763937SThierry Reding tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0); 819c1763937SThierry Reding tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0); 820c1763937SThierry Reding 821c1763937SThierry Reding if (link->caps.tps3_supported) 822c1763937SThierry Reding tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0); 823c1763937SThierry Reding 824c1763937SThierry Reding tegra_sor_writel(sor, pattern, SOR_DP_TPG); 825c1763937SThierry Reding 826c1763937SThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 827c1763937SThierry Reding value &= ~SOR_DP_PADCTL_TX_PU_MASK; 828c1763937SThierry Reding value |= SOR_DP_PADCTL_TX_PU_ENABLE; 829c1763937SThierry Reding value |= SOR_DP_PADCTL_TX_PU(tx_pu); 830c1763937SThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 831c1763937SThierry Reding 832c1763937SThierry Reding usleep_range(20, 100); 8336b6b6042SThierry Reding 8346b6b6042SThierry Reding return 0; 8356b6b6042SThierry Reding } 8366b6b6042SThierry Reding 837c1763937SThierry Reding static int tegra_sor_dp_link_configure(struct drm_dp_link *link) 838c1763937SThierry Reding { 839c1763937SThierry Reding struct tegra_sor *sor = container_of(link, struct tegra_sor, link); 840c1763937SThierry Reding unsigned int rate, lanes; 841c1763937SThierry Reding u32 value; 842c1763937SThierry Reding int err; 843c1763937SThierry Reding 844c1763937SThierry Reding rate = drm_dp_link_rate_to_bw_code(link->rate); 845c1763937SThierry Reding lanes = link->lanes; 846c1763937SThierry Reding 847c1763937SThierry Reding /* configure link speed and lane count */ 848c1763937SThierry Reding value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 849c1763937SThierry Reding value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 850c1763937SThierry Reding value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); 851c1763937SThierry Reding tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 852c1763937SThierry Reding 853c1763937SThierry Reding value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 854c1763937SThierry Reding value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 855c1763937SThierry Reding value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); 856c1763937SThierry Reding 857c1763937SThierry Reding if (link->caps.enhanced_framing) 858c1763937SThierry Reding value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 859c1763937SThierry Reding 860c1763937SThierry Reding tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 861c1763937SThierry Reding 862c1763937SThierry Reding usleep_range(400, 1000); 863c1763937SThierry Reding 864c1763937SThierry Reding /* configure load pulse position adjustment */ 865c1763937SThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll1); 866c1763937SThierry Reding value &= ~SOR_PLL1_LOADADJ_MASK; 867c1763937SThierry Reding 868c1763937SThierry Reding switch (rate) { 869c1763937SThierry Reding case DP_LINK_BW_1_62: 870c1763937SThierry Reding value |= SOR_PLL1_LOADADJ(0x3); 871c1763937SThierry Reding break; 872c1763937SThierry Reding 873c1763937SThierry Reding case DP_LINK_BW_2_7: 874c1763937SThierry Reding value |= SOR_PLL1_LOADADJ(0x4); 875c1763937SThierry Reding break; 876c1763937SThierry Reding 877c1763937SThierry Reding case DP_LINK_BW_5_4: 878c1763937SThierry Reding value |= SOR_PLL1_LOADADJ(0x6); 879c1763937SThierry Reding break; 880c1763937SThierry Reding } 881c1763937SThierry Reding 882c1763937SThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll1); 883c1763937SThierry Reding 884c1763937SThierry Reding /* use alternate scrambler reset for eDP */ 885c1763937SThierry Reding value = tegra_sor_readl(sor, SOR_DP_SPARE0); 886c1763937SThierry Reding 887c1763937SThierry Reding if (link->edp == 0) 888c1763937SThierry Reding value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 889c1763937SThierry Reding else 890c1763937SThierry Reding value |= SOR_DP_SPARE_PANEL_INTERNAL; 891c1763937SThierry Reding 892c1763937SThierry Reding tegra_sor_writel(sor, value, SOR_DP_SPARE0); 893c1763937SThierry Reding 894c1763937SThierry Reding err = tegra_sor_power_down_lanes(sor); 895c1763937SThierry Reding if (err < 0) { 896c1763937SThierry Reding dev_err(sor->dev, "failed to power down lanes: %d\n", err); 897c1763937SThierry Reding return err; 898c1763937SThierry Reding } 899c1763937SThierry Reding 900c1763937SThierry Reding /* power up and pre-charge lanes */ 901c1763937SThierry Reding err = tegra_sor_power_up_lanes(sor, lanes); 902c1763937SThierry Reding if (err < 0) { 903c1763937SThierry Reding dev_err(sor->dev, "failed to power up %u lane%s: %d\n", 904c1763937SThierry Reding lanes, (lanes != 1) ? "s" : "", err); 905c1763937SThierry Reding return err; 906c1763937SThierry Reding } 907c1763937SThierry Reding 908c1763937SThierry Reding tegra_sor_dp_precharge(sor, lanes); 909c1763937SThierry Reding 910c1763937SThierry Reding return 0; 911c1763937SThierry Reding } 912c1763937SThierry Reding 913c1763937SThierry Reding static const struct drm_dp_link_ops tegra_sor_dp_link_ops = { 914c1763937SThierry Reding .apply_training = tegra_sor_dp_link_apply_training, 915c1763937SThierry Reding .configure = tegra_sor_dp_link_configure, 916c1763937SThierry Reding }; 917c1763937SThierry Reding 9186b6b6042SThierry Reding static void tegra_sor_super_update(struct tegra_sor *sor) 9196b6b6042SThierry Reding { 920a9a9e4fdSThierry Reding tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 921a9a9e4fdSThierry Reding tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); 922a9a9e4fdSThierry Reding tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 9236b6b6042SThierry Reding } 9246b6b6042SThierry Reding 9256b6b6042SThierry Reding static void tegra_sor_update(struct tegra_sor *sor) 9266b6b6042SThierry Reding { 927a9a9e4fdSThierry Reding tegra_sor_writel(sor, 0, SOR_STATE0); 928a9a9e4fdSThierry Reding tegra_sor_writel(sor, 1, SOR_STATE0); 929a9a9e4fdSThierry Reding tegra_sor_writel(sor, 0, SOR_STATE0); 9306b6b6042SThierry Reding } 9316b6b6042SThierry Reding 9326b6b6042SThierry Reding static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) 9336b6b6042SThierry Reding { 93428fe2076SThierry Reding u32 value; 9356b6b6042SThierry Reding 9366b6b6042SThierry Reding value = tegra_sor_readl(sor, SOR_PWM_DIV); 9376b6b6042SThierry Reding value &= ~SOR_PWM_DIV_MASK; 9386b6b6042SThierry Reding value |= 0x400; /* period */ 9396b6b6042SThierry Reding tegra_sor_writel(sor, value, SOR_PWM_DIV); 9406b6b6042SThierry Reding 9416b6b6042SThierry Reding value = tegra_sor_readl(sor, SOR_PWM_CTL); 9426b6b6042SThierry Reding value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; 9436b6b6042SThierry Reding value |= 0x400; /* duty cycle */ 9446b6b6042SThierry Reding value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ 9456b6b6042SThierry Reding value |= SOR_PWM_CTL_TRIGGER; 9466b6b6042SThierry Reding tegra_sor_writel(sor, value, SOR_PWM_CTL); 9476b6b6042SThierry Reding 9486b6b6042SThierry Reding timeout = jiffies + msecs_to_jiffies(timeout); 9496b6b6042SThierry Reding 9506b6b6042SThierry Reding while (time_before(jiffies, timeout)) { 9516b6b6042SThierry Reding value = tegra_sor_readl(sor, SOR_PWM_CTL); 9526b6b6042SThierry Reding if ((value & SOR_PWM_CTL_TRIGGER) == 0) 9536b6b6042SThierry Reding return 0; 9546b6b6042SThierry Reding 9556b6b6042SThierry Reding usleep_range(25, 100); 9566b6b6042SThierry Reding } 9576b6b6042SThierry Reding 9586b6b6042SThierry Reding return -ETIMEDOUT; 9596b6b6042SThierry Reding } 9606b6b6042SThierry Reding 9616b6b6042SThierry Reding static int tegra_sor_attach(struct tegra_sor *sor) 9626b6b6042SThierry Reding { 9636b6b6042SThierry Reding unsigned long value, timeout; 9646b6b6042SThierry Reding 9656b6b6042SThierry Reding /* wake up in normal mode */ 966a9a9e4fdSThierry Reding value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 9676b6b6042SThierry Reding value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; 9686b6b6042SThierry Reding value |= SOR_SUPER_STATE_MODE_NORMAL; 969a9a9e4fdSThierry Reding tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 9706b6b6042SThierry Reding tegra_sor_super_update(sor); 9716b6b6042SThierry Reding 9726b6b6042SThierry Reding /* attach */ 973a9a9e4fdSThierry Reding value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 9746b6b6042SThierry Reding value |= SOR_SUPER_STATE_ATTACHED; 975a9a9e4fdSThierry Reding tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 9766b6b6042SThierry Reding tegra_sor_super_update(sor); 9776b6b6042SThierry Reding 9786b6b6042SThierry Reding timeout = jiffies + msecs_to_jiffies(250); 9796b6b6042SThierry Reding 9806b6b6042SThierry Reding while (time_before(jiffies, timeout)) { 9816b6b6042SThierry Reding value = tegra_sor_readl(sor, SOR_TEST); 9826b6b6042SThierry Reding if ((value & SOR_TEST_ATTACHED) != 0) 9836b6b6042SThierry Reding return 0; 9846b6b6042SThierry Reding 9856b6b6042SThierry Reding usleep_range(25, 100); 9866b6b6042SThierry Reding } 9876b6b6042SThierry Reding 9886b6b6042SThierry Reding return -ETIMEDOUT; 9896b6b6042SThierry Reding } 9906b6b6042SThierry Reding 9916b6b6042SThierry Reding static int tegra_sor_wakeup(struct tegra_sor *sor) 9926b6b6042SThierry Reding { 9936b6b6042SThierry Reding unsigned long value, timeout; 9946b6b6042SThierry Reding 9956b6b6042SThierry Reding timeout = jiffies + msecs_to_jiffies(250); 9966b6b6042SThierry Reding 9976b6b6042SThierry Reding /* wait for head to wake up */ 9986b6b6042SThierry Reding while (time_before(jiffies, timeout)) { 9996b6b6042SThierry Reding value = tegra_sor_readl(sor, SOR_TEST); 10006b6b6042SThierry Reding value &= SOR_TEST_HEAD_MODE_MASK; 10016b6b6042SThierry Reding 10026b6b6042SThierry Reding if (value == SOR_TEST_HEAD_MODE_AWAKE) 10036b6b6042SThierry Reding return 0; 10046b6b6042SThierry Reding 10056b6b6042SThierry Reding usleep_range(25, 100); 10066b6b6042SThierry Reding } 10076b6b6042SThierry Reding 10086b6b6042SThierry Reding return -ETIMEDOUT; 10096b6b6042SThierry Reding } 10106b6b6042SThierry Reding 10116b6b6042SThierry Reding static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) 10126b6b6042SThierry Reding { 101328fe2076SThierry Reding u32 value; 10146b6b6042SThierry Reding 10156b6b6042SThierry Reding value = tegra_sor_readl(sor, SOR_PWR); 10166b6b6042SThierry Reding value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; 10176b6b6042SThierry Reding tegra_sor_writel(sor, value, SOR_PWR); 10186b6b6042SThierry Reding 10196b6b6042SThierry Reding timeout = jiffies + msecs_to_jiffies(timeout); 10206b6b6042SThierry Reding 10216b6b6042SThierry Reding while (time_before(jiffies, timeout)) { 10226b6b6042SThierry Reding value = tegra_sor_readl(sor, SOR_PWR); 10236b6b6042SThierry Reding if ((value & SOR_PWR_TRIGGER) == 0) 10246b6b6042SThierry Reding return 0; 10256b6b6042SThierry Reding 10266b6b6042SThierry Reding usleep_range(25, 100); 10276b6b6042SThierry Reding } 10286b6b6042SThierry Reding 10296b6b6042SThierry Reding return -ETIMEDOUT; 10306b6b6042SThierry Reding } 10316b6b6042SThierry Reding 103234fa183bSThierry Reding struct tegra_sor_params { 103334fa183bSThierry Reding /* number of link clocks per line */ 103434fa183bSThierry Reding unsigned int num_clocks; 103534fa183bSThierry Reding /* ratio between input and output */ 103634fa183bSThierry Reding u64 ratio; 103734fa183bSThierry Reding /* precision factor */ 103834fa183bSThierry Reding u64 precision; 103934fa183bSThierry Reding 104034fa183bSThierry Reding unsigned int active_polarity; 104134fa183bSThierry Reding unsigned int active_count; 104234fa183bSThierry Reding unsigned int active_frac; 104334fa183bSThierry Reding unsigned int tu_size; 104434fa183bSThierry Reding unsigned int error; 104534fa183bSThierry Reding }; 104634fa183bSThierry Reding 104734fa183bSThierry Reding static int tegra_sor_compute_params(struct tegra_sor *sor, 104834fa183bSThierry Reding struct tegra_sor_params *params, 104934fa183bSThierry Reding unsigned int tu_size) 105034fa183bSThierry Reding { 105134fa183bSThierry Reding u64 active_sym, active_count, frac, approx; 105234fa183bSThierry Reding u32 active_polarity, active_frac = 0; 105334fa183bSThierry Reding const u64 f = params->precision; 105434fa183bSThierry Reding s64 error; 105534fa183bSThierry Reding 105634fa183bSThierry Reding active_sym = params->ratio * tu_size; 105734fa183bSThierry Reding active_count = div_u64(active_sym, f) * f; 105834fa183bSThierry Reding frac = active_sym - active_count; 105934fa183bSThierry Reding 106034fa183bSThierry Reding /* fraction < 0.5 */ 106134fa183bSThierry Reding if (frac >= (f / 2)) { 106234fa183bSThierry Reding active_polarity = 1; 106334fa183bSThierry Reding frac = f - frac; 106434fa183bSThierry Reding } else { 106534fa183bSThierry Reding active_polarity = 0; 106634fa183bSThierry Reding } 106734fa183bSThierry Reding 106834fa183bSThierry Reding if (frac != 0) { 106934fa183bSThierry Reding frac = div_u64(f * f, frac); /* 1/fraction */ 107034fa183bSThierry Reding if (frac <= (15 * f)) { 107134fa183bSThierry Reding active_frac = div_u64(frac, f); 107234fa183bSThierry Reding 107334fa183bSThierry Reding /* round up */ 107434fa183bSThierry Reding if (active_polarity) 107534fa183bSThierry Reding active_frac++; 107634fa183bSThierry Reding } else { 107734fa183bSThierry Reding active_frac = active_polarity ? 1 : 15; 107834fa183bSThierry Reding } 107934fa183bSThierry Reding } 108034fa183bSThierry Reding 108134fa183bSThierry Reding if (active_frac == 1) 108234fa183bSThierry Reding active_polarity = 0; 108334fa183bSThierry Reding 108434fa183bSThierry Reding if (active_polarity == 1) { 108534fa183bSThierry Reding if (active_frac) { 108634fa183bSThierry Reding approx = active_count + (active_frac * (f - 1)) * f; 108734fa183bSThierry Reding approx = div_u64(approx, active_frac * f); 108834fa183bSThierry Reding } else { 108934fa183bSThierry Reding approx = active_count + f; 109034fa183bSThierry Reding } 109134fa183bSThierry Reding } else { 109234fa183bSThierry Reding if (active_frac) 109334fa183bSThierry Reding approx = active_count + div_u64(f, active_frac); 109434fa183bSThierry Reding else 109534fa183bSThierry Reding approx = active_count; 109634fa183bSThierry Reding } 109734fa183bSThierry Reding 109834fa183bSThierry Reding error = div_s64(active_sym - approx, tu_size); 109934fa183bSThierry Reding error *= params->num_clocks; 110034fa183bSThierry Reding 110179211c8eSAndrew Morton if (error <= 0 && abs(error) < params->error) { 110234fa183bSThierry Reding params->active_count = div_u64(active_count, f); 110334fa183bSThierry Reding params->active_polarity = active_polarity; 110434fa183bSThierry Reding params->active_frac = active_frac; 110579211c8eSAndrew Morton params->error = abs(error); 110634fa183bSThierry Reding params->tu_size = tu_size; 110734fa183bSThierry Reding 110834fa183bSThierry Reding if (error == 0) 110934fa183bSThierry Reding return true; 111034fa183bSThierry Reding } 111134fa183bSThierry Reding 111234fa183bSThierry Reding return false; 111334fa183bSThierry Reding } 111434fa183bSThierry Reding 1115a198359eSThierry Reding static int tegra_sor_compute_config(struct tegra_sor *sor, 111680444495SThierry Reding const struct drm_display_mode *mode, 111734fa183bSThierry Reding struct tegra_sor_config *config, 111834fa183bSThierry Reding struct drm_dp_link *link) 111934fa183bSThierry Reding { 112034fa183bSThierry Reding const u64 f = 100000, link_rate = link->rate * 1000; 112134fa183bSThierry Reding const u64 pclk = mode->clock * 1000; 11227890b576SThierry Reding u64 input, output, watermark, num; 112334fa183bSThierry Reding struct tegra_sor_params params; 112434fa183bSThierry Reding u32 num_syms_per_line; 112534fa183bSThierry Reding unsigned int i; 112634fa183bSThierry Reding 1127c728e2d4SThierry Reding if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel) 112834fa183bSThierry Reding return -EINVAL; 112934fa183bSThierry Reding 113034fa183bSThierry Reding input = pclk * config->bits_per_pixel; 1131c728e2d4SThierry Reding output = link_rate * 8 * link->lanes; 113234fa183bSThierry Reding 113334fa183bSThierry Reding if (input >= output) 113434fa183bSThierry Reding return -ERANGE; 113534fa183bSThierry Reding 113634fa183bSThierry Reding memset(¶ms, 0, sizeof(params)); 113734fa183bSThierry Reding params.ratio = div64_u64(input * f, output); 113834fa183bSThierry Reding params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); 113934fa183bSThierry Reding params.precision = f; 114034fa183bSThierry Reding params.error = 64 * f; 114134fa183bSThierry Reding params.tu_size = 64; 114234fa183bSThierry Reding 114334fa183bSThierry Reding for (i = params.tu_size; i >= 32; i--) 114434fa183bSThierry Reding if (tegra_sor_compute_params(sor, ¶ms, i)) 114534fa183bSThierry Reding break; 114634fa183bSThierry Reding 114734fa183bSThierry Reding if (params.active_frac == 0) { 114834fa183bSThierry Reding config->active_polarity = 0; 114934fa183bSThierry Reding config->active_count = params.active_count; 115034fa183bSThierry Reding 115134fa183bSThierry Reding if (!params.active_polarity) 115234fa183bSThierry Reding config->active_count--; 115334fa183bSThierry Reding 115434fa183bSThierry Reding config->tu_size = params.tu_size; 115534fa183bSThierry Reding config->active_frac = 1; 115634fa183bSThierry Reding } else { 115734fa183bSThierry Reding config->active_polarity = params.active_polarity; 115834fa183bSThierry Reding config->active_count = params.active_count; 115934fa183bSThierry Reding config->active_frac = params.active_frac; 116034fa183bSThierry Reding config->tu_size = params.tu_size; 116134fa183bSThierry Reding } 116234fa183bSThierry Reding 116334fa183bSThierry Reding dev_dbg(sor->dev, 116434fa183bSThierry Reding "polarity: %d active count: %d tu size: %d active frac: %d\n", 116534fa183bSThierry Reding config->active_polarity, config->active_count, 116634fa183bSThierry Reding config->tu_size, config->active_frac); 116734fa183bSThierry Reding 116834fa183bSThierry Reding watermark = params.ratio * config->tu_size * (f - params.ratio); 116934fa183bSThierry Reding watermark = div_u64(watermark, f); 117034fa183bSThierry Reding 117134fa183bSThierry Reding watermark = div_u64(watermark + params.error, f); 117234fa183bSThierry Reding config->watermark = watermark + (config->bits_per_pixel / 8) + 2; 117334fa183bSThierry Reding num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * 1174c728e2d4SThierry Reding (link->lanes * 8); 117534fa183bSThierry Reding 117634fa183bSThierry Reding if (config->watermark > 30) { 117734fa183bSThierry Reding config->watermark = 30; 117834fa183bSThierry Reding dev_err(sor->dev, 117934fa183bSThierry Reding "unable to compute TU size, forcing watermark to %u\n", 118034fa183bSThierry Reding config->watermark); 118134fa183bSThierry Reding } else if (config->watermark > num_syms_per_line) { 118234fa183bSThierry Reding config->watermark = num_syms_per_line; 118334fa183bSThierry Reding dev_err(sor->dev, "watermark too high, forcing to %u\n", 118434fa183bSThierry Reding config->watermark); 118534fa183bSThierry Reding } 118634fa183bSThierry Reding 11877890b576SThierry Reding /* compute the number of symbols per horizontal blanking interval */ 11887890b576SThierry Reding num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; 11897890b576SThierry Reding config->hblank_symbols = div_u64(num, pclk); 11907890b576SThierry Reding 119127ba465cSThierry Reding if (link->caps.enhanced_framing) 11927890b576SThierry Reding config->hblank_symbols -= 3; 11937890b576SThierry Reding 1194c728e2d4SThierry Reding config->hblank_symbols -= 12 / link->lanes; 11957890b576SThierry Reding 11967890b576SThierry Reding /* compute the number of symbols per vertical blanking interval */ 11977890b576SThierry Reding num = (mode->hdisplay - 25) * link_rate; 11987890b576SThierry Reding config->vblank_symbols = div_u64(num, pclk); 1199c728e2d4SThierry Reding config->vblank_symbols -= 36 / link->lanes + 4; 12007890b576SThierry Reding 12017890b576SThierry Reding dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, 12027890b576SThierry Reding config->vblank_symbols); 12037890b576SThierry Reding 120434fa183bSThierry Reding return 0; 120534fa183bSThierry Reding } 120634fa183bSThierry Reding 1207402f6bcdSThierry Reding static void tegra_sor_apply_config(struct tegra_sor *sor, 1208402f6bcdSThierry Reding const struct tegra_sor_config *config) 1209402f6bcdSThierry Reding { 1210402f6bcdSThierry Reding u32 value; 1211402f6bcdSThierry Reding 1212402f6bcdSThierry Reding value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1213402f6bcdSThierry Reding value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; 1214402f6bcdSThierry Reding value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); 1215402f6bcdSThierry Reding tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1216402f6bcdSThierry Reding 1217402f6bcdSThierry Reding value = tegra_sor_readl(sor, SOR_DP_CONFIG0); 1218402f6bcdSThierry Reding value &= ~SOR_DP_CONFIG_WATERMARK_MASK; 1219402f6bcdSThierry Reding value |= SOR_DP_CONFIG_WATERMARK(config->watermark); 1220402f6bcdSThierry Reding 1221402f6bcdSThierry Reding value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; 1222402f6bcdSThierry Reding value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); 1223402f6bcdSThierry Reding 1224402f6bcdSThierry Reding value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; 1225402f6bcdSThierry Reding value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); 1226402f6bcdSThierry Reding 1227402f6bcdSThierry Reding if (config->active_polarity) 1228402f6bcdSThierry Reding value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 1229402f6bcdSThierry Reding else 1230402f6bcdSThierry Reding value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 1231402f6bcdSThierry Reding 1232402f6bcdSThierry Reding value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; 1233402f6bcdSThierry Reding value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; 1234402f6bcdSThierry Reding tegra_sor_writel(sor, value, SOR_DP_CONFIG0); 1235402f6bcdSThierry Reding 1236402f6bcdSThierry Reding value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); 1237402f6bcdSThierry Reding value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; 1238402f6bcdSThierry Reding value |= config->hblank_symbols & 0xffff; 1239402f6bcdSThierry Reding tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); 1240402f6bcdSThierry Reding 1241402f6bcdSThierry Reding value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); 1242402f6bcdSThierry Reding value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; 1243402f6bcdSThierry Reding value |= config->vblank_symbols & 0xffff; 1244402f6bcdSThierry Reding tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); 1245402f6bcdSThierry Reding } 1246402f6bcdSThierry Reding 12472bd1dd39SThierry Reding static void tegra_sor_mode_set(struct tegra_sor *sor, 12482bd1dd39SThierry Reding const struct drm_display_mode *mode, 1249c31efa7aSThierry Reding struct tegra_sor_state *state) 12502bd1dd39SThierry Reding { 12512bd1dd39SThierry Reding struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); 12522bd1dd39SThierry Reding unsigned int vbe, vse, hbe, hse, vbs, hbs; 12532bd1dd39SThierry Reding u32 value; 12542bd1dd39SThierry Reding 12552bd1dd39SThierry Reding value = tegra_sor_readl(sor, SOR_STATE1); 12562bd1dd39SThierry Reding value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; 12572bd1dd39SThierry Reding value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 12582bd1dd39SThierry Reding value &= ~SOR_STATE_ASY_OWNER_MASK; 12592bd1dd39SThierry Reding 12602bd1dd39SThierry Reding value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | 12612bd1dd39SThierry Reding SOR_STATE_ASY_OWNER(dc->pipe + 1); 12622bd1dd39SThierry Reding 12632bd1dd39SThierry Reding if (mode->flags & DRM_MODE_FLAG_PHSYNC) 12642bd1dd39SThierry Reding value &= ~SOR_STATE_ASY_HSYNCPOL; 12652bd1dd39SThierry Reding 12662bd1dd39SThierry Reding if (mode->flags & DRM_MODE_FLAG_NHSYNC) 12672bd1dd39SThierry Reding value |= SOR_STATE_ASY_HSYNCPOL; 12682bd1dd39SThierry Reding 12692bd1dd39SThierry Reding if (mode->flags & DRM_MODE_FLAG_PVSYNC) 12702bd1dd39SThierry Reding value &= ~SOR_STATE_ASY_VSYNCPOL; 12712bd1dd39SThierry Reding 12722bd1dd39SThierry Reding if (mode->flags & DRM_MODE_FLAG_NVSYNC) 12732bd1dd39SThierry Reding value |= SOR_STATE_ASY_VSYNCPOL; 12742bd1dd39SThierry Reding 1275c31efa7aSThierry Reding switch (state->bpc) { 1276c31efa7aSThierry Reding case 16: 1277c31efa7aSThierry Reding value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; 1278c31efa7aSThierry Reding break; 1279c31efa7aSThierry Reding 1280c31efa7aSThierry Reding case 12: 1281c31efa7aSThierry Reding value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; 1282c31efa7aSThierry Reding break; 1283c31efa7aSThierry Reding 1284c31efa7aSThierry Reding case 10: 1285c31efa7aSThierry Reding value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; 1286c31efa7aSThierry Reding break; 1287c31efa7aSThierry Reding 12882bd1dd39SThierry Reding case 8: 12892bd1dd39SThierry Reding value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 12902bd1dd39SThierry Reding break; 12912bd1dd39SThierry Reding 12922bd1dd39SThierry Reding case 6: 12932bd1dd39SThierry Reding value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; 12942bd1dd39SThierry Reding break; 12952bd1dd39SThierry Reding 12962bd1dd39SThierry Reding default: 1297c31efa7aSThierry Reding value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 12982bd1dd39SThierry Reding break; 12992bd1dd39SThierry Reding } 13002bd1dd39SThierry Reding 13012bd1dd39SThierry Reding tegra_sor_writel(sor, value, SOR_STATE1); 13022bd1dd39SThierry Reding 13032bd1dd39SThierry Reding /* 13042bd1dd39SThierry Reding * TODO: The video timing programming below doesn't seem to match the 13052bd1dd39SThierry Reding * register definitions. 13062bd1dd39SThierry Reding */ 13072bd1dd39SThierry Reding 13082bd1dd39SThierry Reding value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); 1309880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); 13102bd1dd39SThierry Reding 13112bd1dd39SThierry Reding /* sync end = sync width - 1 */ 13122bd1dd39SThierry Reding vse = mode->vsync_end - mode->vsync_start - 1; 13132bd1dd39SThierry Reding hse = mode->hsync_end - mode->hsync_start - 1; 13142bd1dd39SThierry Reding 13152bd1dd39SThierry Reding value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); 1316880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); 13172bd1dd39SThierry Reding 13182bd1dd39SThierry Reding /* blank end = sync end + back porch */ 13192bd1dd39SThierry Reding vbe = vse + (mode->vtotal - mode->vsync_end); 13202bd1dd39SThierry Reding hbe = hse + (mode->htotal - mode->hsync_end); 13212bd1dd39SThierry Reding 13222bd1dd39SThierry Reding value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); 1323880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); 13242bd1dd39SThierry Reding 13252bd1dd39SThierry Reding /* blank start = blank end + active */ 13262bd1dd39SThierry Reding vbs = vbe + mode->vdisplay; 13272bd1dd39SThierry Reding hbs = hbe + mode->hdisplay; 13282bd1dd39SThierry Reding 13292bd1dd39SThierry Reding value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); 1330880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); 13312bd1dd39SThierry Reding 13322bd1dd39SThierry Reding /* XXX interlacing support */ 1333880cee0bSThierry Reding tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); 13342bd1dd39SThierry Reding } 13352bd1dd39SThierry Reding 13366fad8f66SThierry Reding static int tegra_sor_detach(struct tegra_sor *sor) 13376b6b6042SThierry Reding { 13386fad8f66SThierry Reding unsigned long value, timeout; 13396fad8f66SThierry Reding 13406fad8f66SThierry Reding /* switch to safe mode */ 1341a9a9e4fdSThierry Reding value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 13426fad8f66SThierry Reding value &= ~SOR_SUPER_STATE_MODE_NORMAL; 1343a9a9e4fdSThierry Reding tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 13446fad8f66SThierry Reding tegra_sor_super_update(sor); 13456fad8f66SThierry Reding 13466fad8f66SThierry Reding timeout = jiffies + msecs_to_jiffies(250); 13476fad8f66SThierry Reding 13486fad8f66SThierry Reding while (time_before(jiffies, timeout)) { 13496fad8f66SThierry Reding value = tegra_sor_readl(sor, SOR_PWR); 13506fad8f66SThierry Reding if (value & SOR_PWR_MODE_SAFE) 13516fad8f66SThierry Reding break; 13526fad8f66SThierry Reding } 13536fad8f66SThierry Reding 13546fad8f66SThierry Reding if ((value & SOR_PWR_MODE_SAFE) == 0) 13556fad8f66SThierry Reding return -ETIMEDOUT; 13566fad8f66SThierry Reding 13576fad8f66SThierry Reding /* go to sleep */ 1358a9a9e4fdSThierry Reding value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 13596fad8f66SThierry Reding value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; 1360a9a9e4fdSThierry Reding tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 13616fad8f66SThierry Reding tegra_sor_super_update(sor); 13626fad8f66SThierry Reding 13636fad8f66SThierry Reding /* detach */ 1364a9a9e4fdSThierry Reding value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 13656fad8f66SThierry Reding value &= ~SOR_SUPER_STATE_ATTACHED; 1366a9a9e4fdSThierry Reding tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 13676fad8f66SThierry Reding tegra_sor_super_update(sor); 13686fad8f66SThierry Reding 13696fad8f66SThierry Reding timeout = jiffies + msecs_to_jiffies(250); 13706fad8f66SThierry Reding 13716fad8f66SThierry Reding while (time_before(jiffies, timeout)) { 13726fad8f66SThierry Reding value = tegra_sor_readl(sor, SOR_TEST); 13736fad8f66SThierry Reding if ((value & SOR_TEST_ATTACHED) == 0) 13746fad8f66SThierry Reding break; 13756fad8f66SThierry Reding 13766fad8f66SThierry Reding usleep_range(25, 100); 13776fad8f66SThierry Reding } 13786fad8f66SThierry Reding 13796fad8f66SThierry Reding if ((value & SOR_TEST_ATTACHED) != 0) 13806fad8f66SThierry Reding return -ETIMEDOUT; 13816fad8f66SThierry Reding 13826fad8f66SThierry Reding return 0; 13836fad8f66SThierry Reding } 13846fad8f66SThierry Reding 13856fad8f66SThierry Reding static int tegra_sor_power_down(struct tegra_sor *sor) 13866fad8f66SThierry Reding { 13876fad8f66SThierry Reding unsigned long value, timeout; 13886fad8f66SThierry Reding int err; 13896fad8f66SThierry Reding 13906fad8f66SThierry Reding value = tegra_sor_readl(sor, SOR_PWR); 13916fad8f66SThierry Reding value &= ~SOR_PWR_NORMAL_STATE_PU; 13926fad8f66SThierry Reding value |= SOR_PWR_TRIGGER; 13936fad8f66SThierry Reding tegra_sor_writel(sor, value, SOR_PWR); 13946fad8f66SThierry Reding 13956fad8f66SThierry Reding timeout = jiffies + msecs_to_jiffies(250); 13966fad8f66SThierry Reding 13976fad8f66SThierry Reding while (time_before(jiffies, timeout)) { 13986fad8f66SThierry Reding value = tegra_sor_readl(sor, SOR_PWR); 13996fad8f66SThierry Reding if ((value & SOR_PWR_TRIGGER) == 0) 14006fad8f66SThierry Reding return 0; 14016fad8f66SThierry Reding 14026fad8f66SThierry Reding usleep_range(25, 100); 14036fad8f66SThierry Reding } 14046fad8f66SThierry Reding 14056fad8f66SThierry Reding if ((value & SOR_PWR_TRIGGER) != 0) 14066fad8f66SThierry Reding return -ETIMEDOUT; 14076fad8f66SThierry Reding 140825bb2cecSThierry Reding /* switch to safe parent clock */ 140925bb2cecSThierry Reding err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 1410e1335e2fSThierry Reding if (err < 0) { 14116fad8f66SThierry Reding dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 1412e1335e2fSThierry Reding return err; 1413e1335e2fSThierry Reding } 14146fad8f66SThierry Reding 1415880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1416a9a9e4fdSThierry Reding value |= SOR_PLL2_PORT_POWERDOWN; 1417880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll2); 14186fad8f66SThierry Reding 14196fad8f66SThierry Reding usleep_range(20, 100); 14206fad8f66SThierry Reding 1421880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll0); 1422a9a9e4fdSThierry Reding value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 1423880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll0); 14246fad8f66SThierry Reding 1425880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1426a9a9e4fdSThierry Reding value |= SOR_PLL2_SEQ_PLLCAPPD; 1427a9a9e4fdSThierry Reding value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1428880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll2); 14296fad8f66SThierry Reding 14306fad8f66SThierry Reding usleep_range(20, 100); 14316fad8f66SThierry Reding 14326fad8f66SThierry Reding return 0; 14336fad8f66SThierry Reding } 14346fad8f66SThierry Reding 14356fad8f66SThierry Reding static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) 14366fad8f66SThierry Reding { 14376fad8f66SThierry Reding u32 value; 14386fad8f66SThierry Reding 14396fad8f66SThierry Reding timeout = jiffies + msecs_to_jiffies(timeout); 14406fad8f66SThierry Reding 14416fad8f66SThierry Reding while (time_before(jiffies, timeout)) { 1442a9a9e4fdSThierry Reding value = tegra_sor_readl(sor, SOR_CRCA); 1443a9a9e4fdSThierry Reding if (value & SOR_CRCA_VALID) 14446fad8f66SThierry Reding return 0; 14456fad8f66SThierry Reding 14466fad8f66SThierry Reding usleep_range(100, 200); 14476fad8f66SThierry Reding } 14486fad8f66SThierry Reding 14496fad8f66SThierry Reding return -ETIMEDOUT; 14506fad8f66SThierry Reding } 14516fad8f66SThierry Reding 1452530239a8SThierry Reding static int tegra_sor_show_crc(struct seq_file *s, void *data) 14536fad8f66SThierry Reding { 1454530239a8SThierry Reding struct drm_info_node *node = s->private; 1455530239a8SThierry Reding struct tegra_sor *sor = node->info_ent->data; 1456850bab44SThierry Reding struct drm_crtc *crtc = sor->output.encoder.crtc; 1457850bab44SThierry Reding struct drm_device *drm = node->minor->dev; 1458530239a8SThierry Reding int err = 0; 14596fad8f66SThierry Reding u32 value; 14606fad8f66SThierry Reding 1461850bab44SThierry Reding drm_modeset_lock_all(drm); 14626fad8f66SThierry Reding 1463850bab44SThierry Reding if (!crtc || !crtc->state->active) { 1464850bab44SThierry Reding err = -EBUSY; 14656fad8f66SThierry Reding goto unlock; 14666fad8f66SThierry Reding } 14676fad8f66SThierry Reding 1468a9a9e4fdSThierry Reding value = tegra_sor_readl(sor, SOR_STATE1); 14696fad8f66SThierry Reding value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1470a9a9e4fdSThierry Reding tegra_sor_writel(sor, value, SOR_STATE1); 14716fad8f66SThierry Reding 14726fad8f66SThierry Reding value = tegra_sor_readl(sor, SOR_CRC_CNTRL); 14736fad8f66SThierry Reding value |= SOR_CRC_CNTRL_ENABLE; 14746fad8f66SThierry Reding tegra_sor_writel(sor, value, SOR_CRC_CNTRL); 14756fad8f66SThierry Reding 14766fad8f66SThierry Reding value = tegra_sor_readl(sor, SOR_TEST); 14776fad8f66SThierry Reding value &= ~SOR_TEST_CRC_POST_SERIALIZE; 14786fad8f66SThierry Reding tegra_sor_writel(sor, value, SOR_TEST); 14796fad8f66SThierry Reding 14806fad8f66SThierry Reding err = tegra_sor_crc_wait(sor, 100); 14816fad8f66SThierry Reding if (err < 0) 14826fad8f66SThierry Reding goto unlock; 14836fad8f66SThierry Reding 1484a9a9e4fdSThierry Reding tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); 1485a9a9e4fdSThierry Reding value = tegra_sor_readl(sor, SOR_CRCB); 14866fad8f66SThierry Reding 1487530239a8SThierry Reding seq_printf(s, "%08x\n", value); 14886fad8f66SThierry Reding 14896fad8f66SThierry Reding unlock: 1490850bab44SThierry Reding drm_modeset_unlock_all(drm); 14916fad8f66SThierry Reding return err; 14926fad8f66SThierry Reding } 14936fad8f66SThierry Reding 1494062f5b2cSThierry Reding #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 1495062f5b2cSThierry Reding 1496062f5b2cSThierry Reding static const struct debugfs_reg32 tegra_sor_regs[] = { 1497062f5b2cSThierry Reding DEBUGFS_REG32(SOR_CTXSW), 1498062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SUPER_STATE0), 1499062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SUPER_STATE1), 1500062f5b2cSThierry Reding DEBUGFS_REG32(SOR_STATE0), 1501062f5b2cSThierry Reding DEBUGFS_REG32(SOR_STATE1), 1502062f5b2cSThierry Reding DEBUGFS_REG32(SOR_HEAD_STATE0(0)), 1503062f5b2cSThierry Reding DEBUGFS_REG32(SOR_HEAD_STATE0(1)), 1504062f5b2cSThierry Reding DEBUGFS_REG32(SOR_HEAD_STATE1(0)), 1505062f5b2cSThierry Reding DEBUGFS_REG32(SOR_HEAD_STATE1(1)), 1506062f5b2cSThierry Reding DEBUGFS_REG32(SOR_HEAD_STATE2(0)), 1507062f5b2cSThierry Reding DEBUGFS_REG32(SOR_HEAD_STATE2(1)), 1508062f5b2cSThierry Reding DEBUGFS_REG32(SOR_HEAD_STATE3(0)), 1509062f5b2cSThierry Reding DEBUGFS_REG32(SOR_HEAD_STATE3(1)), 1510062f5b2cSThierry Reding DEBUGFS_REG32(SOR_HEAD_STATE4(0)), 1511062f5b2cSThierry Reding DEBUGFS_REG32(SOR_HEAD_STATE4(1)), 1512062f5b2cSThierry Reding DEBUGFS_REG32(SOR_HEAD_STATE5(0)), 1513062f5b2cSThierry Reding DEBUGFS_REG32(SOR_HEAD_STATE5(1)), 1514062f5b2cSThierry Reding DEBUGFS_REG32(SOR_CRC_CNTRL), 1515062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_DEBUG_MVID), 1516062f5b2cSThierry Reding DEBUGFS_REG32(SOR_CLK_CNTRL), 1517062f5b2cSThierry Reding DEBUGFS_REG32(SOR_CAP), 1518062f5b2cSThierry Reding DEBUGFS_REG32(SOR_PWR), 1519062f5b2cSThierry Reding DEBUGFS_REG32(SOR_TEST), 1520062f5b2cSThierry Reding DEBUGFS_REG32(SOR_PLL0), 1521062f5b2cSThierry Reding DEBUGFS_REG32(SOR_PLL1), 1522062f5b2cSThierry Reding DEBUGFS_REG32(SOR_PLL2), 1523062f5b2cSThierry Reding DEBUGFS_REG32(SOR_PLL3), 1524062f5b2cSThierry Reding DEBUGFS_REG32(SOR_CSTM), 1525062f5b2cSThierry Reding DEBUGFS_REG32(SOR_LVDS), 1526062f5b2cSThierry Reding DEBUGFS_REG32(SOR_CRCA), 1527062f5b2cSThierry Reding DEBUGFS_REG32(SOR_CRCB), 1528062f5b2cSThierry Reding DEBUGFS_REG32(SOR_BLANK), 1529062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_CTL), 1530062f5b2cSThierry Reding DEBUGFS_REG32(SOR_LANE_SEQ_CTL), 1531062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_INST(0)), 1532062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_INST(1)), 1533062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_INST(2)), 1534062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_INST(3)), 1535062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_INST(4)), 1536062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_INST(5)), 1537062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_INST(6)), 1538062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_INST(7)), 1539062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_INST(8)), 1540062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_INST(9)), 1541062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_INST(10)), 1542062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_INST(11)), 1543062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_INST(12)), 1544062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_INST(13)), 1545062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_INST(14)), 1546062f5b2cSThierry Reding DEBUGFS_REG32(SOR_SEQ_INST(15)), 1547062f5b2cSThierry Reding DEBUGFS_REG32(SOR_PWM_DIV), 1548062f5b2cSThierry Reding DEBUGFS_REG32(SOR_PWM_CTL), 1549062f5b2cSThierry Reding DEBUGFS_REG32(SOR_VCRC_A0), 1550062f5b2cSThierry Reding DEBUGFS_REG32(SOR_VCRC_A1), 1551062f5b2cSThierry Reding DEBUGFS_REG32(SOR_VCRC_B0), 1552062f5b2cSThierry Reding DEBUGFS_REG32(SOR_VCRC_B1), 1553062f5b2cSThierry Reding DEBUGFS_REG32(SOR_CCRC_A0), 1554062f5b2cSThierry Reding DEBUGFS_REG32(SOR_CCRC_A1), 1555062f5b2cSThierry Reding DEBUGFS_REG32(SOR_CCRC_B0), 1556062f5b2cSThierry Reding DEBUGFS_REG32(SOR_CCRC_B1), 1557062f5b2cSThierry Reding DEBUGFS_REG32(SOR_EDATA_A0), 1558062f5b2cSThierry Reding DEBUGFS_REG32(SOR_EDATA_A1), 1559062f5b2cSThierry Reding DEBUGFS_REG32(SOR_EDATA_B0), 1560062f5b2cSThierry Reding DEBUGFS_REG32(SOR_EDATA_B1), 1561062f5b2cSThierry Reding DEBUGFS_REG32(SOR_COUNT_A0), 1562062f5b2cSThierry Reding DEBUGFS_REG32(SOR_COUNT_A1), 1563062f5b2cSThierry Reding DEBUGFS_REG32(SOR_COUNT_B0), 1564062f5b2cSThierry Reding DEBUGFS_REG32(SOR_COUNT_B1), 1565062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DEBUG_A0), 1566062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DEBUG_A1), 1567062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DEBUG_B0), 1568062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DEBUG_B1), 1569062f5b2cSThierry Reding DEBUGFS_REG32(SOR_TRIG), 1570062f5b2cSThierry Reding DEBUGFS_REG32(SOR_MSCHECK), 1571062f5b2cSThierry Reding DEBUGFS_REG32(SOR_XBAR_CTRL), 1572062f5b2cSThierry Reding DEBUGFS_REG32(SOR_XBAR_POL), 1573062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_LINKCTL0), 1574062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_LINKCTL1), 1575062f5b2cSThierry Reding DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0), 1576062f5b2cSThierry Reding DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1), 1577062f5b2cSThierry Reding DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0), 1578062f5b2cSThierry Reding DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1), 1579062f5b2cSThierry Reding DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0), 1580062f5b2cSThierry Reding DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1), 1581062f5b2cSThierry Reding DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0), 1582062f5b2cSThierry Reding DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1), 1583062f5b2cSThierry Reding DEBUGFS_REG32(SOR_LANE_POSTCURSOR0), 1584062f5b2cSThierry Reding DEBUGFS_REG32(SOR_LANE_POSTCURSOR1), 1585062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_CONFIG0), 1586062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_CONFIG1), 1587062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_MN0), 1588062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_MN1), 1589062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_PADCTL0), 1590062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_PADCTL1), 1591c57997bcSThierry Reding DEBUGFS_REG32(SOR_DP_PADCTL2), 1592062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_DEBUG0), 1593062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_DEBUG1), 1594062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_SPARE0), 1595062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_SPARE1), 1596062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_AUDIO_CTRL), 1597062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS), 1598062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS), 1599062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER), 1600062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0), 1601062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1), 1602062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2), 1603062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3), 1604062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4), 1605062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5), 1606062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6), 1607062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_TPG), 1608062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_TPG_CONFIG), 1609062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_LQ_CSTM0), 1610062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_LQ_CSTM1), 1611062f5b2cSThierry Reding DEBUGFS_REG32(SOR_DP_LQ_CSTM2), 1612062f5b2cSThierry Reding }; 1613062f5b2cSThierry Reding 1614dab16336SThierry Reding static int tegra_sor_show_regs(struct seq_file *s, void *data) 1615dab16336SThierry Reding { 1616dab16336SThierry Reding struct drm_info_node *node = s->private; 1617dab16336SThierry Reding struct tegra_sor *sor = node->info_ent->data; 1618850bab44SThierry Reding struct drm_crtc *crtc = sor->output.encoder.crtc; 1619850bab44SThierry Reding struct drm_device *drm = node->minor->dev; 1620062f5b2cSThierry Reding unsigned int i; 1621850bab44SThierry Reding int err = 0; 1622850bab44SThierry Reding 1623850bab44SThierry Reding drm_modeset_lock_all(drm); 1624850bab44SThierry Reding 1625850bab44SThierry Reding if (!crtc || !crtc->state->active) { 1626850bab44SThierry Reding err = -EBUSY; 1627850bab44SThierry Reding goto unlock; 1628850bab44SThierry Reding } 1629dab16336SThierry Reding 1630062f5b2cSThierry Reding for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) { 1631062f5b2cSThierry Reding unsigned int offset = tegra_sor_regs[i].offset; 1632dab16336SThierry Reding 1633062f5b2cSThierry Reding seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name, 1634062f5b2cSThierry Reding offset, tegra_sor_readl(sor, offset)); 1635062f5b2cSThierry Reding } 1636dab16336SThierry Reding 1637850bab44SThierry Reding unlock: 1638850bab44SThierry Reding drm_modeset_unlock_all(drm); 1639850bab44SThierry Reding return err; 1640dab16336SThierry Reding } 1641dab16336SThierry Reding 1642dab16336SThierry Reding static const struct drm_info_list debugfs_files[] = { 1643530239a8SThierry Reding { "crc", tegra_sor_show_crc, 0, NULL }, 1644dab16336SThierry Reding { "regs", tegra_sor_show_regs, 0, NULL }, 1645dab16336SThierry Reding }; 1646dab16336SThierry Reding 16475b8e043bSThierry Reding static int tegra_sor_late_register(struct drm_connector *connector) 16486fad8f66SThierry Reding { 16495b8e043bSThierry Reding struct tegra_output *output = connector_to_output(connector); 16505b8e043bSThierry Reding unsigned int i, count = ARRAY_SIZE(debugfs_files); 16515b8e043bSThierry Reding struct drm_minor *minor = connector->dev->primary; 16525b8e043bSThierry Reding struct dentry *root = connector->debugfs_entry; 16535b8e043bSThierry Reding struct tegra_sor *sor = to_sor(output); 1654530239a8SThierry Reding int err; 16556fad8f66SThierry Reding 1656dab16336SThierry Reding sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1657dab16336SThierry Reding GFP_KERNEL); 16585b8e043bSThierry Reding if (!sor->debugfs_files) 16595b8e043bSThierry Reding return -ENOMEM; 16606fad8f66SThierry Reding 16615b8e043bSThierry Reding for (i = 0; i < count; i++) 1662dab16336SThierry Reding sor->debugfs_files[i].data = sor; 1663dab16336SThierry Reding 16645b8e043bSThierry Reding err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor); 1665dab16336SThierry Reding if (err < 0) 1666dab16336SThierry Reding goto free; 1667dab16336SThierry Reding 1668530239a8SThierry Reding return 0; 16696fad8f66SThierry Reding 1670dab16336SThierry Reding free: 1671dab16336SThierry Reding kfree(sor->debugfs_files); 1672dab16336SThierry Reding sor->debugfs_files = NULL; 16735b8e043bSThierry Reding 16746fad8f66SThierry Reding return err; 16756fad8f66SThierry Reding } 16766fad8f66SThierry Reding 16775b8e043bSThierry Reding static void tegra_sor_early_unregister(struct drm_connector *connector) 16786fad8f66SThierry Reding { 16795b8e043bSThierry Reding struct tegra_output *output = connector_to_output(connector); 16805b8e043bSThierry Reding unsigned int count = ARRAY_SIZE(debugfs_files); 16815b8e043bSThierry Reding struct tegra_sor *sor = to_sor(output); 1682d92e6009SThierry Reding 16835b8e043bSThierry Reding drm_debugfs_remove_files(sor->debugfs_files, count, 16845b8e043bSThierry Reding connector->dev->primary); 1685dab16336SThierry Reding kfree(sor->debugfs_files); 1686066d30f8SThierry Reding sor->debugfs_files = NULL; 16876fad8f66SThierry Reding } 16886fad8f66SThierry Reding 1689c31efa7aSThierry Reding static void tegra_sor_connector_reset(struct drm_connector *connector) 1690c31efa7aSThierry Reding { 1691c31efa7aSThierry Reding struct tegra_sor_state *state; 1692c31efa7aSThierry Reding 1693c31efa7aSThierry Reding state = kzalloc(sizeof(*state), GFP_KERNEL); 1694c31efa7aSThierry Reding if (!state) 1695c31efa7aSThierry Reding return; 1696c31efa7aSThierry Reding 1697c31efa7aSThierry Reding if (connector->state) { 1698c31efa7aSThierry Reding __drm_atomic_helper_connector_destroy_state(connector->state); 1699c31efa7aSThierry Reding kfree(connector->state); 1700c31efa7aSThierry Reding } 1701c31efa7aSThierry Reding 1702c31efa7aSThierry Reding __drm_atomic_helper_connector_reset(connector, &state->base); 1703c31efa7aSThierry Reding } 1704c31efa7aSThierry Reding 17056fad8f66SThierry Reding static enum drm_connector_status 17066fad8f66SThierry Reding tegra_sor_connector_detect(struct drm_connector *connector, bool force) 17076fad8f66SThierry Reding { 17086fad8f66SThierry Reding struct tegra_output *output = connector_to_output(connector); 17096fad8f66SThierry Reding struct tegra_sor *sor = to_sor(output); 17106fad8f66SThierry Reding 17119542c237SThierry Reding if (sor->aux) 17129542c237SThierry Reding return drm_dp_aux_detect(sor->aux); 17136fad8f66SThierry Reding 1714459cc2c6SThierry Reding return tegra_output_connector_detect(connector, force); 17156fad8f66SThierry Reding } 17166fad8f66SThierry Reding 1717c31efa7aSThierry Reding static struct drm_connector_state * 1718c31efa7aSThierry Reding tegra_sor_connector_duplicate_state(struct drm_connector *connector) 1719c31efa7aSThierry Reding { 1720c31efa7aSThierry Reding struct tegra_sor_state *state = to_sor_state(connector->state); 1721c31efa7aSThierry Reding struct tegra_sor_state *copy; 1722c31efa7aSThierry Reding 1723c31efa7aSThierry Reding copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 1724c31efa7aSThierry Reding if (!copy) 1725c31efa7aSThierry Reding return NULL; 1726c31efa7aSThierry Reding 1727c31efa7aSThierry Reding __drm_atomic_helper_connector_duplicate_state(connector, ©->base); 1728c31efa7aSThierry Reding 1729c31efa7aSThierry Reding return ©->base; 1730c31efa7aSThierry Reding } 1731c31efa7aSThierry Reding 17326fad8f66SThierry Reding static const struct drm_connector_funcs tegra_sor_connector_funcs = { 1733c31efa7aSThierry Reding .reset = tegra_sor_connector_reset, 17346fad8f66SThierry Reding .detect = tegra_sor_connector_detect, 17356fad8f66SThierry Reding .fill_modes = drm_helper_probe_single_connector_modes, 17366fad8f66SThierry Reding .destroy = tegra_output_connector_destroy, 1737c31efa7aSThierry Reding .atomic_duplicate_state = tegra_sor_connector_duplicate_state, 17384aa3df71SThierry Reding .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 17395b8e043bSThierry Reding .late_register = tegra_sor_late_register, 17405b8e043bSThierry Reding .early_unregister = tegra_sor_early_unregister, 17416fad8f66SThierry Reding }; 17426fad8f66SThierry Reding 17436fad8f66SThierry Reding static int tegra_sor_connector_get_modes(struct drm_connector *connector) 17446fad8f66SThierry Reding { 17456fad8f66SThierry Reding struct tegra_output *output = connector_to_output(connector); 17466fad8f66SThierry Reding struct tegra_sor *sor = to_sor(output); 17476fad8f66SThierry Reding int err; 17486fad8f66SThierry Reding 17499542c237SThierry Reding if (sor->aux) 17509542c237SThierry Reding drm_dp_aux_enable(sor->aux); 17516fad8f66SThierry Reding 17526fad8f66SThierry Reding err = tegra_output_connector_get_modes(connector); 17536fad8f66SThierry Reding 17549542c237SThierry Reding if (sor->aux) 17559542c237SThierry Reding drm_dp_aux_disable(sor->aux); 17566fad8f66SThierry Reding 17576fad8f66SThierry Reding return err; 17586fad8f66SThierry Reding } 17596fad8f66SThierry Reding 17606fad8f66SThierry Reding static enum drm_mode_status 17616fad8f66SThierry Reding tegra_sor_connector_mode_valid(struct drm_connector *connector, 17626fad8f66SThierry Reding struct drm_display_mode *mode) 17636fad8f66SThierry Reding { 17646fad8f66SThierry Reding return MODE_OK; 17656fad8f66SThierry Reding } 17666fad8f66SThierry Reding 17676fad8f66SThierry Reding static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = { 17686fad8f66SThierry Reding .get_modes = tegra_sor_connector_get_modes, 17696fad8f66SThierry Reding .mode_valid = tegra_sor_connector_mode_valid, 17706fad8f66SThierry Reding }; 17716fad8f66SThierry Reding 17726fad8f66SThierry Reding static const struct drm_encoder_funcs tegra_sor_encoder_funcs = { 17736fad8f66SThierry Reding .destroy = tegra_output_encoder_destroy, 17746fad8f66SThierry Reding }; 17756fad8f66SThierry Reding 1776850bab44SThierry Reding static void tegra_sor_edp_disable(struct drm_encoder *encoder) 17776fad8f66SThierry Reding { 1778850bab44SThierry Reding struct tegra_output *output = encoder_to_output(encoder); 1779850bab44SThierry Reding struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1780850bab44SThierry Reding struct tegra_sor *sor = to_sor(output); 1781850bab44SThierry Reding u32 value; 1782850bab44SThierry Reding int err; 1783850bab44SThierry Reding 1784850bab44SThierry Reding if (output->panel) 1785850bab44SThierry Reding drm_panel_disable(output->panel); 1786850bab44SThierry Reding 1787850bab44SThierry Reding err = tegra_sor_detach(sor); 1788850bab44SThierry Reding if (err < 0) 1789850bab44SThierry Reding dev_err(sor->dev, "failed to detach SOR: %d\n", err); 1790850bab44SThierry Reding 1791850bab44SThierry Reding tegra_sor_writel(sor, 0, SOR_STATE1); 1792850bab44SThierry Reding tegra_sor_update(sor); 1793850bab44SThierry Reding 1794850bab44SThierry Reding value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1795c57997bcSThierry Reding value &= ~SOR_ENABLE(0); 1796850bab44SThierry Reding tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1797850bab44SThierry Reding 1798850bab44SThierry Reding tegra_dc_commit(dc); 17996fad8f66SThierry Reding 1800850bab44SThierry Reding err = tegra_sor_power_down(sor); 1801850bab44SThierry Reding if (err < 0) 1802850bab44SThierry Reding dev_err(sor->dev, "failed to power down SOR: %d\n", err); 1803850bab44SThierry Reding 18049542c237SThierry Reding if (sor->aux) { 18059542c237SThierry Reding err = drm_dp_aux_disable(sor->aux); 1806850bab44SThierry Reding if (err < 0) 1807850bab44SThierry Reding dev_err(sor->dev, "failed to disable DP: %d\n", err); 18086fad8f66SThierry Reding } 18096fad8f66SThierry Reding 1810c57997bcSThierry Reding err = tegra_io_pad_power_disable(sor->pad); 1811850bab44SThierry Reding if (err < 0) 1812c57997bcSThierry Reding dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); 1813850bab44SThierry Reding 1814850bab44SThierry Reding if (output->panel) 1815850bab44SThierry Reding drm_panel_unprepare(output->panel); 1816850bab44SThierry Reding 1817aaff8bd2SThierry Reding pm_runtime_put(sor->dev); 18186fad8f66SThierry Reding } 18196fad8f66SThierry Reding 1820459cc2c6SThierry Reding #if 0 1821459cc2c6SThierry Reding static int calc_h_ref_to_sync(const struct drm_display_mode *mode, 1822459cc2c6SThierry Reding unsigned int *value) 1823459cc2c6SThierry Reding { 1824459cc2c6SThierry Reding unsigned int hfp, hsw, hbp, a = 0, b; 1825459cc2c6SThierry Reding 1826459cc2c6SThierry Reding hfp = mode->hsync_start - mode->hdisplay; 1827459cc2c6SThierry Reding hsw = mode->hsync_end - mode->hsync_start; 1828459cc2c6SThierry Reding hbp = mode->htotal - mode->hsync_end; 1829459cc2c6SThierry Reding 1830459cc2c6SThierry Reding pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp); 1831459cc2c6SThierry Reding 1832459cc2c6SThierry Reding b = hfp - 1; 1833459cc2c6SThierry Reding 1834459cc2c6SThierry Reding pr_info("a: %u, b: %u\n", a, b); 1835459cc2c6SThierry Reding pr_info("a + hsw + hbp = %u\n", a + hsw + hbp); 1836459cc2c6SThierry Reding 1837459cc2c6SThierry Reding if (a + hsw + hbp <= 11) { 1838459cc2c6SThierry Reding a = 1 + 11 - hsw - hbp; 1839459cc2c6SThierry Reding pr_info("a: %u\n", a); 1840459cc2c6SThierry Reding } 1841459cc2c6SThierry Reding 1842459cc2c6SThierry Reding if (a > b) 1843459cc2c6SThierry Reding return -EINVAL; 1844459cc2c6SThierry Reding 1845459cc2c6SThierry Reding if (hsw < 1) 1846459cc2c6SThierry Reding return -EINVAL; 1847459cc2c6SThierry Reding 1848459cc2c6SThierry Reding if (mode->hdisplay < 16) 1849459cc2c6SThierry Reding return -EINVAL; 1850459cc2c6SThierry Reding 1851459cc2c6SThierry Reding if (value) { 1852459cc2c6SThierry Reding if (b > a && a % 2) 1853459cc2c6SThierry Reding *value = a + 1; 1854459cc2c6SThierry Reding else 1855459cc2c6SThierry Reding *value = a; 1856459cc2c6SThierry Reding } 1857459cc2c6SThierry Reding 1858459cc2c6SThierry Reding return 0; 1859459cc2c6SThierry Reding } 1860459cc2c6SThierry Reding #endif 1861459cc2c6SThierry Reding 1862850bab44SThierry Reding static void tegra_sor_edp_enable(struct drm_encoder *encoder) 18636fad8f66SThierry Reding { 18646fad8f66SThierry Reding struct tegra_output *output = encoder_to_output(encoder); 18656fad8f66SThierry Reding struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 18666b6b6042SThierry Reding struct tegra_sor *sor = to_sor(output); 186734fa183bSThierry Reding struct tegra_sor_config config; 1868c31efa7aSThierry Reding struct tegra_sor_state *state; 1869c1763937SThierry Reding struct drm_display_mode *mode; 1870c1763937SThierry Reding struct drm_display_info *info; 18712bd1dd39SThierry Reding unsigned int i; 187228fe2076SThierry Reding u32 value; 1873c1763937SThierry Reding int err; 187486f5c52dSThierry Reding 1875c31efa7aSThierry Reding state = to_sor_state(output->connector.state); 1876c1763937SThierry Reding mode = &encoder->crtc->state->adjusted_mode; 1877c1763937SThierry Reding info = &output->connector.display_info; 18786b6b6042SThierry Reding 1879aaff8bd2SThierry Reding pm_runtime_get_sync(sor->dev); 18806b6b6042SThierry Reding 188125bb2cecSThierry Reding /* switch to safe parent clock */ 188225bb2cecSThierry Reding err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 18836b6b6042SThierry Reding if (err < 0) 18846b6b6042SThierry Reding dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 18856b6b6042SThierry Reding 1886*38b445bcSThierry Reding err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); 1887*38b445bcSThierry Reding if (err < 0) 1888*38b445bcSThierry Reding dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err); 1889*38b445bcSThierry Reding 1890*38b445bcSThierry Reding usleep_range(20, 100); 1891*38b445bcSThierry Reding 1892*38b445bcSThierry Reding err = drm_dp_aux_enable(sor->aux); 1893*38b445bcSThierry Reding if (err < 0) 1894*38b445bcSThierry Reding dev_err(sor->dev, "failed to enable DPAUX: %d\n", err); 1895*38b445bcSThierry Reding 1896*38b445bcSThierry Reding err = drm_dp_link_probe(sor->aux, &sor->link); 1897*38b445bcSThierry Reding if (err < 0) 1898*38b445bcSThierry Reding dev_err(sor->dev, "failed to probe eDP link: %d\n", err); 1899*38b445bcSThierry Reding 1900*38b445bcSThierry Reding err = drm_dp_link_choose(&sor->link, mode, info); 1901*38b445bcSThierry Reding if (err < 0) 1902*38b445bcSThierry Reding dev_err(sor->dev, "failed to choose link: %d\n", err); 1903*38b445bcSThierry Reding 1904*38b445bcSThierry Reding if (output->panel) 1905*38b445bcSThierry Reding drm_panel_prepare(output->panel); 19066b6b6042SThierry Reding 1907880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1908a9a9e4fdSThierry Reding value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 1909880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1910*38b445bcSThierry Reding 1911*38b445bcSThierry Reding usleep_range(20, 40); 19126b6b6042SThierry Reding 1913880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll3); 1914a9a9e4fdSThierry Reding value |= SOR_PLL3_PLL_VDD_MODE_3V3; 1915880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll3); 19166b6b6042SThierry Reding 1917*38b445bcSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll0); 1918*38b445bcSThierry Reding value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR); 1919880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll0); 19206b6b6042SThierry Reding 1921880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1922a9a9e4fdSThierry Reding value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1923*38b445bcSThierry Reding value |= SOR_PLL2_SEQ_PLLCAPPD; 1924880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll2); 19256b6b6042SThierry Reding 1926*38b445bcSThierry Reding usleep_range(200, 400); 19276b6b6042SThierry Reding 1928880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1929a9a9e4fdSThierry Reding value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 1930a9a9e4fdSThierry Reding value &= ~SOR_PLL2_PORT_POWERDOWN; 1931880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll2); 19326b6b6042SThierry Reding 19336b6b6042SThierry Reding value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1934*38b445bcSThierry Reding value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 1935*38b445bcSThierry Reding value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 19366b6b6042SThierry Reding tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 19376b6b6042SThierry Reding 1938*38b445bcSThierry Reding value = tegra_sor_readl(sor, SOR_DP_SPARE0); 1939*38b445bcSThierry Reding /* XXX not in TRM */ 1940*38b445bcSThierry Reding value |= SOR_DP_SPARE_PANEL_INTERNAL; 1941*38b445bcSThierry Reding value |= SOR_DP_SPARE_SEQ_ENABLE; 1942*38b445bcSThierry Reding tegra_sor_writel(sor, value, SOR_DP_SPARE0); 1943*38b445bcSThierry Reding 1944*38b445bcSThierry Reding /* XXX not in TRM */ 1945*38b445bcSThierry Reding tegra_sor_writel(sor, 0, SOR_LVDS); 19466b6b6042SThierry Reding 1947880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll0); 1948*38b445bcSThierry Reding value &= ~SOR_PLL0_ICHPMP_MASK; 1949*38b445bcSThierry Reding value &= ~SOR_PLL0_VCOCAP_MASK; 1950*38b445bcSThierry Reding value |= SOR_PLL0_ICHPMP(0x1); 1951*38b445bcSThierry Reding value |= SOR_PLL0_VCOCAP(0x3); 1952*38b445bcSThierry Reding value |= SOR_PLL0_RESISTOR_EXT; 1953880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll0); 19546b6b6042SThierry Reding 195530b49435SThierry Reding /* XXX not in TRM */ 195630b49435SThierry Reding for (value = 0, i = 0; i < 5; i++) 19576d6c815dSThierry Reding value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | 195830b49435SThierry Reding SOR_XBAR_CTRL_LINK1_XSEL(i, i); 195930b49435SThierry Reding 196030b49435SThierry Reding tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 196130b49435SThierry Reding tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 196230b49435SThierry Reding 196325bb2cecSThierry Reding /* switch to DP parent clock */ 196425bb2cecSThierry Reding err = tegra_sor_set_parent_clock(sor, sor->clk_dp); 19656b6b6042SThierry Reding if (err < 0) 196625bb2cecSThierry Reding dev_err(sor->dev, "failed to set parent clock: %d\n", err); 19676b6b6042SThierry Reding 1968c1763937SThierry Reding /* use DP-A protocol */ 1969c1763937SThierry Reding value = tegra_sor_readl(sor, SOR_STATE1); 1970c1763937SThierry Reding value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 1971c1763937SThierry Reding value |= SOR_STATE_ASY_PROTOCOL_DP_A; 1972c1763937SThierry Reding tegra_sor_writel(sor, value, SOR_STATE1); 1973899451b7SThierry Reding 1974c1763937SThierry Reding /* enable port */ 1975a9a9e4fdSThierry Reding value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 19766b6b6042SThierry Reding value |= SOR_DP_LINKCTL_ENABLE; 1977a9a9e4fdSThierry Reding tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 19786b6b6042SThierry Reding 1979c1763937SThierry Reding tegra_sor_dp_term_calibrate(sor); 1980c1763937SThierry Reding 1981c1763937SThierry Reding err = drm_dp_link_train(&sor->link); 1982c1763937SThierry Reding if (err < 0) 1983c1763937SThierry Reding dev_err(sor->dev, "link training failed: %d\n", err); 1984c1763937SThierry Reding else 1985c1763937SThierry Reding dev_dbg(sor->dev, "link training succeeded\n"); 1986c1763937SThierry Reding 1987c1763937SThierry Reding err = drm_dp_link_power_up(sor->aux, &sor->link); 1988*38b445bcSThierry Reding if (err < 0) 1989*38b445bcSThierry Reding dev_err(sor->dev, "failed to power up eDP link: %d\n", err); 19906b6b6042SThierry Reding 1991c1763937SThierry Reding /* compute configuration */ 1992c1763937SThierry Reding memset(&config, 0, sizeof(config)); 1993c1763937SThierry Reding config.bits_per_pixel = state->bpc * 3; 19946b6b6042SThierry Reding 1995c1763937SThierry Reding err = tegra_sor_compute_config(sor, mode, &config, &sor->link); 1996*38b445bcSThierry Reding if (err < 0) 1997c1763937SThierry Reding dev_err(sor->dev, "failed to compute configuration: %d\n", err); 19986b6b6042SThierry Reding 1999c1763937SThierry Reding tegra_sor_apply_config(sor, &config); 20006b6b6042SThierry Reding 20016b6b6042SThierry Reding err = tegra_sor_power_up(sor, 250); 2002850bab44SThierry Reding if (err < 0) 20036b6b6042SThierry Reding dev_err(sor->dev, "failed to power up SOR: %d\n", err); 20046b6b6042SThierry Reding 20056b6b6042SThierry Reding /* CSTM (LVDS, link A/B, upper) */ 2006143b1df2SStéphane Marchesin value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | 20076b6b6042SThierry Reding SOR_CSTM_UPPER; 20086b6b6042SThierry Reding tegra_sor_writel(sor, value, SOR_CSTM); 20096b6b6042SThierry Reding 20102bd1dd39SThierry Reding /* use DP-A protocol */ 20112bd1dd39SThierry Reding value = tegra_sor_readl(sor, SOR_STATE1); 20122bd1dd39SThierry Reding value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 20132bd1dd39SThierry Reding value |= SOR_STATE_ASY_PROTOCOL_DP_A; 20142bd1dd39SThierry Reding tegra_sor_writel(sor, value, SOR_STATE1); 20152bd1dd39SThierry Reding 2016c31efa7aSThierry Reding tegra_sor_mode_set(sor, mode, state); 20172bd1dd39SThierry Reding 20186b6b6042SThierry Reding /* PWM setup */ 20196b6b6042SThierry Reding err = tegra_sor_setup_pwm(sor, 250); 2020850bab44SThierry Reding if (err < 0) 20216b6b6042SThierry Reding dev_err(sor->dev, "failed to setup PWM: %d\n", err); 20226b6b6042SThierry Reding 2023666cb873SThierry Reding tegra_sor_update(sor); 2024666cb873SThierry Reding 2025*38b445bcSThierry Reding err = tegra_sor_power_up(sor, 250); 2026*38b445bcSThierry Reding if (err < 0) 2027*38b445bcSThierry Reding dev_err(sor->dev, "failed to power up SOR: %d\n", err); 2028*38b445bcSThierry Reding 2029*38b445bcSThierry Reding /* attach and wake up */ 2030*38b445bcSThierry Reding err = tegra_sor_attach(sor); 2031*38b445bcSThierry Reding if (err < 0) 2032*38b445bcSThierry Reding dev_err(sor->dev, "failed to attach SOR: %d\n", err); 2033*38b445bcSThierry Reding 20346b6b6042SThierry Reding value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2035c57997bcSThierry Reding value |= SOR_ENABLE(0); 20366b6b6042SThierry Reding tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 20376b6b6042SThierry Reding 2038666cb873SThierry Reding tegra_dc_commit(dc); 20396b6b6042SThierry Reding 20406b6b6042SThierry Reding err = tegra_sor_wakeup(sor); 2041850bab44SThierry Reding if (err < 0) 2042*38b445bcSThierry Reding dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); 20436b6b6042SThierry Reding 20446fad8f66SThierry Reding if (output->panel) 20456fad8f66SThierry Reding drm_panel_enable(output->panel); 20466b6b6042SThierry Reding } 20476b6b6042SThierry Reding 204882f1511cSThierry Reding static int 204982f1511cSThierry Reding tegra_sor_encoder_atomic_check(struct drm_encoder *encoder, 205082f1511cSThierry Reding struct drm_crtc_state *crtc_state, 205182f1511cSThierry Reding struct drm_connector_state *conn_state) 205282f1511cSThierry Reding { 205382f1511cSThierry Reding struct tegra_output *output = encoder_to_output(encoder); 2054c31efa7aSThierry Reding struct tegra_sor_state *state = to_sor_state(conn_state); 205582f1511cSThierry Reding struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 205682f1511cSThierry Reding unsigned long pclk = crtc_state->mode.clock * 1000; 205782f1511cSThierry Reding struct tegra_sor *sor = to_sor(output); 2058c31efa7aSThierry Reding struct drm_display_info *info; 205982f1511cSThierry Reding int err; 206082f1511cSThierry Reding 2061c31efa7aSThierry Reding info = &output->connector.display_info; 2062c31efa7aSThierry Reding 206336e90221SThierry Reding /* 206436e90221SThierry Reding * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so 206536e90221SThierry Reding * the pixel clock must be corrected accordingly. 206636e90221SThierry Reding */ 206736e90221SThierry Reding if (pclk >= 340000000) { 206836e90221SThierry Reding state->link_speed = 20; 206936e90221SThierry Reding state->pclk = pclk / 2; 207036e90221SThierry Reding } else { 207136e90221SThierry Reding state->link_speed = 10; 207236e90221SThierry Reding state->pclk = pclk; 207336e90221SThierry Reding } 207436e90221SThierry Reding 207582f1511cSThierry Reding err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, 207682f1511cSThierry Reding pclk, 0); 207782f1511cSThierry Reding if (err < 0) { 207882f1511cSThierry Reding dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 207982f1511cSThierry Reding return err; 208082f1511cSThierry Reding } 208182f1511cSThierry Reding 2082c31efa7aSThierry Reding switch (info->bpc) { 2083c31efa7aSThierry Reding case 8: 2084c31efa7aSThierry Reding case 6: 2085c31efa7aSThierry Reding state->bpc = info->bpc; 2086c31efa7aSThierry Reding break; 2087c31efa7aSThierry Reding 2088c31efa7aSThierry Reding default: 2089c31efa7aSThierry Reding DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc); 2090c31efa7aSThierry Reding state->bpc = 8; 2091c31efa7aSThierry Reding break; 2092c31efa7aSThierry Reding } 2093c31efa7aSThierry Reding 209482f1511cSThierry Reding return 0; 209582f1511cSThierry Reding } 209682f1511cSThierry Reding 2097459cc2c6SThierry Reding static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = { 2098850bab44SThierry Reding .disable = tegra_sor_edp_disable, 2099850bab44SThierry Reding .enable = tegra_sor_edp_enable, 210082f1511cSThierry Reding .atomic_check = tegra_sor_encoder_atomic_check, 21016b6b6042SThierry Reding }; 21026b6b6042SThierry Reding 2103459cc2c6SThierry Reding static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size) 2104459cc2c6SThierry Reding { 2105459cc2c6SThierry Reding u32 value = 0; 2106459cc2c6SThierry Reding size_t i; 2107459cc2c6SThierry Reding 2108459cc2c6SThierry Reding for (i = size; i > 0; i--) 2109459cc2c6SThierry Reding value = (value << 8) | ptr[i - 1]; 2110459cc2c6SThierry Reding 2111459cc2c6SThierry Reding return value; 2112459cc2c6SThierry Reding } 2113459cc2c6SThierry Reding 2114459cc2c6SThierry Reding static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, 2115459cc2c6SThierry Reding const void *data, size_t size) 2116459cc2c6SThierry Reding { 2117459cc2c6SThierry Reding const u8 *ptr = data; 2118459cc2c6SThierry Reding unsigned long offset; 2119459cc2c6SThierry Reding size_t i, j; 2120459cc2c6SThierry Reding u32 value; 2121459cc2c6SThierry Reding 2122459cc2c6SThierry Reding switch (ptr[0]) { 2123459cc2c6SThierry Reding case HDMI_INFOFRAME_TYPE_AVI: 2124459cc2c6SThierry Reding offset = SOR_HDMI_AVI_INFOFRAME_HEADER; 2125459cc2c6SThierry Reding break; 2126459cc2c6SThierry Reding 2127459cc2c6SThierry Reding case HDMI_INFOFRAME_TYPE_AUDIO: 2128459cc2c6SThierry Reding offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER; 2129459cc2c6SThierry Reding break; 2130459cc2c6SThierry Reding 2131459cc2c6SThierry Reding case HDMI_INFOFRAME_TYPE_VENDOR: 2132459cc2c6SThierry Reding offset = SOR_HDMI_VSI_INFOFRAME_HEADER; 2133459cc2c6SThierry Reding break; 2134459cc2c6SThierry Reding 2135459cc2c6SThierry Reding default: 2136459cc2c6SThierry Reding dev_err(sor->dev, "unsupported infoframe type: %02x\n", 2137459cc2c6SThierry Reding ptr[0]); 2138459cc2c6SThierry Reding return; 2139459cc2c6SThierry Reding } 2140459cc2c6SThierry Reding 2141459cc2c6SThierry Reding value = INFOFRAME_HEADER_TYPE(ptr[0]) | 2142459cc2c6SThierry Reding INFOFRAME_HEADER_VERSION(ptr[1]) | 2143459cc2c6SThierry Reding INFOFRAME_HEADER_LEN(ptr[2]); 2144459cc2c6SThierry Reding tegra_sor_writel(sor, value, offset); 2145459cc2c6SThierry Reding offset++; 2146459cc2c6SThierry Reding 2147459cc2c6SThierry Reding /* 2148459cc2c6SThierry Reding * Each subpack contains 7 bytes, divided into: 2149459cc2c6SThierry Reding * - subpack_low: bytes 0 - 3 2150459cc2c6SThierry Reding * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) 2151459cc2c6SThierry Reding */ 2152459cc2c6SThierry Reding for (i = 3, j = 0; i < size; i += 7, j += 8) { 2153459cc2c6SThierry Reding size_t rem = size - i, num = min_t(size_t, rem, 4); 2154459cc2c6SThierry Reding 2155459cc2c6SThierry Reding value = tegra_sor_hdmi_subpack(&ptr[i], num); 2156459cc2c6SThierry Reding tegra_sor_writel(sor, value, offset++); 2157459cc2c6SThierry Reding 2158459cc2c6SThierry Reding num = min_t(size_t, rem - num, 3); 2159459cc2c6SThierry Reding 2160459cc2c6SThierry Reding value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); 2161459cc2c6SThierry Reding tegra_sor_writel(sor, value, offset++); 2162459cc2c6SThierry Reding } 2163459cc2c6SThierry Reding } 2164459cc2c6SThierry Reding 2165459cc2c6SThierry Reding static int 2166459cc2c6SThierry Reding tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, 2167459cc2c6SThierry Reding const struct drm_display_mode *mode) 2168459cc2c6SThierry Reding { 2169459cc2c6SThierry Reding u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 2170459cc2c6SThierry Reding struct hdmi_avi_infoframe frame; 2171459cc2c6SThierry Reding u32 value; 2172459cc2c6SThierry Reding int err; 2173459cc2c6SThierry Reding 2174459cc2c6SThierry Reding /* disable AVI infoframe */ 2175459cc2c6SThierry Reding value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 2176459cc2c6SThierry Reding value &= ~INFOFRAME_CTRL_SINGLE; 2177459cc2c6SThierry Reding value &= ~INFOFRAME_CTRL_OTHER; 2178459cc2c6SThierry Reding value &= ~INFOFRAME_CTRL_ENABLE; 2179459cc2c6SThierry Reding tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 2180459cc2c6SThierry Reding 218113d0add3SVille Syrjälä err = drm_hdmi_avi_infoframe_from_display_mode(&frame, 218213d0add3SVille Syrjälä &sor->output.connector, mode); 2183459cc2c6SThierry Reding if (err < 0) { 2184459cc2c6SThierry Reding dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 2185459cc2c6SThierry Reding return err; 2186459cc2c6SThierry Reding } 2187459cc2c6SThierry Reding 2188459cc2c6SThierry Reding err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 2189459cc2c6SThierry Reding if (err < 0) { 2190459cc2c6SThierry Reding dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); 2191459cc2c6SThierry Reding return err; 2192459cc2c6SThierry Reding } 2193459cc2c6SThierry Reding 2194459cc2c6SThierry Reding tegra_sor_hdmi_write_infopack(sor, buffer, err); 2195459cc2c6SThierry Reding 2196459cc2c6SThierry Reding /* enable AVI infoframe */ 2197459cc2c6SThierry Reding value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 2198459cc2c6SThierry Reding value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; 2199459cc2c6SThierry Reding value |= INFOFRAME_CTRL_ENABLE; 2200459cc2c6SThierry Reding tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 2201459cc2c6SThierry Reding 2202459cc2c6SThierry Reding return 0; 2203459cc2c6SThierry Reding } 2204459cc2c6SThierry Reding 22058e2988a7SThierry Reding static void tegra_sor_write_eld(struct tegra_sor *sor) 22068e2988a7SThierry Reding { 22078e2988a7SThierry Reding size_t length = drm_eld_size(sor->output.connector.eld), i; 22088e2988a7SThierry Reding 22098e2988a7SThierry Reding for (i = 0; i < length; i++) 22108e2988a7SThierry Reding tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i], 22118e2988a7SThierry Reding SOR_AUDIO_HDA_ELD_BUFWR); 22128e2988a7SThierry Reding 22138e2988a7SThierry Reding /* 22148e2988a7SThierry Reding * The HDA codec will always report an ELD buffer size of 96 bytes and 22158e2988a7SThierry Reding * the HDA codec driver will check that each byte read from the buffer 22168e2988a7SThierry Reding * is valid. Therefore every byte must be written, even if no 96 bytes 22178e2988a7SThierry Reding * were parsed from EDID. 22188e2988a7SThierry Reding */ 22198e2988a7SThierry Reding for (i = length; i < 96; i++) 22208e2988a7SThierry Reding tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR); 22218e2988a7SThierry Reding } 22228e2988a7SThierry Reding 22238e2988a7SThierry Reding static void tegra_sor_audio_prepare(struct tegra_sor *sor) 22248e2988a7SThierry Reding { 22258e2988a7SThierry Reding u32 value; 22268e2988a7SThierry Reding 2227f1f20eb9SThierry Reding /* 2228f1f20eb9SThierry Reding * Enable and unmask the HDA codec SCRATCH0 register interrupt. This 2229f1f20eb9SThierry Reding * is used for interoperability between the HDA codec driver and the 2230f1f20eb9SThierry Reding * HDMI/DP driver. 2231f1f20eb9SThierry Reding */ 2232f1f20eb9SThierry Reding value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0; 2233f1f20eb9SThierry Reding tegra_sor_writel(sor, value, SOR_INT_ENABLE); 2234f1f20eb9SThierry Reding tegra_sor_writel(sor, value, SOR_INT_MASK); 2235f1f20eb9SThierry Reding 22368e2988a7SThierry Reding tegra_sor_write_eld(sor); 22378e2988a7SThierry Reding 22388e2988a7SThierry Reding value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD; 22398e2988a7SThierry Reding tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); 22408e2988a7SThierry Reding } 22418e2988a7SThierry Reding 22428e2988a7SThierry Reding static void tegra_sor_audio_unprepare(struct tegra_sor *sor) 22438e2988a7SThierry Reding { 22448e2988a7SThierry Reding tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE); 2245f1f20eb9SThierry Reding tegra_sor_writel(sor, 0, SOR_INT_MASK); 2246f1f20eb9SThierry Reding tegra_sor_writel(sor, 0, SOR_INT_ENABLE); 22478e2988a7SThierry Reding } 22488e2988a7SThierry Reding 22498e2988a7SThierry Reding static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor) 22508e2988a7SThierry Reding { 22518e2988a7SThierry Reding u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)]; 22528e2988a7SThierry Reding struct hdmi_audio_infoframe frame; 22538e2988a7SThierry Reding u32 value; 22548e2988a7SThierry Reding int err; 22558e2988a7SThierry Reding 22568e2988a7SThierry Reding err = hdmi_audio_infoframe_init(&frame); 22578e2988a7SThierry Reding if (err < 0) { 22588e2988a7SThierry Reding dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err); 22598e2988a7SThierry Reding return err; 22608e2988a7SThierry Reding } 22618e2988a7SThierry Reding 2262fad7b806SThierry Reding frame.channels = sor->format.channels; 22638e2988a7SThierry Reding 22648e2988a7SThierry Reding err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 22658e2988a7SThierry Reding if (err < 0) { 22668e2988a7SThierry Reding dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err); 22678e2988a7SThierry Reding return err; 22688e2988a7SThierry Reding } 22698e2988a7SThierry Reding 22708e2988a7SThierry Reding tegra_sor_hdmi_write_infopack(sor, buffer, err); 22718e2988a7SThierry Reding 22728e2988a7SThierry Reding value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 22738e2988a7SThierry Reding value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; 22748e2988a7SThierry Reding value |= INFOFRAME_CTRL_ENABLE; 22758e2988a7SThierry Reding tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 22768e2988a7SThierry Reding 22778e2988a7SThierry Reding return 0; 22788e2988a7SThierry Reding } 22798e2988a7SThierry Reding 22808e2988a7SThierry Reding static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor) 22818e2988a7SThierry Reding { 22828e2988a7SThierry Reding u32 value; 22838e2988a7SThierry Reding 22848e2988a7SThierry Reding value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); 22858e2988a7SThierry Reding 22868e2988a7SThierry Reding /* select HDA audio input */ 22878e2988a7SThierry Reding value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK); 22888e2988a7SThierry Reding value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA); 22898e2988a7SThierry Reding 22908e2988a7SThierry Reding /* inject null samples */ 2291fad7b806SThierry Reding if (sor->format.channels != 2) 22928e2988a7SThierry Reding value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL; 22938e2988a7SThierry Reding else 22948e2988a7SThierry Reding value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL; 22958e2988a7SThierry Reding 22968e2988a7SThierry Reding value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH; 22978e2988a7SThierry Reding 22988e2988a7SThierry Reding tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); 22998e2988a7SThierry Reding 23008e2988a7SThierry Reding /* enable advertising HBR capability */ 23018e2988a7SThierry Reding tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE); 23028e2988a7SThierry Reding 23038e2988a7SThierry Reding tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL); 23048e2988a7SThierry Reding 23058e2988a7SThierry Reding value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH | 23068e2988a7SThierry Reding SOR_HDMI_SPARE_CTS_RESET(1) | 23078e2988a7SThierry Reding SOR_HDMI_SPARE_HW_CTS_ENABLE; 23088e2988a7SThierry Reding tegra_sor_writel(sor, value, SOR_HDMI_SPARE); 23098e2988a7SThierry Reding 23108e2988a7SThierry Reding /* enable HW CTS */ 23118e2988a7SThierry Reding value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0); 23128e2988a7SThierry Reding tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); 23138e2988a7SThierry Reding 23148e2988a7SThierry Reding /* allow packet to be sent */ 23158e2988a7SThierry Reding value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE; 23168e2988a7SThierry Reding tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); 23178e2988a7SThierry Reding 23188e2988a7SThierry Reding /* reset N counter and enable lookup */ 23198e2988a7SThierry Reding value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP; 23208e2988a7SThierry Reding tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); 23218e2988a7SThierry Reding 2322fad7b806SThierry Reding value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); 23238e2988a7SThierry Reding tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); 23248e2988a7SThierry Reding tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320); 23258e2988a7SThierry Reding 23268e2988a7SThierry Reding tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441); 23278e2988a7SThierry Reding tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441); 23288e2988a7SThierry Reding 23298e2988a7SThierry Reding tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882); 23308e2988a7SThierry Reding tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882); 23318e2988a7SThierry Reding 23328e2988a7SThierry Reding tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764); 23338e2988a7SThierry Reding tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764); 23348e2988a7SThierry Reding 2335fad7b806SThierry Reding value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); 23368e2988a7SThierry Reding tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); 23378e2988a7SThierry Reding tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480); 23388e2988a7SThierry Reding 2339fad7b806SThierry Reding value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); 23408e2988a7SThierry Reding tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); 23418e2988a7SThierry Reding tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960); 23428e2988a7SThierry Reding 2343fad7b806SThierry Reding value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); 23448e2988a7SThierry Reding tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); 23458e2988a7SThierry Reding tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920); 23468e2988a7SThierry Reding 23478e2988a7SThierry Reding value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); 23488e2988a7SThierry Reding value &= ~SOR_HDMI_AUDIO_N_RESET; 23498e2988a7SThierry Reding tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); 23508e2988a7SThierry Reding 23518e2988a7SThierry Reding tegra_sor_hdmi_enable_audio_infoframe(sor); 23528e2988a7SThierry Reding } 23538e2988a7SThierry Reding 2354459cc2c6SThierry Reding static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) 2355459cc2c6SThierry Reding { 2356459cc2c6SThierry Reding u32 value; 2357459cc2c6SThierry Reding 2358459cc2c6SThierry Reding value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2359459cc2c6SThierry Reding value &= ~INFOFRAME_CTRL_ENABLE; 2360459cc2c6SThierry Reding tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2361459cc2c6SThierry Reding } 2362459cc2c6SThierry Reding 23638e2988a7SThierry Reding static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor) 23648e2988a7SThierry Reding { 23658e2988a7SThierry Reding tegra_sor_hdmi_disable_audio_infoframe(sor); 23668e2988a7SThierry Reding } 23678e2988a7SThierry Reding 2368459cc2c6SThierry Reding static struct tegra_sor_hdmi_settings * 2369459cc2c6SThierry Reding tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) 2370459cc2c6SThierry Reding { 2371459cc2c6SThierry Reding unsigned int i; 2372459cc2c6SThierry Reding 2373459cc2c6SThierry Reding for (i = 0; i < sor->num_settings; i++) 2374459cc2c6SThierry Reding if (frequency <= sor->settings[i].frequency) 2375459cc2c6SThierry Reding return &sor->settings[i]; 2376459cc2c6SThierry Reding 2377459cc2c6SThierry Reding return NULL; 2378459cc2c6SThierry Reding } 2379459cc2c6SThierry Reding 238036e90221SThierry Reding static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor) 238136e90221SThierry Reding { 238236e90221SThierry Reding u32 value; 238336e90221SThierry Reding 238436e90221SThierry Reding value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); 238536e90221SThierry Reding value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; 238636e90221SThierry Reding value &= ~SOR_HDMI2_CTRL_SCRAMBLE; 238736e90221SThierry Reding tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); 238836e90221SThierry Reding } 238936e90221SThierry Reding 239036e90221SThierry Reding static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor) 239136e90221SThierry Reding { 239236e90221SThierry Reding struct i2c_adapter *ddc = sor->output.ddc; 239336e90221SThierry Reding 239436e90221SThierry Reding drm_scdc_set_high_tmds_clock_ratio(ddc, false); 239536e90221SThierry Reding drm_scdc_set_scrambling(ddc, false); 239636e90221SThierry Reding 239736e90221SThierry Reding tegra_sor_hdmi_disable_scrambling(sor); 239836e90221SThierry Reding } 239936e90221SThierry Reding 240036e90221SThierry Reding static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor) 240136e90221SThierry Reding { 240236e90221SThierry Reding if (sor->scdc_enabled) { 240336e90221SThierry Reding cancel_delayed_work_sync(&sor->scdc); 240436e90221SThierry Reding tegra_sor_hdmi_scdc_disable(sor); 240536e90221SThierry Reding } 240636e90221SThierry Reding } 240736e90221SThierry Reding 240836e90221SThierry Reding static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor) 240936e90221SThierry Reding { 241036e90221SThierry Reding u32 value; 241136e90221SThierry Reding 241236e90221SThierry Reding value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); 241336e90221SThierry Reding value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; 241436e90221SThierry Reding value |= SOR_HDMI2_CTRL_SCRAMBLE; 241536e90221SThierry Reding tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); 241636e90221SThierry Reding } 241736e90221SThierry Reding 241836e90221SThierry Reding static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor) 241936e90221SThierry Reding { 242036e90221SThierry Reding struct i2c_adapter *ddc = sor->output.ddc; 242136e90221SThierry Reding 242236e90221SThierry Reding drm_scdc_set_high_tmds_clock_ratio(ddc, true); 242336e90221SThierry Reding drm_scdc_set_scrambling(ddc, true); 242436e90221SThierry Reding 242536e90221SThierry Reding tegra_sor_hdmi_enable_scrambling(sor); 242636e90221SThierry Reding } 242736e90221SThierry Reding 242836e90221SThierry Reding static void tegra_sor_hdmi_scdc_work(struct work_struct *work) 242936e90221SThierry Reding { 243036e90221SThierry Reding struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work); 243136e90221SThierry Reding struct i2c_adapter *ddc = sor->output.ddc; 243236e90221SThierry Reding 243336e90221SThierry Reding if (!drm_scdc_get_scrambling_status(ddc)) { 243436e90221SThierry Reding DRM_DEBUG_KMS("SCDC not scrambled\n"); 243536e90221SThierry Reding tegra_sor_hdmi_scdc_enable(sor); 243636e90221SThierry Reding } 243736e90221SThierry Reding 243836e90221SThierry Reding schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); 243936e90221SThierry Reding } 244036e90221SThierry Reding 244136e90221SThierry Reding static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor) 244236e90221SThierry Reding { 244336e90221SThierry Reding struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; 244436e90221SThierry Reding struct drm_display_mode *mode; 244536e90221SThierry Reding 244636e90221SThierry Reding mode = &sor->output.encoder.crtc->state->adjusted_mode; 244736e90221SThierry Reding 244836e90221SThierry Reding if (mode->clock >= 340000 && scdc->supported) { 244936e90221SThierry Reding schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); 245036e90221SThierry Reding tegra_sor_hdmi_scdc_enable(sor); 245136e90221SThierry Reding sor->scdc_enabled = true; 245236e90221SThierry Reding } 245336e90221SThierry Reding } 245436e90221SThierry Reding 2455459cc2c6SThierry Reding static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) 2456459cc2c6SThierry Reding { 2457459cc2c6SThierry Reding struct tegra_output *output = encoder_to_output(encoder); 2458459cc2c6SThierry Reding struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2459459cc2c6SThierry Reding struct tegra_sor *sor = to_sor(output); 2460459cc2c6SThierry Reding u32 value; 2461459cc2c6SThierry Reding int err; 2462459cc2c6SThierry Reding 24638e2988a7SThierry Reding tegra_sor_audio_unprepare(sor); 246436e90221SThierry Reding tegra_sor_hdmi_scdc_stop(sor); 246536e90221SThierry Reding 2466459cc2c6SThierry Reding err = tegra_sor_detach(sor); 2467459cc2c6SThierry Reding if (err < 0) 2468459cc2c6SThierry Reding dev_err(sor->dev, "failed to detach SOR: %d\n", err); 2469459cc2c6SThierry Reding 2470459cc2c6SThierry Reding tegra_sor_writel(sor, 0, SOR_STATE1); 2471459cc2c6SThierry Reding tegra_sor_update(sor); 2472459cc2c6SThierry Reding 2473459cc2c6SThierry Reding /* disable display to SOR clock */ 2474459cc2c6SThierry Reding value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2475c57997bcSThierry Reding 2476c57997bcSThierry Reding if (!sor->soc->has_nvdisplay) 2477c57997bcSThierry Reding value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1)); 2478c57997bcSThierry Reding else 2479c57997bcSThierry Reding value &= ~SOR_ENABLE(sor->index); 2480c57997bcSThierry Reding 2481459cc2c6SThierry Reding tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2482459cc2c6SThierry Reding 2483459cc2c6SThierry Reding tegra_dc_commit(dc); 2484459cc2c6SThierry Reding 2485459cc2c6SThierry Reding err = tegra_sor_power_down(sor); 2486459cc2c6SThierry Reding if (err < 0) 2487459cc2c6SThierry Reding dev_err(sor->dev, "failed to power down SOR: %d\n", err); 2488459cc2c6SThierry Reding 2489c57997bcSThierry Reding err = tegra_io_pad_power_disable(sor->pad); 2490459cc2c6SThierry Reding if (err < 0) 2491c57997bcSThierry Reding dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); 2492459cc2c6SThierry Reding 2493aaff8bd2SThierry Reding pm_runtime_put(sor->dev); 2494459cc2c6SThierry Reding } 2495459cc2c6SThierry Reding 2496459cc2c6SThierry Reding static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) 2497459cc2c6SThierry Reding { 2498459cc2c6SThierry Reding struct tegra_output *output = encoder_to_output(encoder); 2499459cc2c6SThierry Reding unsigned int h_ref_to_sync = 1, pulse_start, max_ac; 2500459cc2c6SThierry Reding struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2501459cc2c6SThierry Reding struct tegra_sor_hdmi_settings *settings; 2502459cc2c6SThierry Reding struct tegra_sor *sor = to_sor(output); 2503c31efa7aSThierry Reding struct tegra_sor_state *state; 2504459cc2c6SThierry Reding struct drm_display_mode *mode; 250536e90221SThierry Reding unsigned long rate, pclk; 250630b49435SThierry Reding unsigned int div, i; 2507459cc2c6SThierry Reding u32 value; 2508459cc2c6SThierry Reding int err; 2509459cc2c6SThierry Reding 2510c31efa7aSThierry Reding state = to_sor_state(output->connector.state); 2511459cc2c6SThierry Reding mode = &encoder->crtc->state->adjusted_mode; 251236e90221SThierry Reding pclk = mode->clock * 1000; 2513459cc2c6SThierry Reding 2514aaff8bd2SThierry Reding pm_runtime_get_sync(sor->dev); 2515459cc2c6SThierry Reding 251625bb2cecSThierry Reding /* switch to safe parent clock */ 251725bb2cecSThierry Reding err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 2518e1335e2fSThierry Reding if (err < 0) { 2519459cc2c6SThierry Reding dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 2520e1335e2fSThierry Reding return; 2521e1335e2fSThierry Reding } 2522459cc2c6SThierry Reding 2523459cc2c6SThierry Reding div = clk_get_rate(sor->clk) / 1000000 * 4; 2524459cc2c6SThierry Reding 2525c57997bcSThierry Reding err = tegra_io_pad_power_enable(sor->pad); 2526459cc2c6SThierry Reding if (err < 0) 2527c57997bcSThierry Reding dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); 2528459cc2c6SThierry Reding 2529459cc2c6SThierry Reding usleep_range(20, 100); 2530459cc2c6SThierry Reding 2531880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2532459cc2c6SThierry Reding value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 2533880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2534459cc2c6SThierry Reding 2535459cc2c6SThierry Reding usleep_range(20, 100); 2536459cc2c6SThierry Reding 2537880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2538459cc2c6SThierry Reding value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; 2539880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2540459cc2c6SThierry Reding 2541880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2542459cc2c6SThierry Reding value &= ~SOR_PLL0_VCOPD; 2543459cc2c6SThierry Reding value &= ~SOR_PLL0_PWR; 2544880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2545459cc2c6SThierry Reding 2546880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2547459cc2c6SThierry Reding value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 2548880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2549459cc2c6SThierry Reding 2550459cc2c6SThierry Reding usleep_range(200, 400); 2551459cc2c6SThierry Reding 2552880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2553459cc2c6SThierry Reding value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 2554459cc2c6SThierry Reding value &= ~SOR_PLL2_PORT_POWERDOWN; 2555880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2556459cc2c6SThierry Reding 2557459cc2c6SThierry Reding usleep_range(20, 100); 2558459cc2c6SThierry Reding 2559880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2560459cc2c6SThierry Reding value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 2561459cc2c6SThierry Reding SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; 2562880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2563459cc2c6SThierry Reding 2564459cc2c6SThierry Reding while (true) { 2565459cc2c6SThierry Reding value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2566459cc2c6SThierry Reding if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) 2567459cc2c6SThierry Reding break; 2568459cc2c6SThierry Reding 2569459cc2c6SThierry Reding usleep_range(250, 1000); 2570459cc2c6SThierry Reding } 2571459cc2c6SThierry Reding 2572459cc2c6SThierry Reding value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 2573459cc2c6SThierry Reding SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5); 2574459cc2c6SThierry Reding tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 2575459cc2c6SThierry Reding 2576459cc2c6SThierry Reding while (true) { 2577459cc2c6SThierry Reding value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2578459cc2c6SThierry Reding if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 2579459cc2c6SThierry Reding break; 2580459cc2c6SThierry Reding 2581459cc2c6SThierry Reding usleep_range(250, 1000); 2582459cc2c6SThierry Reding } 2583459cc2c6SThierry Reding 2584459cc2c6SThierry Reding value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 2585459cc2c6SThierry Reding value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 2586459cc2c6SThierry Reding value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 2587459cc2c6SThierry Reding 258836e90221SThierry Reding if (mode->clock < 340000) { 258936e90221SThierry Reding DRM_DEBUG_KMS("setting 2.7 GHz link speed\n"); 2590459cc2c6SThierry Reding value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; 259136e90221SThierry Reding } else { 259236e90221SThierry Reding DRM_DEBUG_KMS("setting 5.4 GHz link speed\n"); 2593459cc2c6SThierry Reding value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; 259436e90221SThierry Reding } 2595459cc2c6SThierry Reding 2596459cc2c6SThierry Reding value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 2597459cc2c6SThierry Reding tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 2598459cc2c6SThierry Reding 2599c57997bcSThierry Reding /* SOR pad PLL stabilization time */ 2600c57997bcSThierry Reding usleep_range(250, 1000); 2601c57997bcSThierry Reding 2602c57997bcSThierry Reding value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 2603c57997bcSThierry Reding value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 2604c57997bcSThierry Reding value |= SOR_DP_LINKCTL_LANE_COUNT(4); 2605c57997bcSThierry Reding tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 2606c57997bcSThierry Reding 2607459cc2c6SThierry Reding value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2608c57997bcSThierry Reding value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2609459cc2c6SThierry Reding value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 2610c57997bcSThierry Reding value &= ~SOR_DP_SPARE_SEQ_ENABLE; 2611c57997bcSThierry Reding value &= ~SOR_DP_SPARE_MACRO_SOR_CLK; 2612459cc2c6SThierry Reding tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2613459cc2c6SThierry Reding 2614459cc2c6SThierry Reding value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | 2615459cc2c6SThierry Reding SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8); 2616459cc2c6SThierry Reding tegra_sor_writel(sor, value, SOR_SEQ_CTL); 2617459cc2c6SThierry Reding 2618459cc2c6SThierry Reding value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | 2619459cc2c6SThierry Reding SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1); 2620459cc2c6SThierry Reding tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); 2621459cc2c6SThierry Reding tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); 2622459cc2c6SThierry Reding 2623c57997bcSThierry Reding if (!sor->soc->has_nvdisplay) { 2624459cc2c6SThierry Reding /* program the reference clock */ 2625459cc2c6SThierry Reding value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); 2626459cc2c6SThierry Reding tegra_sor_writel(sor, value, SOR_REFCLK); 2627c57997bcSThierry Reding } 2628459cc2c6SThierry Reding 262930b49435SThierry Reding /* XXX not in TRM */ 263030b49435SThierry Reding for (value = 0, i = 0; i < 5; i++) 26316d6c815dSThierry Reding value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | 263230b49435SThierry Reding SOR_XBAR_CTRL_LINK1_XSEL(i, i); 2633459cc2c6SThierry Reding 2634459cc2c6SThierry Reding tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 263530b49435SThierry Reding tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 2636459cc2c6SThierry Reding 263725bb2cecSThierry Reding /* switch to parent clock */ 2638e1335e2fSThierry Reding err = clk_set_parent(sor->clk, sor->clk_parent); 2639e1335e2fSThierry Reding if (err < 0) { 2640459cc2c6SThierry Reding dev_err(sor->dev, "failed to set parent clock: %d\n", err); 2641e1335e2fSThierry Reding return; 2642e1335e2fSThierry Reding } 2643e1335e2fSThierry Reding 2644e1335e2fSThierry Reding err = tegra_sor_set_parent_clock(sor, sor->clk_pad); 2645e1335e2fSThierry Reding if (err < 0) { 2646e1335e2fSThierry Reding dev_err(sor->dev, "failed to set pad clock: %d\n", err); 2647e1335e2fSThierry Reding return; 2648e1335e2fSThierry Reding } 2649459cc2c6SThierry Reding 265036e90221SThierry Reding /* adjust clock rate for HDMI 2.0 modes */ 265136e90221SThierry Reding rate = clk_get_rate(sor->clk_parent); 265236e90221SThierry Reding 265336e90221SThierry Reding if (mode->clock >= 340000) 265436e90221SThierry Reding rate /= 2; 265536e90221SThierry Reding 265636e90221SThierry Reding DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk); 265736e90221SThierry Reding 265836e90221SThierry Reding clk_set_rate(sor->clk, rate); 2659c57997bcSThierry Reding 2660c57997bcSThierry Reding if (!sor->soc->has_nvdisplay) { 2661459cc2c6SThierry Reding value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); 2662459cc2c6SThierry Reding 2663459cc2c6SThierry Reding /* XXX is this the proper check? */ 2664459cc2c6SThierry Reding if (mode->clock < 75000) 2665459cc2c6SThierry Reding value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; 2666459cc2c6SThierry Reding 2667459cc2c6SThierry Reding tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); 2668c57997bcSThierry Reding } 2669459cc2c6SThierry Reding 2670459cc2c6SThierry Reding max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; 2671459cc2c6SThierry Reding 2672459cc2c6SThierry Reding value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | 2673459cc2c6SThierry Reding SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY); 2674459cc2c6SThierry Reding tegra_sor_writel(sor, value, SOR_HDMI_CTRL); 2675459cc2c6SThierry Reding 2676c57997bcSThierry Reding if (!dc->soc->has_nvdisplay) { 2677459cc2c6SThierry Reding /* H_PULSE2 setup */ 2678c57997bcSThierry Reding pulse_start = h_ref_to_sync + 2679c57997bcSThierry Reding (mode->hsync_end - mode->hsync_start) + 2680459cc2c6SThierry Reding (mode->htotal - mode->hsync_end) - 10; 2681459cc2c6SThierry Reding 2682459cc2c6SThierry Reding value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | 2683459cc2c6SThierry Reding PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL; 2684459cc2c6SThierry Reding tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); 2685459cc2c6SThierry Reding 2686459cc2c6SThierry Reding value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); 2687459cc2c6SThierry Reding tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); 2688459cc2c6SThierry Reding 2689459cc2c6SThierry Reding value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); 2690459cc2c6SThierry Reding value |= H_PULSE2_ENABLE; 2691459cc2c6SThierry Reding tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); 2692c57997bcSThierry Reding } 2693459cc2c6SThierry Reding 2694459cc2c6SThierry Reding /* infoframe setup */ 2695459cc2c6SThierry Reding err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); 2696459cc2c6SThierry Reding if (err < 0) 2697459cc2c6SThierry Reding dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 2698459cc2c6SThierry Reding 2699459cc2c6SThierry Reding /* XXX HDMI audio support not implemented yet */ 2700459cc2c6SThierry Reding tegra_sor_hdmi_disable_audio_infoframe(sor); 2701459cc2c6SThierry Reding 2702459cc2c6SThierry Reding /* use single TMDS protocol */ 2703459cc2c6SThierry Reding value = tegra_sor_readl(sor, SOR_STATE1); 2704459cc2c6SThierry Reding value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2705459cc2c6SThierry Reding value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; 2706459cc2c6SThierry Reding tegra_sor_writel(sor, value, SOR_STATE1); 2707459cc2c6SThierry Reding 2708459cc2c6SThierry Reding /* power up pad calibration */ 2709880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2710459cc2c6SThierry Reding value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 2711880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2712459cc2c6SThierry Reding 2713459cc2c6SThierry Reding /* production settings */ 2714459cc2c6SThierry Reding settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); 2715db8b42fbSDan Carpenter if (!settings) { 2716db8b42fbSDan Carpenter dev_err(sor->dev, "no settings for pixel clock %d Hz\n", 2717db8b42fbSDan Carpenter mode->clock * 1000); 2718459cc2c6SThierry Reding return; 2719459cc2c6SThierry Reding } 2720459cc2c6SThierry Reding 2721880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2722459cc2c6SThierry Reding value &= ~SOR_PLL0_ICHPMP_MASK; 2723c57997bcSThierry Reding value &= ~SOR_PLL0_FILTER_MASK; 2724459cc2c6SThierry Reding value &= ~SOR_PLL0_VCOCAP_MASK; 2725459cc2c6SThierry Reding value |= SOR_PLL0_ICHPMP(settings->ichpmp); 2726c57997bcSThierry Reding value |= SOR_PLL0_FILTER(settings->filter); 2727459cc2c6SThierry Reding value |= SOR_PLL0_VCOCAP(settings->vcocap); 2728880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2729459cc2c6SThierry Reding 2730c57997bcSThierry Reding /* XXX not in TRM */ 2731880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll1); 2732459cc2c6SThierry Reding value &= ~SOR_PLL1_LOADADJ_MASK; 2733c57997bcSThierry Reding value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 2734459cc2c6SThierry Reding value |= SOR_PLL1_LOADADJ(settings->loadadj); 2735c57997bcSThierry Reding value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); 2736c57997bcSThierry Reding value |= SOR_PLL1_TMDS_TERM; 2737880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll1); 2738459cc2c6SThierry Reding 2739880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2740c57997bcSThierry Reding value &= ~SOR_PLL3_BG_TEMP_COEF_MASK; 2741459cc2c6SThierry Reding value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; 2742c57997bcSThierry Reding value &= ~SOR_PLL3_AVDD10_LEVEL_MASK; 2743c57997bcSThierry Reding value &= ~SOR_PLL3_AVDD14_LEVEL_MASK; 2744c57997bcSThierry Reding value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); 2745c57997bcSThierry Reding value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); 2746c57997bcSThierry Reding value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); 2747c57997bcSThierry Reding value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); 2748880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2749459cc2c6SThierry Reding 2750c57997bcSThierry Reding value = settings->drive_current[3] << 24 | 2751c57997bcSThierry Reding settings->drive_current[2] << 16 | 2752c57997bcSThierry Reding settings->drive_current[1] << 8 | 2753c57997bcSThierry Reding settings->drive_current[0] << 0; 2754459cc2c6SThierry Reding tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); 2755459cc2c6SThierry Reding 2756c57997bcSThierry Reding value = settings->preemphasis[3] << 24 | 2757c57997bcSThierry Reding settings->preemphasis[2] << 16 | 2758c57997bcSThierry Reding settings->preemphasis[1] << 8 | 2759c57997bcSThierry Reding settings->preemphasis[0] << 0; 2760459cc2c6SThierry Reding tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); 2761459cc2c6SThierry Reding 2762880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2763459cc2c6SThierry Reding value &= ~SOR_DP_PADCTL_TX_PU_MASK; 2764459cc2c6SThierry Reding value |= SOR_DP_PADCTL_TX_PU_ENABLE; 2765c57997bcSThierry Reding value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); 2766880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2767459cc2c6SThierry Reding 2768c57997bcSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); 2769c57997bcSThierry Reding value &= ~SOR_DP_PADCTL_SPAREPLL_MASK; 2770c57997bcSThierry Reding value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); 2771c57997bcSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); 2772c57997bcSThierry Reding 2773459cc2c6SThierry Reding /* power down pad calibration */ 2774880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2775459cc2c6SThierry Reding value |= SOR_DP_PADCTL_PAD_CAL_PD; 2776880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2777459cc2c6SThierry Reding 2778c57997bcSThierry Reding if (!dc->soc->has_nvdisplay) { 2779459cc2c6SThierry Reding /* miscellaneous display controller settings */ 2780459cc2c6SThierry Reding value = VSYNC_H_POSITION(1); 2781459cc2c6SThierry Reding tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); 2782c57997bcSThierry Reding } 2783459cc2c6SThierry Reding 2784459cc2c6SThierry Reding value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); 2785459cc2c6SThierry Reding value &= ~DITHER_CONTROL_MASK; 2786459cc2c6SThierry Reding value &= ~BASE_COLOR_SIZE_MASK; 2787459cc2c6SThierry Reding 2788c31efa7aSThierry Reding switch (state->bpc) { 2789459cc2c6SThierry Reding case 6: 2790459cc2c6SThierry Reding value |= BASE_COLOR_SIZE_666; 2791459cc2c6SThierry Reding break; 2792459cc2c6SThierry Reding 2793459cc2c6SThierry Reding case 8: 2794459cc2c6SThierry Reding value |= BASE_COLOR_SIZE_888; 2795459cc2c6SThierry Reding break; 2796459cc2c6SThierry Reding 2797c57997bcSThierry Reding case 10: 2798c57997bcSThierry Reding value |= BASE_COLOR_SIZE_101010; 2799c57997bcSThierry Reding break; 2800c57997bcSThierry Reding 2801c57997bcSThierry Reding case 12: 2802c57997bcSThierry Reding value |= BASE_COLOR_SIZE_121212; 2803c57997bcSThierry Reding break; 2804c57997bcSThierry Reding 2805459cc2c6SThierry Reding default: 2806c31efa7aSThierry Reding WARN(1, "%u bits-per-color not supported\n", state->bpc); 2807c31efa7aSThierry Reding value |= BASE_COLOR_SIZE_888; 2808459cc2c6SThierry Reding break; 2809459cc2c6SThierry Reding } 2810459cc2c6SThierry Reding 2811459cc2c6SThierry Reding tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); 2812459cc2c6SThierry Reding 2813c57997bcSThierry Reding /* XXX set display head owner */ 2814c57997bcSThierry Reding value = tegra_sor_readl(sor, SOR_STATE1); 2815c57997bcSThierry Reding value &= ~SOR_STATE_ASY_OWNER_MASK; 2816c57997bcSThierry Reding value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); 2817c57997bcSThierry Reding tegra_sor_writel(sor, value, SOR_STATE1); 2818c57997bcSThierry Reding 2819459cc2c6SThierry Reding err = tegra_sor_power_up(sor, 250); 2820459cc2c6SThierry Reding if (err < 0) 2821459cc2c6SThierry Reding dev_err(sor->dev, "failed to power up SOR: %d\n", err); 2822459cc2c6SThierry Reding 28232bd1dd39SThierry Reding /* configure dynamic range of output */ 2824880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); 2825459cc2c6SThierry Reding value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; 2826459cc2c6SThierry Reding value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; 2827880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); 2828459cc2c6SThierry Reding 28292bd1dd39SThierry Reding /* configure colorspace */ 2830880cee0bSThierry Reding value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); 2831459cc2c6SThierry Reding value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; 2832459cc2c6SThierry Reding value |= SOR_HEAD_STATE_COLORSPACE_RGB; 2833880cee0bSThierry Reding tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); 2834459cc2c6SThierry Reding 2835c31efa7aSThierry Reding tegra_sor_mode_set(sor, mode, state); 2836459cc2c6SThierry Reding 2837459cc2c6SThierry Reding tegra_sor_update(sor); 2838459cc2c6SThierry Reding 2839c57997bcSThierry Reding /* program preamble timing in SOR (XXX) */ 2840c57997bcSThierry Reding value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2841c57997bcSThierry Reding value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2842c57997bcSThierry Reding tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2843c57997bcSThierry Reding 2844459cc2c6SThierry Reding err = tegra_sor_attach(sor); 2845459cc2c6SThierry Reding if (err < 0) 2846459cc2c6SThierry Reding dev_err(sor->dev, "failed to attach SOR: %d\n", err); 2847459cc2c6SThierry Reding 2848459cc2c6SThierry Reding /* enable display to SOR clock and generate HDMI preamble */ 2849459cc2c6SThierry Reding value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2850c57997bcSThierry Reding 2851c57997bcSThierry Reding if (!sor->soc->has_nvdisplay) 2852c57997bcSThierry Reding value |= SOR_ENABLE(1) | SOR1_TIMING_CYA; 2853c57997bcSThierry Reding else 2854c57997bcSThierry Reding value |= SOR_ENABLE(sor->index); 2855c57997bcSThierry Reding 2856459cc2c6SThierry Reding tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2857459cc2c6SThierry Reding 2858c57997bcSThierry Reding if (dc->soc->has_nvdisplay) { 2859c57997bcSThierry Reding value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); 2860c57997bcSThierry Reding value &= ~PROTOCOL_MASK; 2861c57997bcSThierry Reding value |= PROTOCOL_SINGLE_TMDS_A; 2862c57997bcSThierry Reding tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); 2863c57997bcSThierry Reding } 2864c57997bcSThierry Reding 2865459cc2c6SThierry Reding tegra_dc_commit(dc); 2866459cc2c6SThierry Reding 2867459cc2c6SThierry Reding err = tegra_sor_wakeup(sor); 2868459cc2c6SThierry Reding if (err < 0) 2869459cc2c6SThierry Reding dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); 287036e90221SThierry Reding 287136e90221SThierry Reding tegra_sor_hdmi_scdc_start(sor); 28728e2988a7SThierry Reding tegra_sor_audio_prepare(sor); 2873459cc2c6SThierry Reding } 2874459cc2c6SThierry Reding 2875459cc2c6SThierry Reding static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = { 2876459cc2c6SThierry Reding .disable = tegra_sor_hdmi_disable, 2877459cc2c6SThierry Reding .enable = tegra_sor_hdmi_enable, 2878459cc2c6SThierry Reding .atomic_check = tegra_sor_encoder_atomic_check, 2879459cc2c6SThierry Reding }; 2880459cc2c6SThierry Reding 28816b6b6042SThierry Reding static int tegra_sor_init(struct host1x_client *client) 28826b6b6042SThierry Reding { 28839910f5c4SThierry Reding struct drm_device *drm = dev_get_drvdata(client->parent); 2884459cc2c6SThierry Reding const struct drm_encoder_helper_funcs *helpers = NULL; 28856b6b6042SThierry Reding struct tegra_sor *sor = host1x_client_to_sor(client); 2886459cc2c6SThierry Reding int connector = DRM_MODE_CONNECTOR_Unknown; 2887459cc2c6SThierry Reding int encoder = DRM_MODE_ENCODER_NONE; 28886b6b6042SThierry Reding int err; 28896b6b6042SThierry Reding 28909542c237SThierry Reding if (!sor->aux) { 2891459cc2c6SThierry Reding if (sor->soc->supports_hdmi) { 2892459cc2c6SThierry Reding connector = DRM_MODE_CONNECTOR_HDMIA; 2893459cc2c6SThierry Reding encoder = DRM_MODE_ENCODER_TMDS; 2894459cc2c6SThierry Reding helpers = &tegra_sor_hdmi_helpers; 2895459cc2c6SThierry Reding } else if (sor->soc->supports_lvds) { 2896459cc2c6SThierry Reding connector = DRM_MODE_CONNECTOR_LVDS; 2897459cc2c6SThierry Reding encoder = DRM_MODE_ENCODER_LVDS; 2898459cc2c6SThierry Reding } 2899459cc2c6SThierry Reding } else { 2900459cc2c6SThierry Reding if (sor->soc->supports_edp) { 2901459cc2c6SThierry Reding connector = DRM_MODE_CONNECTOR_eDP; 2902459cc2c6SThierry Reding encoder = DRM_MODE_ENCODER_TMDS; 2903459cc2c6SThierry Reding helpers = &tegra_sor_edp_helpers; 2904459cc2c6SThierry Reding } else if (sor->soc->supports_dp) { 2905459cc2c6SThierry Reding connector = DRM_MODE_CONNECTOR_DisplayPort; 2906459cc2c6SThierry Reding encoder = DRM_MODE_ENCODER_TMDS; 2907459cc2c6SThierry Reding } 2908c1763937SThierry Reding 2909c1763937SThierry Reding sor->link.ops = &tegra_sor_dp_link_ops; 2910c1763937SThierry Reding sor->link.aux = sor->aux; 2911459cc2c6SThierry Reding } 29126b6b6042SThierry Reding 29136b6b6042SThierry Reding sor->output.dev = sor->dev; 29146b6b6042SThierry Reding 29156fad8f66SThierry Reding drm_connector_init(drm, &sor->output.connector, 29166fad8f66SThierry Reding &tegra_sor_connector_funcs, 2917459cc2c6SThierry Reding connector); 29186fad8f66SThierry Reding drm_connector_helper_add(&sor->output.connector, 29196fad8f66SThierry Reding &tegra_sor_connector_helper_funcs); 29206fad8f66SThierry Reding sor->output.connector.dpms = DRM_MODE_DPMS_OFF; 29216fad8f66SThierry Reding 29226fad8f66SThierry Reding drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs, 292313a3d91fSVille Syrjälä encoder, NULL); 2924459cc2c6SThierry Reding drm_encoder_helper_add(&sor->output.encoder, helpers); 29256fad8f66SThierry Reding 2926cde4c44dSDaniel Vetter drm_connector_attach_encoder(&sor->output.connector, 29276fad8f66SThierry Reding &sor->output.encoder); 29286fad8f66SThierry Reding drm_connector_register(&sor->output.connector); 29296fad8f66SThierry Reding 2930ea130b24SThierry Reding err = tegra_output_init(drm, &sor->output); 2931ea130b24SThierry Reding if (err < 0) { 2932ea130b24SThierry Reding dev_err(client->dev, "failed to initialize output: %d\n", err); 2933ea130b24SThierry Reding return err; 2934ea130b24SThierry Reding } 29356fad8f66SThierry Reding 2936c57997bcSThierry Reding tegra_output_find_possible_crtcs(&sor->output, drm); 29376b6b6042SThierry Reding 29389542c237SThierry Reding if (sor->aux) { 29399542c237SThierry Reding err = drm_dp_aux_attach(sor->aux, &sor->output); 29406b6b6042SThierry Reding if (err < 0) { 29416b6b6042SThierry Reding dev_err(sor->dev, "failed to attach DP: %d\n", err); 29426b6b6042SThierry Reding return err; 29436b6b6042SThierry Reding } 29446b6b6042SThierry Reding } 29456b6b6042SThierry Reding 2946535a65dbSTomeu Vizoso /* 2947535a65dbSTomeu Vizoso * XXX: Remove this reset once proper hand-over from firmware to 2948535a65dbSTomeu Vizoso * kernel is possible. 2949535a65dbSTomeu Vizoso */ 2950f8c79120SJon Hunter if (sor->rst) { 295111c632e1SThierry Reding err = reset_control_acquire(sor->rst); 295211c632e1SThierry Reding if (err < 0) { 295311c632e1SThierry Reding dev_err(sor->dev, "failed to acquire SOR reset: %d\n", 295411c632e1SThierry Reding err); 295511c632e1SThierry Reding return err; 295611c632e1SThierry Reding } 295711c632e1SThierry Reding 2958535a65dbSTomeu Vizoso err = reset_control_assert(sor->rst); 2959535a65dbSTomeu Vizoso if (err < 0) { 2960f8c79120SJon Hunter dev_err(sor->dev, "failed to assert SOR reset: %d\n", 2961f8c79120SJon Hunter err); 2962535a65dbSTomeu Vizoso return err; 2963535a65dbSTomeu Vizoso } 2964f8c79120SJon Hunter } 2965535a65dbSTomeu Vizoso 29666fad8f66SThierry Reding err = clk_prepare_enable(sor->clk); 29676fad8f66SThierry Reding if (err < 0) { 29686fad8f66SThierry Reding dev_err(sor->dev, "failed to enable clock: %d\n", err); 29696fad8f66SThierry Reding return err; 29706fad8f66SThierry Reding } 29716fad8f66SThierry Reding 2972535a65dbSTomeu Vizoso usleep_range(1000, 3000); 2973535a65dbSTomeu Vizoso 2974f8c79120SJon Hunter if (sor->rst) { 2975535a65dbSTomeu Vizoso err = reset_control_deassert(sor->rst); 2976535a65dbSTomeu Vizoso if (err < 0) { 2977f8c79120SJon Hunter dev_err(sor->dev, "failed to deassert SOR reset: %d\n", 2978f8c79120SJon Hunter err); 2979535a65dbSTomeu Vizoso return err; 2980535a65dbSTomeu Vizoso } 298111c632e1SThierry Reding 298211c632e1SThierry Reding reset_control_release(sor->rst); 2983f8c79120SJon Hunter } 2984535a65dbSTomeu Vizoso 29856fad8f66SThierry Reding err = clk_prepare_enable(sor->clk_safe); 29866fad8f66SThierry Reding if (err < 0) 29876fad8f66SThierry Reding return err; 29886fad8f66SThierry Reding 29896fad8f66SThierry Reding err = clk_prepare_enable(sor->clk_dp); 29906fad8f66SThierry Reding if (err < 0) 29916fad8f66SThierry Reding return err; 29926fad8f66SThierry Reding 29936b6b6042SThierry Reding return 0; 29946b6b6042SThierry Reding } 29956b6b6042SThierry Reding 29966b6b6042SThierry Reding static int tegra_sor_exit(struct host1x_client *client) 29976b6b6042SThierry Reding { 29986b6b6042SThierry Reding struct tegra_sor *sor = host1x_client_to_sor(client); 29996b6b6042SThierry Reding int err; 30006b6b6042SThierry Reding 3001328ec69eSThierry Reding tegra_output_exit(&sor->output); 3002328ec69eSThierry Reding 30039542c237SThierry Reding if (sor->aux) { 30049542c237SThierry Reding err = drm_dp_aux_detach(sor->aux); 30056b6b6042SThierry Reding if (err < 0) { 30066b6b6042SThierry Reding dev_err(sor->dev, "failed to detach DP: %d\n", err); 30076b6b6042SThierry Reding return err; 30086b6b6042SThierry Reding } 30096b6b6042SThierry Reding } 30106b6b6042SThierry Reding 30116fad8f66SThierry Reding clk_disable_unprepare(sor->clk_safe); 30126fad8f66SThierry Reding clk_disable_unprepare(sor->clk_dp); 30136fad8f66SThierry Reding clk_disable_unprepare(sor->clk); 30146fad8f66SThierry Reding 30156b6b6042SThierry Reding return 0; 30166b6b6042SThierry Reding } 30176b6b6042SThierry Reding 30186b6b6042SThierry Reding static const struct host1x_client_ops sor_client_ops = { 30196b6b6042SThierry Reding .init = tegra_sor_init, 30206b6b6042SThierry Reding .exit = tegra_sor_exit, 30216b6b6042SThierry Reding }; 30226b6b6042SThierry Reding 3023459cc2c6SThierry Reding static const struct tegra_sor_ops tegra_sor_edp_ops = { 3024459cc2c6SThierry Reding .name = "eDP", 3025459cc2c6SThierry Reding }; 3026459cc2c6SThierry Reding 3027459cc2c6SThierry Reding static int tegra_sor_hdmi_probe(struct tegra_sor *sor) 3028459cc2c6SThierry Reding { 3029459cc2c6SThierry Reding int err; 3030459cc2c6SThierry Reding 3031459cc2c6SThierry Reding sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io"); 3032459cc2c6SThierry Reding if (IS_ERR(sor->avdd_io_supply)) { 3033459cc2c6SThierry Reding dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", 3034459cc2c6SThierry Reding PTR_ERR(sor->avdd_io_supply)); 3035459cc2c6SThierry Reding return PTR_ERR(sor->avdd_io_supply); 3036459cc2c6SThierry Reding } 3037459cc2c6SThierry Reding 3038459cc2c6SThierry Reding err = regulator_enable(sor->avdd_io_supply); 3039459cc2c6SThierry Reding if (err < 0) { 3040459cc2c6SThierry Reding dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", 3041459cc2c6SThierry Reding err); 3042459cc2c6SThierry Reding return err; 3043459cc2c6SThierry Reding } 3044459cc2c6SThierry Reding 3045459cc2c6SThierry Reding sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll"); 3046459cc2c6SThierry Reding if (IS_ERR(sor->vdd_pll_supply)) { 3047459cc2c6SThierry Reding dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", 3048459cc2c6SThierry Reding PTR_ERR(sor->vdd_pll_supply)); 3049459cc2c6SThierry Reding return PTR_ERR(sor->vdd_pll_supply); 3050459cc2c6SThierry Reding } 3051459cc2c6SThierry Reding 3052459cc2c6SThierry Reding err = regulator_enable(sor->vdd_pll_supply); 3053459cc2c6SThierry Reding if (err < 0) { 3054459cc2c6SThierry Reding dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", 3055459cc2c6SThierry Reding err); 3056459cc2c6SThierry Reding return err; 3057459cc2c6SThierry Reding } 3058459cc2c6SThierry Reding 3059459cc2c6SThierry Reding sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); 3060459cc2c6SThierry Reding if (IS_ERR(sor->hdmi_supply)) { 3061459cc2c6SThierry Reding dev_err(sor->dev, "cannot get HDMI supply: %ld\n", 3062459cc2c6SThierry Reding PTR_ERR(sor->hdmi_supply)); 3063459cc2c6SThierry Reding return PTR_ERR(sor->hdmi_supply); 3064459cc2c6SThierry Reding } 3065459cc2c6SThierry Reding 3066459cc2c6SThierry Reding err = regulator_enable(sor->hdmi_supply); 3067459cc2c6SThierry Reding if (err < 0) { 3068459cc2c6SThierry Reding dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); 3069459cc2c6SThierry Reding return err; 3070459cc2c6SThierry Reding } 3071459cc2c6SThierry Reding 307236e90221SThierry Reding INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); 307336e90221SThierry Reding 3074459cc2c6SThierry Reding return 0; 3075459cc2c6SThierry Reding } 3076459cc2c6SThierry Reding 3077459cc2c6SThierry Reding static int tegra_sor_hdmi_remove(struct tegra_sor *sor) 3078459cc2c6SThierry Reding { 3079459cc2c6SThierry Reding regulator_disable(sor->hdmi_supply); 3080459cc2c6SThierry Reding regulator_disable(sor->vdd_pll_supply); 3081459cc2c6SThierry Reding regulator_disable(sor->avdd_io_supply); 3082459cc2c6SThierry Reding 3083459cc2c6SThierry Reding return 0; 3084459cc2c6SThierry Reding } 3085459cc2c6SThierry Reding 3086459cc2c6SThierry Reding static const struct tegra_sor_ops tegra_sor_hdmi_ops = { 3087459cc2c6SThierry Reding .name = "HDMI", 3088459cc2c6SThierry Reding .probe = tegra_sor_hdmi_probe, 3089459cc2c6SThierry Reding .remove = tegra_sor_hdmi_remove, 3090459cc2c6SThierry Reding }; 3091459cc2c6SThierry Reding 309230b49435SThierry Reding static const u8 tegra124_sor_xbar_cfg[5] = { 309330b49435SThierry Reding 0, 1, 2, 3, 4 309430b49435SThierry Reding }; 309530b49435SThierry Reding 3096880cee0bSThierry Reding static const struct tegra_sor_regs tegra124_sor_regs = { 3097880cee0bSThierry Reding .head_state0 = 0x05, 3098880cee0bSThierry Reding .head_state1 = 0x07, 3099880cee0bSThierry Reding .head_state2 = 0x09, 3100880cee0bSThierry Reding .head_state3 = 0x0b, 3101880cee0bSThierry Reding .head_state4 = 0x0d, 3102880cee0bSThierry Reding .head_state5 = 0x0f, 3103880cee0bSThierry Reding .pll0 = 0x17, 3104880cee0bSThierry Reding .pll1 = 0x18, 3105880cee0bSThierry Reding .pll2 = 0x19, 3106880cee0bSThierry Reding .pll3 = 0x1a, 3107880cee0bSThierry Reding .dp_padctl0 = 0x5c, 3108880cee0bSThierry Reding .dp_padctl2 = 0x73, 3109880cee0bSThierry Reding }; 3110880cee0bSThierry Reding 3111c1763937SThierry Reding /* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */ 3112c1763937SThierry Reding static const u8 tegra124_sor_lane_map[4] = { 3113c1763937SThierry Reding 2, 1, 0, 3, 3114c1763937SThierry Reding }; 3115c1763937SThierry Reding 3116c1763937SThierry Reding static const u8 tegra124_sor_voltage_swing[4][4][4] = { 3117c1763937SThierry Reding { 3118c1763937SThierry Reding { 0x13, 0x19, 0x1e, 0x28 }, 3119c1763937SThierry Reding { 0x1e, 0x25, 0x2d, }, 3120c1763937SThierry Reding { 0x28, 0x32, }, 3121c1763937SThierry Reding { 0x3c, }, 3122c1763937SThierry Reding }, { 3123c1763937SThierry Reding { 0x12, 0x17, 0x1b, 0x25 }, 3124c1763937SThierry Reding { 0x1c, 0x23, 0x2a, }, 3125c1763937SThierry Reding { 0x25, 0x2f, }, 3126c1763937SThierry Reding { 0x39, } 3127c1763937SThierry Reding }, { 3128c1763937SThierry Reding { 0x12, 0x16, 0x1a, 0x22 }, 3129c1763937SThierry Reding { 0x1b, 0x20, 0x27, }, 3130c1763937SThierry Reding { 0x24, 0x2d, }, 3131c1763937SThierry Reding { 0x36, }, 3132c1763937SThierry Reding }, { 3133c1763937SThierry Reding { 0x11, 0x14, 0x17, 0x1f }, 3134c1763937SThierry Reding { 0x19, 0x1e, 0x24, }, 3135c1763937SThierry Reding { 0x22, 0x2a, }, 3136c1763937SThierry Reding { 0x32, }, 3137c1763937SThierry Reding }, 3138c1763937SThierry Reding }; 3139c1763937SThierry Reding 3140c1763937SThierry Reding static const u8 tegra124_sor_pre_emphasis[4][4][4] = { 3141c1763937SThierry Reding { 3142c1763937SThierry Reding { 0x00, 0x09, 0x13, 0x25 }, 3143c1763937SThierry Reding { 0x00, 0x0f, 0x1e, }, 3144c1763937SThierry Reding { 0x00, 0x14, }, 3145c1763937SThierry Reding { 0x00, }, 3146c1763937SThierry Reding }, { 3147c1763937SThierry Reding { 0x00, 0x0a, 0x14, 0x28 }, 3148c1763937SThierry Reding { 0x00, 0x0f, 0x1e, }, 3149c1763937SThierry Reding { 0x00, 0x14, }, 3150c1763937SThierry Reding { 0x00 }, 3151c1763937SThierry Reding }, { 3152c1763937SThierry Reding { 0x00, 0x0a, 0x14, 0x28 }, 3153c1763937SThierry Reding { 0x00, 0x0f, 0x1e, }, 3154c1763937SThierry Reding { 0x00, 0x14, }, 3155c1763937SThierry Reding { 0x00, }, 3156c1763937SThierry Reding }, { 3157c1763937SThierry Reding { 0x00, 0x0a, 0x14, 0x28 }, 3158c1763937SThierry Reding { 0x00, 0x0f, 0x1e, }, 3159c1763937SThierry Reding { 0x00, 0x14, }, 3160c1763937SThierry Reding { 0x00, }, 3161c1763937SThierry Reding }, 3162c1763937SThierry Reding }; 3163c1763937SThierry Reding 3164c1763937SThierry Reding static const u8 tegra124_sor_post_cursor[4][4][4] = { 3165c1763937SThierry Reding { 3166c1763937SThierry Reding { 0x00, 0x00, 0x00, 0x00 }, 3167c1763937SThierry Reding { 0x00, 0x00, 0x00, }, 3168c1763937SThierry Reding { 0x00, 0x00, }, 3169c1763937SThierry Reding { 0x00, }, 3170c1763937SThierry Reding }, { 3171c1763937SThierry Reding { 0x02, 0x02, 0x04, 0x05 }, 3172c1763937SThierry Reding { 0x02, 0x04, 0x05, }, 3173c1763937SThierry Reding { 0x04, 0x05, }, 3174c1763937SThierry Reding { 0x05, }, 3175c1763937SThierry Reding }, { 3176c1763937SThierry Reding { 0x04, 0x05, 0x08, 0x0b }, 3177c1763937SThierry Reding { 0x05, 0x09, 0x0b, }, 3178c1763937SThierry Reding { 0x08, 0x0a, }, 3179c1763937SThierry Reding { 0x0b, }, 3180c1763937SThierry Reding }, { 3181c1763937SThierry Reding { 0x05, 0x09, 0x0b, 0x12 }, 3182c1763937SThierry Reding { 0x09, 0x0d, 0x12, }, 3183c1763937SThierry Reding { 0x0b, 0x0f, }, 3184c1763937SThierry Reding { 0x12, }, 3185c1763937SThierry Reding }, 3186c1763937SThierry Reding }; 3187c1763937SThierry Reding 3188c1763937SThierry Reding static const u8 tegra124_sor_tx_pu[4][4][4] = { 3189c1763937SThierry Reding { 3190c1763937SThierry Reding { 0x20, 0x30, 0x40, 0x60 }, 3191c1763937SThierry Reding { 0x30, 0x40, 0x60, }, 3192c1763937SThierry Reding { 0x40, 0x60, }, 3193c1763937SThierry Reding { 0x60, }, 3194c1763937SThierry Reding }, { 3195c1763937SThierry Reding { 0x20, 0x20, 0x30, 0x50 }, 3196c1763937SThierry Reding { 0x30, 0x40, 0x50, }, 3197c1763937SThierry Reding { 0x40, 0x50, }, 3198c1763937SThierry Reding { 0x60, }, 3199c1763937SThierry Reding }, { 3200c1763937SThierry Reding { 0x20, 0x20, 0x30, 0x40, }, 3201c1763937SThierry Reding { 0x30, 0x30, 0x40, }, 3202c1763937SThierry Reding { 0x40, 0x50, }, 3203c1763937SThierry Reding { 0x60, }, 3204c1763937SThierry Reding }, { 3205c1763937SThierry Reding { 0x20, 0x20, 0x20, 0x40, }, 3206c1763937SThierry Reding { 0x30, 0x30, 0x40, }, 3207c1763937SThierry Reding { 0x40, 0x40, }, 3208c1763937SThierry Reding { 0x60, }, 3209c1763937SThierry Reding }, 3210c1763937SThierry Reding }; 3211c1763937SThierry Reding 3212459cc2c6SThierry Reding static const struct tegra_sor_soc tegra124_sor = { 3213459cc2c6SThierry Reding .supports_edp = true, 3214459cc2c6SThierry Reding .supports_lvds = true, 3215459cc2c6SThierry Reding .supports_hdmi = false, 3216459cc2c6SThierry Reding .supports_dp = false, 3217880cee0bSThierry Reding .regs = &tegra124_sor_regs, 3218c57997bcSThierry Reding .has_nvdisplay = false, 321930b49435SThierry Reding .xbar_cfg = tegra124_sor_xbar_cfg, 3220c1763937SThierry Reding .lane_map = tegra124_sor_lane_map, 3221c1763937SThierry Reding .voltage_swing = tegra124_sor_voltage_swing, 3222c1763937SThierry Reding .pre_emphasis = tegra124_sor_pre_emphasis, 3223c1763937SThierry Reding .post_cursor = tegra124_sor_post_cursor, 3224c1763937SThierry Reding .tx_pu = tegra124_sor_tx_pu, 3225c1763937SThierry Reding }; 3226c1763937SThierry Reding 3227c1763937SThierry Reding static const u8 tegra132_sor_pre_emphasis[4][4][4] = { 3228c1763937SThierry Reding { 3229c1763937SThierry Reding { 0x00, 0x08, 0x12, 0x24 }, 3230c1763937SThierry Reding { 0x01, 0x0e, 0x1d, }, 3231c1763937SThierry Reding { 0x01, 0x13, }, 3232c1763937SThierry Reding { 0x00, }, 3233c1763937SThierry Reding }, { 3234c1763937SThierry Reding { 0x00, 0x08, 0x12, 0x24 }, 3235c1763937SThierry Reding { 0x00, 0x0e, 0x1d, }, 3236c1763937SThierry Reding { 0x00, 0x13, }, 3237c1763937SThierry Reding { 0x00 }, 3238c1763937SThierry Reding }, { 3239c1763937SThierry Reding { 0x00, 0x08, 0x12, 0x24 }, 3240c1763937SThierry Reding { 0x00, 0x0e, 0x1d, }, 3241c1763937SThierry Reding { 0x00, 0x13, }, 3242c1763937SThierry Reding { 0x00, }, 3243c1763937SThierry Reding }, { 3244c1763937SThierry Reding { 0x00, 0x08, 0x12, 0x24 }, 3245c1763937SThierry Reding { 0x00, 0x0e, 0x1d, }, 3246c1763937SThierry Reding { 0x00, 0x13, }, 3247c1763937SThierry Reding { 0x00, }, 3248c1763937SThierry Reding }, 3249c1763937SThierry Reding }; 3250c1763937SThierry Reding 3251c1763937SThierry Reding static const struct tegra_sor_soc tegra132_sor = { 3252c1763937SThierry Reding .supports_edp = true, 3253c1763937SThierry Reding .supports_lvds = true, 3254c1763937SThierry Reding .supports_hdmi = false, 3255c1763937SThierry Reding .supports_dp = false, 3256c1763937SThierry Reding .regs = &tegra124_sor_regs, 3257c1763937SThierry Reding .has_nvdisplay = false, 3258c1763937SThierry Reding .xbar_cfg = tegra124_sor_xbar_cfg, 3259c1763937SThierry Reding .lane_map = tegra124_sor_lane_map, 3260c1763937SThierry Reding .voltage_swing = tegra124_sor_voltage_swing, 3261c1763937SThierry Reding .pre_emphasis = tegra132_sor_pre_emphasis, 3262c1763937SThierry Reding .post_cursor = tegra124_sor_post_cursor, 3263c1763937SThierry Reding .tx_pu = tegra124_sor_tx_pu, 3264459cc2c6SThierry Reding }; 3265459cc2c6SThierry Reding 3266880cee0bSThierry Reding static const struct tegra_sor_regs tegra210_sor_regs = { 3267880cee0bSThierry Reding .head_state0 = 0x05, 3268880cee0bSThierry Reding .head_state1 = 0x07, 3269880cee0bSThierry Reding .head_state2 = 0x09, 3270880cee0bSThierry Reding .head_state3 = 0x0b, 3271880cee0bSThierry Reding .head_state4 = 0x0d, 3272880cee0bSThierry Reding .head_state5 = 0x0f, 3273880cee0bSThierry Reding .pll0 = 0x17, 3274880cee0bSThierry Reding .pll1 = 0x18, 3275880cee0bSThierry Reding .pll2 = 0x19, 3276880cee0bSThierry Reding .pll3 = 0x1a, 3277880cee0bSThierry Reding .dp_padctl0 = 0x5c, 3278880cee0bSThierry Reding .dp_padctl2 = 0x73, 3279880cee0bSThierry Reding }; 3280880cee0bSThierry Reding 3281c1763937SThierry Reding static const u8 tegra210_sor_xbar_cfg[5] = { 3282c1763937SThierry Reding 2, 1, 0, 3, 4 3283c1763937SThierry Reding }; 3284c1763937SThierry Reding 3285459cc2c6SThierry Reding static const struct tegra_sor_soc tegra210_sor = { 3286459cc2c6SThierry Reding .supports_edp = true, 3287459cc2c6SThierry Reding .supports_lvds = false, 3288459cc2c6SThierry Reding .supports_hdmi = false, 3289459cc2c6SThierry Reding .supports_dp = false, 3290c1763937SThierry Reding 3291880cee0bSThierry Reding .regs = &tegra210_sor_regs, 3292c57997bcSThierry Reding .has_nvdisplay = false, 329330b49435SThierry Reding 3294c1763937SThierry Reding .xbar_cfg = tegra210_sor_xbar_cfg, 3295459cc2c6SThierry Reding }; 3296459cc2c6SThierry Reding 3297459cc2c6SThierry Reding static const struct tegra_sor_soc tegra210_sor1 = { 3298459cc2c6SThierry Reding .supports_edp = false, 3299459cc2c6SThierry Reding .supports_lvds = false, 3300459cc2c6SThierry Reding .supports_hdmi = true, 3301459cc2c6SThierry Reding .supports_dp = true, 3302459cc2c6SThierry Reding 3303880cee0bSThierry Reding .regs = &tegra210_sor_regs, 3304c57997bcSThierry Reding .has_nvdisplay = false, 3305880cee0bSThierry Reding 3306459cc2c6SThierry Reding .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults), 3307459cc2c6SThierry Reding .settings = tegra210_sor_hdmi_defaults, 330830b49435SThierry Reding .xbar_cfg = tegra210_sor_xbar_cfg, 3309459cc2c6SThierry Reding }; 3310459cc2c6SThierry Reding 3311c57997bcSThierry Reding static const struct tegra_sor_regs tegra186_sor_regs = { 3312c57997bcSThierry Reding .head_state0 = 0x151, 3313c57997bcSThierry Reding .head_state1 = 0x154, 3314c57997bcSThierry Reding .head_state2 = 0x157, 3315c57997bcSThierry Reding .head_state3 = 0x15a, 3316c57997bcSThierry Reding .head_state4 = 0x15d, 3317c57997bcSThierry Reding .head_state5 = 0x160, 3318c57997bcSThierry Reding .pll0 = 0x163, 3319c57997bcSThierry Reding .pll1 = 0x164, 3320c57997bcSThierry Reding .pll2 = 0x165, 3321c57997bcSThierry Reding .pll3 = 0x166, 3322c57997bcSThierry Reding .dp_padctl0 = 0x168, 3323c57997bcSThierry Reding .dp_padctl2 = 0x16a, 3324c57997bcSThierry Reding }; 3325c57997bcSThierry Reding 3326c57997bcSThierry Reding static const struct tegra_sor_soc tegra186_sor = { 3327c57997bcSThierry Reding .supports_edp = false, 3328c57997bcSThierry Reding .supports_lvds = false, 3329c57997bcSThierry Reding .supports_hdmi = false, 3330c57997bcSThierry Reding .supports_dp = true, 3331c57997bcSThierry Reding 3332c57997bcSThierry Reding .regs = &tegra186_sor_regs, 3333c57997bcSThierry Reding .has_nvdisplay = true, 3334c57997bcSThierry Reding 3335c57997bcSThierry Reding .xbar_cfg = tegra124_sor_xbar_cfg, 3336c57997bcSThierry Reding }; 3337c57997bcSThierry Reding 3338c57997bcSThierry Reding static const struct tegra_sor_soc tegra186_sor1 = { 3339c57997bcSThierry Reding .supports_edp = false, 3340c57997bcSThierry Reding .supports_lvds = false, 3341c57997bcSThierry Reding .supports_hdmi = true, 3342c57997bcSThierry Reding .supports_dp = true, 3343c57997bcSThierry Reding 3344c57997bcSThierry Reding .regs = &tegra186_sor_regs, 3345c57997bcSThierry Reding .has_nvdisplay = true, 3346c57997bcSThierry Reding 3347c57997bcSThierry Reding .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults), 3348c57997bcSThierry Reding .settings = tegra186_sor_hdmi_defaults, 3349c57997bcSThierry Reding .xbar_cfg = tegra124_sor_xbar_cfg, 3350c57997bcSThierry Reding }; 3351c57997bcSThierry Reding 33529b6c14b8SThierry Reding static const struct tegra_sor_regs tegra194_sor_regs = { 33539b6c14b8SThierry Reding .head_state0 = 0x151, 33549b6c14b8SThierry Reding .head_state1 = 0x155, 33559b6c14b8SThierry Reding .head_state2 = 0x159, 33569b6c14b8SThierry Reding .head_state3 = 0x15d, 33579b6c14b8SThierry Reding .head_state4 = 0x161, 33589b6c14b8SThierry Reding .head_state5 = 0x165, 33599b6c14b8SThierry Reding .pll0 = 0x169, 33609b6c14b8SThierry Reding .pll1 = 0x16a, 33619b6c14b8SThierry Reding .pll2 = 0x16b, 33629b6c14b8SThierry Reding .pll3 = 0x16c, 33639b6c14b8SThierry Reding .dp_padctl0 = 0x16e, 33649b6c14b8SThierry Reding .dp_padctl2 = 0x16f, 33659b6c14b8SThierry Reding }; 33669b6c14b8SThierry Reding 33679b6c14b8SThierry Reding static const struct tegra_sor_soc tegra194_sor = { 33689b6c14b8SThierry Reding .supports_edp = true, 33699b6c14b8SThierry Reding .supports_lvds = false, 33709b6c14b8SThierry Reding .supports_hdmi = true, 33719b6c14b8SThierry Reding .supports_dp = true, 33729b6c14b8SThierry Reding 33739b6c14b8SThierry Reding .regs = &tegra194_sor_regs, 33749b6c14b8SThierry Reding .has_nvdisplay = true, 33759b6c14b8SThierry Reding 33769b6c14b8SThierry Reding .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults), 33779b6c14b8SThierry Reding .settings = tegra194_sor_hdmi_defaults, 33789b6c14b8SThierry Reding 33799b6c14b8SThierry Reding .xbar_cfg = tegra210_sor_xbar_cfg, 33809b6c14b8SThierry Reding }; 33819b6c14b8SThierry Reding 3382459cc2c6SThierry Reding static const struct of_device_id tegra_sor_of_match[] = { 33839b6c14b8SThierry Reding { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor }, 3384c57997bcSThierry Reding { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 }, 3385c57997bcSThierry Reding { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor }, 3386459cc2c6SThierry Reding { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, 3387459cc2c6SThierry Reding { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor }, 3388c1763937SThierry Reding { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor }, 3389459cc2c6SThierry Reding { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor }, 3390459cc2c6SThierry Reding { }, 3391459cc2c6SThierry Reding }; 3392459cc2c6SThierry Reding MODULE_DEVICE_TABLE(of, tegra_sor_of_match); 3393459cc2c6SThierry Reding 3394c57997bcSThierry Reding static int tegra_sor_parse_dt(struct tegra_sor *sor) 3395c57997bcSThierry Reding { 3396c57997bcSThierry Reding struct device_node *np = sor->dev->of_node; 33976d6c815dSThierry Reding u32 xbar_cfg[5]; 33986d6c815dSThierry Reding unsigned int i; 3399c57997bcSThierry Reding u32 value; 3400c57997bcSThierry Reding int err; 3401c57997bcSThierry Reding 3402c57997bcSThierry Reding if (sor->soc->has_nvdisplay) { 3403c57997bcSThierry Reding err = of_property_read_u32(np, "nvidia,interface", &value); 3404c57997bcSThierry Reding if (err < 0) 3405c57997bcSThierry Reding return err; 3406c57997bcSThierry Reding 3407c57997bcSThierry Reding sor->index = value; 3408c57997bcSThierry Reding 3409c57997bcSThierry Reding /* 3410c57997bcSThierry Reding * override the default that we already set for Tegra210 and 3411c57997bcSThierry Reding * earlier 3412c57997bcSThierry Reding */ 3413c57997bcSThierry Reding sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; 3414c57997bcSThierry Reding } 3415c57997bcSThierry Reding 34166d6c815dSThierry Reding err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5); 34176d6c815dSThierry Reding if (err < 0) { 34186d6c815dSThierry Reding /* fall back to default per-SoC XBAR configuration */ 34196d6c815dSThierry Reding for (i = 0; i < 5; i++) 34206d6c815dSThierry Reding sor->xbar_cfg[i] = sor->soc->xbar_cfg[i]; 34216d6c815dSThierry Reding } else { 34226d6c815dSThierry Reding /* copy cells to SOR XBAR configuration */ 34236d6c815dSThierry Reding for (i = 0; i < 5; i++) 34246d6c815dSThierry Reding sor->xbar_cfg[i] = xbar_cfg[i]; 3425c57997bcSThierry Reding } 3426c57997bcSThierry Reding 34276b6b6042SThierry Reding return 0; 34288e2988a7SThierry Reding } 34298e2988a7SThierry Reding 34308e2988a7SThierry Reding static irqreturn_t tegra_sor_irq(int irq, void *data) 34318e2988a7SThierry Reding { 34328e2988a7SThierry Reding struct tegra_sor *sor = data; 34338e2988a7SThierry Reding u32 value; 34348e2988a7SThierry Reding 34358e2988a7SThierry Reding value = tegra_sor_readl(sor, SOR_INT_STATUS); 34368e2988a7SThierry Reding tegra_sor_writel(sor, value, SOR_INT_STATUS); 34378e2988a7SThierry Reding 34388e2988a7SThierry Reding if (value & SOR_INT_CODEC_SCRATCH0) { 34398e2988a7SThierry Reding value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); 34408e2988a7SThierry Reding 34418e2988a7SThierry Reding if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) { 3442cd54fb96SThierry Reding unsigned int format; 34438e2988a7SThierry Reding 34448e2988a7SThierry Reding format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; 34458e2988a7SThierry Reding 3446fad7b806SThierry Reding tegra_hda_parse_format(format, &sor->format); 34478e2988a7SThierry Reding 34488e2988a7SThierry Reding tegra_sor_hdmi_audio_enable(sor); 34498e2988a7SThierry Reding } else { 34508e2988a7SThierry Reding tegra_sor_hdmi_audio_disable(sor); 34518e2988a7SThierry Reding } 34528e2988a7SThierry Reding } 34538e2988a7SThierry Reding 34548e2988a7SThierry Reding return IRQ_HANDLED; 34558e2988a7SThierry Reding } 34568e2988a7SThierry Reding 34576b6b6042SThierry Reding static int tegra_sor_probe(struct platform_device *pdev) 34586b6b6042SThierry Reding { 34596b6b6042SThierry Reding struct device_node *np; 34606b6b6042SThierry Reding struct tegra_sor *sor; 34616b6b6042SThierry Reding struct resource *regs; 34626b6b6042SThierry Reding int err; 34636b6b6042SThierry Reding 34646b6b6042SThierry Reding sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); 34656b6b6042SThierry Reding if (!sor) 34666b6b6042SThierry Reding return -ENOMEM; 34676b6b6042SThierry Reding 34685faea3d0SThierry Reding sor->soc = of_device_get_match_data(&pdev->dev); 34696b6b6042SThierry Reding sor->output.dev = sor->dev = &pdev->dev; 3470459cc2c6SThierry Reding 3471459cc2c6SThierry Reding sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, 3472459cc2c6SThierry Reding sor->soc->num_settings * 3473459cc2c6SThierry Reding sizeof(*sor->settings), 3474459cc2c6SThierry Reding GFP_KERNEL); 3475459cc2c6SThierry Reding if (!sor->settings) 3476459cc2c6SThierry Reding return -ENOMEM; 3477459cc2c6SThierry Reding 3478459cc2c6SThierry Reding sor->num_settings = sor->soc->num_settings; 34796b6b6042SThierry Reding 34806b6b6042SThierry Reding np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); 34816b6b6042SThierry Reding if (np) { 34829542c237SThierry Reding sor->aux = drm_dp_aux_find_by_of_node(np); 34836b6b6042SThierry Reding of_node_put(np); 34846b6b6042SThierry Reding 34859542c237SThierry Reding if (!sor->aux) 34866b6b6042SThierry Reding return -EPROBE_DEFER; 34876f684de5SThierry Reding 34886f684de5SThierry Reding sor->output.ddc = &sor->aux->ddc; 34896b6b6042SThierry Reding } 34906b6b6042SThierry Reding 34919542c237SThierry Reding if (!sor->aux) { 3492459cc2c6SThierry Reding if (sor->soc->supports_hdmi) { 3493459cc2c6SThierry Reding sor->ops = &tegra_sor_hdmi_ops; 3494c57997bcSThierry Reding sor->pad = TEGRA_IO_PAD_HDMI; 3495459cc2c6SThierry Reding } else if (sor->soc->supports_lvds) { 3496459cc2c6SThierry Reding dev_err(&pdev->dev, "LVDS not supported yet\n"); 3497459cc2c6SThierry Reding return -ENODEV; 3498459cc2c6SThierry Reding } else { 3499459cc2c6SThierry Reding dev_err(&pdev->dev, "unknown (non-DP) support\n"); 3500459cc2c6SThierry Reding return -ENODEV; 3501459cc2c6SThierry Reding } 3502459cc2c6SThierry Reding } else { 3503459cc2c6SThierry Reding if (sor->soc->supports_edp) { 3504459cc2c6SThierry Reding sor->ops = &tegra_sor_edp_ops; 3505c57997bcSThierry Reding sor->pad = TEGRA_IO_PAD_LVDS; 3506459cc2c6SThierry Reding } else if (sor->soc->supports_dp) { 3507459cc2c6SThierry Reding dev_err(&pdev->dev, "DisplayPort not supported yet\n"); 3508459cc2c6SThierry Reding return -ENODEV; 3509459cc2c6SThierry Reding } else { 3510459cc2c6SThierry Reding dev_err(&pdev->dev, "unknown (DP) support\n"); 3511459cc2c6SThierry Reding return -ENODEV; 3512459cc2c6SThierry Reding } 3513459cc2c6SThierry Reding } 3514459cc2c6SThierry Reding 3515c57997bcSThierry Reding err = tegra_sor_parse_dt(sor); 3516c57997bcSThierry Reding if (err < 0) 3517c57997bcSThierry Reding return err; 3518c57997bcSThierry Reding 35196b6b6042SThierry Reding err = tegra_output_probe(&sor->output); 35204dbdc740SThierry Reding if (err < 0) { 35214dbdc740SThierry Reding dev_err(&pdev->dev, "failed to probe output: %d\n", err); 35226b6b6042SThierry Reding return err; 35234dbdc740SThierry Reding } 35246b6b6042SThierry Reding 3525459cc2c6SThierry Reding if (sor->ops && sor->ops->probe) { 3526459cc2c6SThierry Reding err = sor->ops->probe(sor); 3527459cc2c6SThierry Reding if (err < 0) { 3528459cc2c6SThierry Reding dev_err(&pdev->dev, "failed to probe %s: %d\n", 3529459cc2c6SThierry Reding sor->ops->name, err); 3530459cc2c6SThierry Reding goto output; 3531459cc2c6SThierry Reding } 3532459cc2c6SThierry Reding } 3533459cc2c6SThierry Reding 35346b6b6042SThierry Reding regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 35356b6b6042SThierry Reding sor->regs = devm_ioremap_resource(&pdev->dev, regs); 3536459cc2c6SThierry Reding if (IS_ERR(sor->regs)) { 3537459cc2c6SThierry Reding err = PTR_ERR(sor->regs); 3538459cc2c6SThierry Reding goto remove; 3539459cc2c6SThierry Reding } 35406b6b6042SThierry Reding 35418e2988a7SThierry Reding err = platform_get_irq(pdev, 0); 35428e2988a7SThierry Reding if (err < 0) { 35438e2988a7SThierry Reding dev_err(&pdev->dev, "failed to get IRQ: %d\n", err); 35448e2988a7SThierry Reding goto remove; 35458e2988a7SThierry Reding } 35468e2988a7SThierry Reding 35478e2988a7SThierry Reding sor->irq = err; 35488e2988a7SThierry Reding 35498e2988a7SThierry Reding err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0, 35508e2988a7SThierry Reding dev_name(sor->dev), sor); 35518e2988a7SThierry Reding if (err < 0) { 35528e2988a7SThierry Reding dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); 35538e2988a7SThierry Reding goto remove; 35548e2988a7SThierry Reding } 35558e2988a7SThierry Reding 355611c632e1SThierry Reding sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor"); 35574dbdc740SThierry Reding if (IS_ERR(sor->rst)) { 3558459cc2c6SThierry Reding err = PTR_ERR(sor->rst); 3559180b46ecSThierry Reding 3560180b46ecSThierry Reding if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) { 3561f8c79120SJon Hunter dev_err(&pdev->dev, "failed to get reset control: %d\n", 3562f8c79120SJon Hunter err); 3563459cc2c6SThierry Reding goto remove; 35644dbdc740SThierry Reding } 3565180b46ecSThierry Reding 3566180b46ecSThierry Reding /* 3567180b46ecSThierry Reding * At this point, the reset control is most likely being used 3568180b46ecSThierry Reding * by the generic power domain implementation. With any luck 3569180b46ecSThierry Reding * the power domain will have taken care of resetting the SOR 3570180b46ecSThierry Reding * and we don't have to do anything. 3571180b46ecSThierry Reding */ 3572180b46ecSThierry Reding sor->rst = NULL; 3573f8c79120SJon Hunter } 35746b6b6042SThierry Reding 35756b6b6042SThierry Reding sor->clk = devm_clk_get(&pdev->dev, NULL); 35764dbdc740SThierry Reding if (IS_ERR(sor->clk)) { 3577459cc2c6SThierry Reding err = PTR_ERR(sor->clk); 3578459cc2c6SThierry Reding dev_err(&pdev->dev, "failed to get module clock: %d\n", err); 3579459cc2c6SThierry Reding goto remove; 35804dbdc740SThierry Reding } 35816b6b6042SThierry Reding 3582618dee39SThierry Reding if (sor->soc->supports_hdmi || sor->soc->supports_dp) { 3583e1335e2fSThierry Reding struct device_node *np = pdev->dev.of_node; 3584e1335e2fSThierry Reding const char *name; 3585e1335e2fSThierry Reding 3586e1335e2fSThierry Reding /* 3587e1335e2fSThierry Reding * For backwards compatibility with Tegra210 device trees, 3588e1335e2fSThierry Reding * fall back to the old clock name "source" if the new "out" 3589e1335e2fSThierry Reding * clock is not available. 3590e1335e2fSThierry Reding */ 3591e1335e2fSThierry Reding if (of_property_match_string(np, "clock-names", "out") < 0) 3592e1335e2fSThierry Reding name = "source"; 3593e1335e2fSThierry Reding else 3594e1335e2fSThierry Reding name = "out"; 3595e1335e2fSThierry Reding 3596e1335e2fSThierry Reding sor->clk_out = devm_clk_get(&pdev->dev, name); 3597e1335e2fSThierry Reding if (IS_ERR(sor->clk_out)) { 3598e1335e2fSThierry Reding err = PTR_ERR(sor->clk_out); 3599e1335e2fSThierry Reding dev_err(sor->dev, "failed to get %s clock: %d\n", 3600e1335e2fSThierry Reding name, err); 3601618dee39SThierry Reding goto remove; 3602618dee39SThierry Reding } 36031087fac1SThierry Reding } else { 3604d780537fSThierry Reding /* fall back to the module clock on SOR0 (eDP/LVDS only) */ 36051087fac1SThierry Reding sor->clk_out = sor->clk; 3606618dee39SThierry Reding } 3607618dee39SThierry Reding 36086b6b6042SThierry Reding sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); 36094dbdc740SThierry Reding if (IS_ERR(sor->clk_parent)) { 3610459cc2c6SThierry Reding err = PTR_ERR(sor->clk_parent); 3611459cc2c6SThierry Reding dev_err(&pdev->dev, "failed to get parent clock: %d\n", err); 3612459cc2c6SThierry Reding goto remove; 36134dbdc740SThierry Reding } 36146b6b6042SThierry Reding 36156b6b6042SThierry Reding sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); 36164dbdc740SThierry Reding if (IS_ERR(sor->clk_safe)) { 3617459cc2c6SThierry Reding err = PTR_ERR(sor->clk_safe); 3618459cc2c6SThierry Reding dev_err(&pdev->dev, "failed to get safe clock: %d\n", err); 3619459cc2c6SThierry Reding goto remove; 36204dbdc740SThierry Reding } 36216b6b6042SThierry Reding 36226b6b6042SThierry Reding sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); 36234dbdc740SThierry Reding if (IS_ERR(sor->clk_dp)) { 3624459cc2c6SThierry Reding err = PTR_ERR(sor->clk_dp); 3625459cc2c6SThierry Reding dev_err(&pdev->dev, "failed to get DP clock: %d\n", err); 3626459cc2c6SThierry Reding goto remove; 36274dbdc740SThierry Reding } 36286b6b6042SThierry Reding 3629e1335e2fSThierry Reding /* 3630e1335e2fSThierry Reding * Starting with Tegra186, the BPMP provides an implementation for 3631e1335e2fSThierry Reding * the pad output clock, so we have to look it up from device tree. 3632e1335e2fSThierry Reding */ 3633e1335e2fSThierry Reding sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); 3634e1335e2fSThierry Reding if (IS_ERR(sor->clk_pad)) { 3635e1335e2fSThierry Reding if (sor->clk_pad != ERR_PTR(-ENOENT)) { 3636e1335e2fSThierry Reding err = PTR_ERR(sor->clk_pad); 3637e1335e2fSThierry Reding goto remove; 3638e1335e2fSThierry Reding } 3639e1335e2fSThierry Reding 3640e1335e2fSThierry Reding /* 3641e1335e2fSThierry Reding * If the pad output clock is not available, then we assume 3642e1335e2fSThierry Reding * we're on Tegra210 or earlier and have to provide our own 3643e1335e2fSThierry Reding * implementation. 3644e1335e2fSThierry Reding */ 3645e1335e2fSThierry Reding sor->clk_pad = NULL; 3646e1335e2fSThierry Reding } 3647e1335e2fSThierry Reding 3648e1335e2fSThierry Reding /* 3649e1335e2fSThierry Reding * The bootloader may have set up the SOR such that it's module clock 3650e1335e2fSThierry Reding * is sourced by one of the display PLLs. However, that doesn't work 3651e1335e2fSThierry Reding * without properly having set up other bits of the SOR. 3652e1335e2fSThierry Reding */ 3653e1335e2fSThierry Reding err = clk_set_parent(sor->clk_out, sor->clk_safe); 3654e1335e2fSThierry Reding if (err < 0) { 3655e1335e2fSThierry Reding dev_err(&pdev->dev, "failed to use safe clock: %d\n", err); 3656e1335e2fSThierry Reding goto remove; 3657e1335e2fSThierry Reding } 3658e1335e2fSThierry Reding 3659aaff8bd2SThierry Reding platform_set_drvdata(pdev, sor); 3660aaff8bd2SThierry Reding pm_runtime_enable(&pdev->dev); 3661aaff8bd2SThierry Reding 3662e1335e2fSThierry Reding /* 3663e1335e2fSThierry Reding * On Tegra210 and earlier, provide our own implementation for the 3664e1335e2fSThierry Reding * pad output clock. 3665e1335e2fSThierry Reding */ 3666e1335e2fSThierry Reding if (!sor->clk_pad) { 3667e1335e2fSThierry Reding err = pm_runtime_get_sync(&pdev->dev); 3668e1335e2fSThierry Reding if (err < 0) { 3669e1335e2fSThierry Reding dev_err(&pdev->dev, "failed to get runtime PM: %d\n", 3670e1335e2fSThierry Reding err); 3671e1335e2fSThierry Reding goto remove; 3672e1335e2fSThierry Reding } 3673b299221cSThierry Reding 3674e1335e2fSThierry Reding sor->clk_pad = tegra_clk_sor_pad_register(sor, 3675e1335e2fSThierry Reding "sor1_pad_clkout"); 3676e1335e2fSThierry Reding pm_runtime_put(&pdev->dev); 3677e1335e2fSThierry Reding } 3678e1335e2fSThierry Reding 3679e1335e2fSThierry Reding if (IS_ERR(sor->clk_pad)) { 3680e1335e2fSThierry Reding err = PTR_ERR(sor->clk_pad); 3681e1335e2fSThierry Reding dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n", 3682e1335e2fSThierry Reding err); 3683b299221cSThierry Reding goto remove; 3684b299221cSThierry Reding } 3685b299221cSThierry Reding 36866b6b6042SThierry Reding INIT_LIST_HEAD(&sor->client.list); 36876b6b6042SThierry Reding sor->client.ops = &sor_client_ops; 36886b6b6042SThierry Reding sor->client.dev = &pdev->dev; 36896b6b6042SThierry Reding 36906b6b6042SThierry Reding err = host1x_client_register(&sor->client); 36916b6b6042SThierry Reding if (err < 0) { 36926b6b6042SThierry Reding dev_err(&pdev->dev, "failed to register host1x client: %d\n", 36936b6b6042SThierry Reding err); 3694459cc2c6SThierry Reding goto remove; 36956b6b6042SThierry Reding } 36966b6b6042SThierry Reding 36976b6b6042SThierry Reding return 0; 3698459cc2c6SThierry Reding 3699459cc2c6SThierry Reding remove: 3700459cc2c6SThierry Reding if (sor->ops && sor->ops->remove) 3701459cc2c6SThierry Reding sor->ops->remove(sor); 3702459cc2c6SThierry Reding output: 3703459cc2c6SThierry Reding tegra_output_remove(&sor->output); 3704459cc2c6SThierry Reding return err; 37056b6b6042SThierry Reding } 37066b6b6042SThierry Reding 37076b6b6042SThierry Reding static int tegra_sor_remove(struct platform_device *pdev) 37086b6b6042SThierry Reding { 37096b6b6042SThierry Reding struct tegra_sor *sor = platform_get_drvdata(pdev); 37106b6b6042SThierry Reding int err; 37116b6b6042SThierry Reding 3712aaff8bd2SThierry Reding pm_runtime_disable(&pdev->dev); 3713aaff8bd2SThierry Reding 37146b6b6042SThierry Reding err = host1x_client_unregister(&sor->client); 37156b6b6042SThierry Reding if (err < 0) { 37166b6b6042SThierry Reding dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 37176b6b6042SThierry Reding err); 37186b6b6042SThierry Reding return err; 37196b6b6042SThierry Reding } 37206b6b6042SThierry Reding 3721459cc2c6SThierry Reding if (sor->ops && sor->ops->remove) { 3722459cc2c6SThierry Reding err = sor->ops->remove(sor); 3723459cc2c6SThierry Reding if (err < 0) 3724459cc2c6SThierry Reding dev_err(&pdev->dev, "failed to remove SOR: %d\n", err); 3725459cc2c6SThierry Reding } 3726459cc2c6SThierry Reding 3727328ec69eSThierry Reding tegra_output_remove(&sor->output); 37286b6b6042SThierry Reding 37296b6b6042SThierry Reding return 0; 37306b6b6042SThierry Reding } 37316b6b6042SThierry Reding 3732aaff8bd2SThierry Reding #ifdef CONFIG_PM 3733aaff8bd2SThierry Reding static int tegra_sor_suspend(struct device *dev) 3734aaff8bd2SThierry Reding { 3735aaff8bd2SThierry Reding struct tegra_sor *sor = dev_get_drvdata(dev); 3736aaff8bd2SThierry Reding int err; 3737aaff8bd2SThierry Reding 3738f8c79120SJon Hunter if (sor->rst) { 3739aaff8bd2SThierry Reding err = reset_control_assert(sor->rst); 3740aaff8bd2SThierry Reding if (err < 0) { 3741aaff8bd2SThierry Reding dev_err(dev, "failed to assert reset: %d\n", err); 3742aaff8bd2SThierry Reding return err; 3743aaff8bd2SThierry Reding } 374411c632e1SThierry Reding 374511c632e1SThierry Reding reset_control_release(sor->rst); 3746f8c79120SJon Hunter } 3747aaff8bd2SThierry Reding 3748aaff8bd2SThierry Reding usleep_range(1000, 2000); 3749aaff8bd2SThierry Reding 3750aaff8bd2SThierry Reding clk_disable_unprepare(sor->clk); 3751aaff8bd2SThierry Reding 3752aaff8bd2SThierry Reding return 0; 3753aaff8bd2SThierry Reding } 3754aaff8bd2SThierry Reding 3755aaff8bd2SThierry Reding static int tegra_sor_resume(struct device *dev) 3756aaff8bd2SThierry Reding { 3757aaff8bd2SThierry Reding struct tegra_sor *sor = dev_get_drvdata(dev); 3758aaff8bd2SThierry Reding int err; 3759aaff8bd2SThierry Reding 3760aaff8bd2SThierry Reding err = clk_prepare_enable(sor->clk); 3761aaff8bd2SThierry Reding if (err < 0) { 3762aaff8bd2SThierry Reding dev_err(dev, "failed to enable clock: %d\n", err); 3763aaff8bd2SThierry Reding return err; 3764aaff8bd2SThierry Reding } 3765aaff8bd2SThierry Reding 3766aaff8bd2SThierry Reding usleep_range(1000, 2000); 3767aaff8bd2SThierry Reding 3768f8c79120SJon Hunter if (sor->rst) { 376911c632e1SThierry Reding err = reset_control_acquire(sor->rst); 377011c632e1SThierry Reding if (err < 0) { 377111c632e1SThierry Reding dev_err(dev, "failed to acquire reset: %d\n", err); 377211c632e1SThierry Reding clk_disable_unprepare(sor->clk); 377311c632e1SThierry Reding return err; 377411c632e1SThierry Reding } 377511c632e1SThierry Reding 3776aaff8bd2SThierry Reding err = reset_control_deassert(sor->rst); 3777aaff8bd2SThierry Reding if (err < 0) { 3778aaff8bd2SThierry Reding dev_err(dev, "failed to deassert reset: %d\n", err); 377911c632e1SThierry Reding reset_control_release(sor->rst); 3780aaff8bd2SThierry Reding clk_disable_unprepare(sor->clk); 3781aaff8bd2SThierry Reding return err; 3782aaff8bd2SThierry Reding } 3783f8c79120SJon Hunter } 3784aaff8bd2SThierry Reding 3785aaff8bd2SThierry Reding return 0; 3786aaff8bd2SThierry Reding } 3787aaff8bd2SThierry Reding #endif 3788aaff8bd2SThierry Reding 3789aaff8bd2SThierry Reding static const struct dev_pm_ops tegra_sor_pm_ops = { 3790aaff8bd2SThierry Reding SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL) 3791aaff8bd2SThierry Reding }; 3792aaff8bd2SThierry Reding 37936b6b6042SThierry Reding struct platform_driver tegra_sor_driver = { 37946b6b6042SThierry Reding .driver = { 37956b6b6042SThierry Reding .name = "tegra-sor", 37966b6b6042SThierry Reding .of_match_table = tegra_sor_of_match, 3797aaff8bd2SThierry Reding .pm = &tegra_sor_pm_ops, 37986b6b6042SThierry Reding }, 37996b6b6042SThierry Reding .probe = tegra_sor_probe, 38006b6b6042SThierry Reding .remove = tegra_sor_remove, 38016b6b6042SThierry Reding }; 3802