1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/iommu.h> 7 #include <linux/interconnect.h> 8 9 #include <drm/drm_atomic.h> 10 #include <drm/drm_atomic_helper.h> 11 #include <drm/drm_fourcc.h> 12 #include <drm/drm_gem_atomic_helper.h> 13 #include <drm/drm_plane_helper.h> 14 15 #include "dc.h" 16 #include "plane.h" 17 18 static void tegra_plane_destroy(struct drm_plane *plane) 19 { 20 struct tegra_plane *p = to_tegra_plane(plane); 21 22 drm_plane_cleanup(plane); 23 kfree(p); 24 } 25 26 static void tegra_plane_reset(struct drm_plane *plane) 27 { 28 struct tegra_plane *p = to_tegra_plane(plane); 29 struct tegra_plane_state *state; 30 unsigned int i; 31 32 if (plane->state) 33 __drm_atomic_helper_plane_destroy_state(plane->state); 34 35 kfree(plane->state); 36 plane->state = NULL; 37 38 state = kzalloc(sizeof(*state), GFP_KERNEL); 39 if (state) { 40 plane->state = &state->base; 41 plane->state->plane = plane; 42 plane->state->zpos = p->index; 43 plane->state->normalized_zpos = p->index; 44 45 for (i = 0; i < 3; i++) 46 state->iova[i] = DMA_MAPPING_ERROR; 47 } 48 } 49 50 static struct drm_plane_state * 51 tegra_plane_atomic_duplicate_state(struct drm_plane *plane) 52 { 53 struct tegra_plane_state *state = to_tegra_plane_state(plane->state); 54 struct tegra_plane_state *copy; 55 unsigned int i; 56 57 copy = kmalloc(sizeof(*copy), GFP_KERNEL); 58 if (!copy) 59 return NULL; 60 61 __drm_atomic_helper_plane_duplicate_state(plane, ©->base); 62 copy->tiling = state->tiling; 63 copy->format = state->format; 64 copy->swap = state->swap; 65 copy->reflect_x = state->reflect_x; 66 copy->reflect_y = state->reflect_y; 67 copy->opaque = state->opaque; 68 copy->total_peak_memory_bandwidth = state->total_peak_memory_bandwidth; 69 copy->peak_memory_bandwidth = state->peak_memory_bandwidth; 70 copy->avg_memory_bandwidth = state->avg_memory_bandwidth; 71 72 for (i = 0; i < 2; i++) 73 copy->blending[i] = state->blending[i]; 74 75 for (i = 0; i < 3; i++) { 76 copy->iova[i] = DMA_MAPPING_ERROR; 77 copy->map[i] = NULL; 78 } 79 80 return ©->base; 81 } 82 83 static void tegra_plane_atomic_destroy_state(struct drm_plane *plane, 84 struct drm_plane_state *state) 85 { 86 __drm_atomic_helper_plane_destroy_state(state); 87 kfree(state); 88 } 89 90 static bool tegra_plane_supports_sector_layout(struct drm_plane *plane) 91 { 92 struct drm_crtc *crtc; 93 94 drm_for_each_crtc(crtc, plane->dev) { 95 if (plane->possible_crtcs & drm_crtc_mask(crtc)) { 96 struct tegra_dc *dc = to_tegra_dc(crtc); 97 98 if (!dc->soc->supports_sector_layout) 99 return false; 100 } 101 } 102 103 return true; 104 } 105 106 static bool tegra_plane_format_mod_supported(struct drm_plane *plane, 107 uint32_t format, 108 uint64_t modifier) 109 { 110 const struct drm_format_info *info = drm_format_info(format); 111 112 if (modifier == DRM_FORMAT_MOD_LINEAR) 113 return true; 114 115 /* check for the sector layout bit */ 116 if (fourcc_mod_is_vendor(modifier, NVIDIA)) { 117 if (modifier & DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT) { 118 if (!tegra_plane_supports_sector_layout(plane)) 119 return false; 120 } 121 } 122 123 if (info->num_planes == 1) 124 return true; 125 126 return false; 127 } 128 129 const struct drm_plane_funcs tegra_plane_funcs = { 130 .update_plane = drm_atomic_helper_update_plane, 131 .disable_plane = drm_atomic_helper_disable_plane, 132 .destroy = tegra_plane_destroy, 133 .reset = tegra_plane_reset, 134 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, 135 .atomic_destroy_state = tegra_plane_atomic_destroy_state, 136 .format_mod_supported = tegra_plane_format_mod_supported, 137 }; 138 139 static int tegra_dc_pin(struct tegra_dc *dc, struct tegra_plane_state *state) 140 { 141 unsigned int i; 142 int err; 143 144 for (i = 0; i < state->base.fb->format->num_planes; i++) { 145 struct tegra_bo *bo = tegra_fb_get_plane(state->base.fb, i); 146 struct host1x_bo_mapping *map; 147 148 map = host1x_bo_pin(dc->dev, &bo->base, DMA_TO_DEVICE); 149 if (IS_ERR(map)) { 150 err = PTR_ERR(map); 151 goto unpin; 152 } 153 154 if (!dc->client.group) { 155 /* 156 * The display controller needs contiguous memory, so 157 * fail if the buffer is discontiguous and we fail to 158 * map its SG table to a single contiguous chunk of 159 * I/O virtual memory. 160 */ 161 if (map->chunks > 1) { 162 err = -EINVAL; 163 goto unpin; 164 } 165 166 state->iova[i] = map->phys; 167 } else { 168 state->iova[i] = bo->iova; 169 } 170 171 state->map[i] = map; 172 } 173 174 return 0; 175 176 unpin: 177 dev_err(dc->dev, "failed to map plane %u: %d\n", i, err); 178 179 while (i--) { 180 host1x_bo_unpin(state->map[i]); 181 state->iova[i] = DMA_MAPPING_ERROR; 182 state->map[i] = NULL; 183 } 184 185 return err; 186 } 187 188 static void tegra_dc_unpin(struct tegra_dc *dc, struct tegra_plane_state *state) 189 { 190 unsigned int i; 191 192 for (i = 0; i < state->base.fb->format->num_planes; i++) { 193 host1x_bo_unpin(state->map[i]); 194 state->iova[i] = DMA_MAPPING_ERROR; 195 state->map[i] = NULL; 196 } 197 } 198 199 int tegra_plane_prepare_fb(struct drm_plane *plane, 200 struct drm_plane_state *state) 201 { 202 struct tegra_dc *dc = to_tegra_dc(state->crtc); 203 204 if (!state->fb) 205 return 0; 206 207 drm_gem_plane_helper_prepare_fb(plane, state); 208 209 return tegra_dc_pin(dc, to_tegra_plane_state(state)); 210 } 211 212 void tegra_plane_cleanup_fb(struct drm_plane *plane, 213 struct drm_plane_state *state) 214 { 215 struct tegra_dc *dc = to_tegra_dc(state->crtc); 216 217 if (dc) 218 tegra_dc_unpin(dc, to_tegra_plane_state(state)); 219 } 220 221 static int tegra_plane_calculate_memory_bandwidth(struct drm_plane_state *state) 222 { 223 struct tegra_plane_state *tegra_state = to_tegra_plane_state(state); 224 unsigned int i, bpp, dst_w, dst_h, src_w, src_h, mul; 225 const struct tegra_dc_soc_info *soc; 226 const struct drm_format_info *fmt; 227 struct drm_crtc_state *crtc_state; 228 u64 avg_bandwidth, peak_bandwidth; 229 230 if (!state->visible) 231 return 0; 232 233 crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); 234 if (!crtc_state) 235 return -EINVAL; 236 237 src_w = drm_rect_width(&state->src) >> 16; 238 src_h = drm_rect_height(&state->src) >> 16; 239 dst_w = drm_rect_width(&state->dst); 240 dst_h = drm_rect_height(&state->dst); 241 242 fmt = state->fb->format; 243 soc = to_tegra_dc(state->crtc)->soc; 244 245 /* 246 * Note that real memory bandwidth vary depending on format and 247 * memory layout, we are not taking that into account because small 248 * estimation error isn't important since bandwidth is rounded up 249 * anyway. 250 */ 251 for (i = 0, bpp = 0; i < fmt->num_planes; i++) { 252 unsigned int bpp_plane = fmt->cpp[i] * 8; 253 254 /* 255 * Sub-sampling is relevant for chroma planes only and vertical 256 * readouts are not cached, hence only horizontal sub-sampling 257 * matters. 258 */ 259 if (i > 0) 260 bpp_plane /= fmt->hsub; 261 262 bpp += bpp_plane; 263 } 264 265 /* average bandwidth in kbytes/sec */ 266 avg_bandwidth = min(src_w, dst_w) * min(src_h, dst_h); 267 avg_bandwidth *= drm_mode_vrefresh(&crtc_state->adjusted_mode); 268 avg_bandwidth = DIV_ROUND_UP(avg_bandwidth * bpp, 8) + 999; 269 do_div(avg_bandwidth, 1000); 270 271 /* mode.clock in kHz, peak bandwidth in kbytes/sec */ 272 peak_bandwidth = DIV_ROUND_UP(crtc_state->adjusted_mode.clock * bpp, 8); 273 274 /* 275 * Tegra30/114 Memory Controller can't interleave DC memory requests 276 * for the tiled windows because DC uses 16-bytes atom, while DDR3 277 * uses 32-bytes atom. Hence there is x2 memory overfetch for tiled 278 * framebuffer and DDR3 on these SoCs. 279 */ 280 if (soc->plane_tiled_memory_bandwidth_x2 && 281 tegra_state->tiling.mode == TEGRA_BO_TILING_MODE_TILED) 282 mul = 2; 283 else 284 mul = 1; 285 286 /* ICC bandwidth in kbytes/sec */ 287 tegra_state->peak_memory_bandwidth = kBps_to_icc(peak_bandwidth) * mul; 288 tegra_state->avg_memory_bandwidth = kBps_to_icc(avg_bandwidth) * mul; 289 290 return 0; 291 } 292 293 int tegra_plane_state_add(struct tegra_plane *plane, 294 struct drm_plane_state *state) 295 { 296 struct drm_crtc_state *crtc_state; 297 struct tegra_dc_state *tegra; 298 int err; 299 300 /* Propagate errors from allocation or locking failures. */ 301 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); 302 if (IS_ERR(crtc_state)) 303 return PTR_ERR(crtc_state); 304 305 /* Check plane state for visibility and calculate clipping bounds */ 306 err = drm_atomic_helper_check_plane_state(state, crtc_state, 307 0, INT_MAX, true, true); 308 if (err < 0) 309 return err; 310 311 err = tegra_plane_calculate_memory_bandwidth(state); 312 if (err < 0) 313 return err; 314 315 tegra = to_dc_state(crtc_state); 316 317 tegra->planes |= WIN_A_ACT_REQ << plane->index; 318 319 return 0; 320 } 321 322 int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap) 323 { 324 /* assume no swapping of fetched data */ 325 if (swap) 326 *swap = BYTE_SWAP_NOSWAP; 327 328 switch (fourcc) { 329 case DRM_FORMAT_ARGB4444: 330 *format = WIN_COLOR_DEPTH_B4G4R4A4; 331 break; 332 333 case DRM_FORMAT_ARGB1555: 334 *format = WIN_COLOR_DEPTH_B5G5R5A1; 335 break; 336 337 case DRM_FORMAT_RGB565: 338 *format = WIN_COLOR_DEPTH_B5G6R5; 339 break; 340 341 case DRM_FORMAT_RGBA5551: 342 *format = WIN_COLOR_DEPTH_A1B5G5R5; 343 break; 344 345 case DRM_FORMAT_ARGB8888: 346 *format = WIN_COLOR_DEPTH_B8G8R8A8; 347 break; 348 349 case DRM_FORMAT_ABGR8888: 350 *format = WIN_COLOR_DEPTH_R8G8B8A8; 351 break; 352 353 case DRM_FORMAT_ABGR4444: 354 *format = WIN_COLOR_DEPTH_R4G4B4A4; 355 break; 356 357 case DRM_FORMAT_ABGR1555: 358 *format = WIN_COLOR_DEPTH_R5G5B5A; 359 break; 360 361 case DRM_FORMAT_BGRA5551: 362 *format = WIN_COLOR_DEPTH_AR5G5B5; 363 break; 364 365 case DRM_FORMAT_XRGB1555: 366 *format = WIN_COLOR_DEPTH_B5G5R5X1; 367 break; 368 369 case DRM_FORMAT_RGBX5551: 370 *format = WIN_COLOR_DEPTH_X1B5G5R5; 371 break; 372 373 case DRM_FORMAT_XBGR1555: 374 *format = WIN_COLOR_DEPTH_R5G5B5X1; 375 break; 376 377 case DRM_FORMAT_BGRX5551: 378 *format = WIN_COLOR_DEPTH_X1R5G5B5; 379 break; 380 381 case DRM_FORMAT_BGR565: 382 *format = WIN_COLOR_DEPTH_R5G6B5; 383 break; 384 385 case DRM_FORMAT_BGRA8888: 386 *format = WIN_COLOR_DEPTH_A8R8G8B8; 387 break; 388 389 case DRM_FORMAT_RGBA8888: 390 *format = WIN_COLOR_DEPTH_A8B8G8R8; 391 break; 392 393 case DRM_FORMAT_XRGB8888: 394 *format = WIN_COLOR_DEPTH_B8G8R8X8; 395 break; 396 397 case DRM_FORMAT_XBGR8888: 398 *format = WIN_COLOR_DEPTH_R8G8B8X8; 399 break; 400 401 case DRM_FORMAT_UYVY: 402 *format = WIN_COLOR_DEPTH_YCbCr422; 403 break; 404 405 case DRM_FORMAT_YUYV: 406 if (!swap) 407 return -EINVAL; 408 409 *format = WIN_COLOR_DEPTH_YCbCr422; 410 *swap = BYTE_SWAP_SWAP2; 411 break; 412 413 case DRM_FORMAT_YUV420: 414 *format = WIN_COLOR_DEPTH_YCbCr420P; 415 break; 416 417 case DRM_FORMAT_YUV422: 418 *format = WIN_COLOR_DEPTH_YCbCr422P; 419 break; 420 421 default: 422 return -EINVAL; 423 } 424 425 return 0; 426 } 427 428 bool tegra_plane_format_is_indexed(unsigned int format) 429 { 430 switch (format) { 431 case WIN_COLOR_DEPTH_P1: 432 case WIN_COLOR_DEPTH_P2: 433 case WIN_COLOR_DEPTH_P4: 434 case WIN_COLOR_DEPTH_P8: 435 return true; 436 } 437 438 return false; 439 } 440 441 bool tegra_plane_format_is_yuv(unsigned int format, bool *planar, unsigned int *bpc) 442 { 443 switch (format) { 444 case WIN_COLOR_DEPTH_YCbCr422: 445 case WIN_COLOR_DEPTH_YUV422: 446 if (planar) 447 *planar = false; 448 449 if (bpc) 450 *bpc = 8; 451 452 return true; 453 454 case WIN_COLOR_DEPTH_YCbCr420P: 455 case WIN_COLOR_DEPTH_YUV420P: 456 case WIN_COLOR_DEPTH_YCbCr422P: 457 case WIN_COLOR_DEPTH_YUV422P: 458 case WIN_COLOR_DEPTH_YCbCr422R: 459 case WIN_COLOR_DEPTH_YUV422R: 460 case WIN_COLOR_DEPTH_YCbCr422RA: 461 case WIN_COLOR_DEPTH_YUV422RA: 462 if (planar) 463 *planar = true; 464 465 if (bpc) 466 *bpc = 8; 467 468 return true; 469 } 470 471 if (planar) 472 *planar = false; 473 474 return false; 475 } 476 477 static bool __drm_format_has_alpha(u32 format) 478 { 479 switch (format) { 480 case DRM_FORMAT_ARGB1555: 481 case DRM_FORMAT_RGBA5551: 482 case DRM_FORMAT_ABGR8888: 483 case DRM_FORMAT_ARGB8888: 484 return true; 485 } 486 487 return false; 488 } 489 490 static int tegra_plane_format_get_alpha(unsigned int opaque, 491 unsigned int *alpha) 492 { 493 if (tegra_plane_format_is_yuv(opaque, NULL, NULL)) { 494 *alpha = opaque; 495 return 0; 496 } 497 498 switch (opaque) { 499 case WIN_COLOR_DEPTH_B5G5R5X1: 500 *alpha = WIN_COLOR_DEPTH_B5G5R5A1; 501 return 0; 502 503 case WIN_COLOR_DEPTH_X1B5G5R5: 504 *alpha = WIN_COLOR_DEPTH_A1B5G5R5; 505 return 0; 506 507 case WIN_COLOR_DEPTH_R8G8B8X8: 508 *alpha = WIN_COLOR_DEPTH_R8G8B8A8; 509 return 0; 510 511 case WIN_COLOR_DEPTH_B8G8R8X8: 512 *alpha = WIN_COLOR_DEPTH_B8G8R8A8; 513 return 0; 514 515 case WIN_COLOR_DEPTH_B5G6R5: 516 *alpha = opaque; 517 return 0; 518 } 519 520 return -EINVAL; 521 } 522 523 /* 524 * This is applicable to Tegra20 and Tegra30 only where the opaque formats can 525 * be emulated using the alpha formats and alpha blending disabled. 526 */ 527 static int tegra_plane_setup_opacity(struct tegra_plane *tegra, 528 struct tegra_plane_state *state) 529 { 530 unsigned int format; 531 int err; 532 533 switch (state->format) { 534 case WIN_COLOR_DEPTH_B5G5R5A1: 535 case WIN_COLOR_DEPTH_A1B5G5R5: 536 case WIN_COLOR_DEPTH_R8G8B8A8: 537 case WIN_COLOR_DEPTH_B8G8R8A8: 538 state->opaque = false; 539 break; 540 541 default: 542 err = tegra_plane_format_get_alpha(state->format, &format); 543 if (err < 0) 544 return err; 545 546 state->format = format; 547 state->opaque = true; 548 break; 549 } 550 551 return 0; 552 } 553 554 static int tegra_plane_check_transparency(struct tegra_plane *tegra, 555 struct tegra_plane_state *state) 556 { 557 struct drm_plane_state *old, *plane_state; 558 struct drm_plane *plane; 559 560 old = drm_atomic_get_old_plane_state(state->base.state, &tegra->base); 561 562 /* check if zpos / transparency changed */ 563 if (old->normalized_zpos == state->base.normalized_zpos && 564 to_tegra_plane_state(old)->opaque == state->opaque) 565 return 0; 566 567 /* include all sibling planes into this commit */ 568 drm_for_each_plane(plane, tegra->base.dev) { 569 struct tegra_plane *p = to_tegra_plane(plane); 570 571 /* skip this plane and planes on different CRTCs */ 572 if (p == tegra || p->dc != tegra->dc) 573 continue; 574 575 plane_state = drm_atomic_get_plane_state(state->base.state, 576 plane); 577 if (IS_ERR(plane_state)) 578 return PTR_ERR(plane_state); 579 } 580 581 return 1; 582 } 583 584 static unsigned int tegra_plane_get_overlap_index(struct tegra_plane *plane, 585 struct tegra_plane *other) 586 { 587 unsigned int index = 0, i; 588 589 WARN_ON(plane == other); 590 591 for (i = 0; i < 3; i++) { 592 if (i == plane->index) 593 continue; 594 595 if (i == other->index) 596 break; 597 598 index++; 599 } 600 601 return index; 602 } 603 604 static void tegra_plane_update_transparency(struct tegra_plane *tegra, 605 struct tegra_plane_state *state) 606 { 607 struct drm_plane_state *new; 608 struct drm_plane *plane; 609 unsigned int i; 610 611 for_each_new_plane_in_state(state->base.state, plane, new, i) { 612 struct tegra_plane *p = to_tegra_plane(plane); 613 unsigned index; 614 615 /* skip this plane and planes on different CRTCs */ 616 if (p == tegra || p->dc != tegra->dc) 617 continue; 618 619 index = tegra_plane_get_overlap_index(tegra, p); 620 621 if (new->fb && __drm_format_has_alpha(new->fb->format->format)) 622 state->blending[index].alpha = true; 623 else 624 state->blending[index].alpha = false; 625 626 if (new->normalized_zpos > state->base.normalized_zpos) 627 state->blending[index].top = true; 628 else 629 state->blending[index].top = false; 630 631 /* 632 * Missing framebuffer means that plane is disabled, in this 633 * case mark B / C window as top to be able to differentiate 634 * windows indices order in regards to zPos for the middle 635 * window X / Y registers programming. 636 */ 637 if (!new->fb) 638 state->blending[index].top = (index == 1); 639 } 640 } 641 642 static int tegra_plane_setup_transparency(struct tegra_plane *tegra, 643 struct tegra_plane_state *state) 644 { 645 struct tegra_plane_state *tegra_state; 646 struct drm_plane_state *new; 647 struct drm_plane *plane; 648 int err; 649 650 /* 651 * If planes zpos / transparency changed, sibling planes blending 652 * state may require adjustment and in this case they will be included 653 * into this atom commit, otherwise blending state is unchanged. 654 */ 655 err = tegra_plane_check_transparency(tegra, state); 656 if (err <= 0) 657 return err; 658 659 /* 660 * All planes are now in the atomic state, walk them up and update 661 * transparency state for each plane. 662 */ 663 drm_for_each_plane(plane, tegra->base.dev) { 664 struct tegra_plane *p = to_tegra_plane(plane); 665 666 /* skip planes on different CRTCs */ 667 if (p->dc != tegra->dc) 668 continue; 669 670 new = drm_atomic_get_new_plane_state(state->base.state, plane); 671 tegra_state = to_tegra_plane_state(new); 672 673 /* 674 * There is no need to update blending state for the disabled 675 * plane. 676 */ 677 if (new->fb) 678 tegra_plane_update_transparency(p, tegra_state); 679 } 680 681 return 0; 682 } 683 684 int tegra_plane_setup_legacy_state(struct tegra_plane *tegra, 685 struct tegra_plane_state *state) 686 { 687 int err; 688 689 err = tegra_plane_setup_opacity(tegra, state); 690 if (err < 0) 691 return err; 692 693 err = tegra_plane_setup_transparency(tegra, state); 694 if (err < 0) 695 return err; 696 697 return 0; 698 } 699 700 static const char * const tegra_plane_icc_names[TEGRA_DC_LEGACY_PLANES_NUM] = { 701 "wina", "winb", "winc", NULL, NULL, NULL, "cursor", 702 }; 703 704 int tegra_plane_interconnect_init(struct tegra_plane *plane) 705 { 706 const char *icc_name = tegra_plane_icc_names[plane->index]; 707 struct device *dev = plane->dc->dev; 708 struct tegra_dc *dc = plane->dc; 709 int err; 710 711 if (WARN_ON(plane->index >= TEGRA_DC_LEGACY_PLANES_NUM) || 712 WARN_ON(!tegra_plane_icc_names[plane->index])) 713 return -EINVAL; 714 715 plane->icc_mem = devm_of_icc_get(dev, icc_name); 716 err = PTR_ERR_OR_ZERO(plane->icc_mem); 717 if (err) { 718 dev_err_probe(dev, err, "failed to get %s interconnect\n", 719 icc_name); 720 return err; 721 } 722 723 /* plane B on T20/30 has a dedicated memory client for a 6-tap vertical filter */ 724 if (plane->index == 1 && dc->soc->has_win_b_vfilter_mem_client) { 725 plane->icc_mem_vfilter = devm_of_icc_get(dev, "winb-vfilter"); 726 err = PTR_ERR_OR_ZERO(plane->icc_mem_vfilter); 727 if (err) { 728 dev_err_probe(dev, err, "failed to get %s interconnect\n", 729 "winb-vfilter"); 730 return err; 731 } 732 } 733 734 return 0; 735 } 736