1 /* 2 * Copyright (C) 2013 NVIDIA Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/debugfs.h> 11 #include <linux/host1x.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 19 #include <linux/regulator/consumer.h> 20 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_mipi_dsi.h> 23 #include <drm/drm_panel.h> 24 25 #include <video/mipi_display.h> 26 27 #include "dc.h" 28 #include "drm.h" 29 #include "dsi.h" 30 #include "mipi-phy.h" 31 #include "trace.h" 32 33 struct tegra_dsi_state { 34 struct drm_connector_state base; 35 36 struct mipi_dphy_timing timing; 37 unsigned long period; 38 39 unsigned int vrefresh; 40 unsigned int lanes; 41 unsigned long pclk; 42 unsigned long bclk; 43 44 enum tegra_dsi_format format; 45 unsigned int mul; 46 unsigned int div; 47 }; 48 49 static inline struct tegra_dsi_state * 50 to_dsi_state(struct drm_connector_state *state) 51 { 52 return container_of(state, struct tegra_dsi_state, base); 53 } 54 55 struct tegra_dsi { 56 struct host1x_client client; 57 struct tegra_output output; 58 struct device *dev; 59 60 void __iomem *regs; 61 62 struct reset_control *rst; 63 struct clk *clk_parent; 64 struct clk *clk_lp; 65 struct clk *clk; 66 67 struct drm_info_list *debugfs_files; 68 struct drm_minor *minor; 69 struct dentry *debugfs; 70 71 unsigned long flags; 72 enum mipi_dsi_pixel_format format; 73 unsigned int lanes; 74 75 struct tegra_mipi_device *mipi; 76 struct mipi_dsi_host host; 77 78 struct regulator *vdd; 79 80 unsigned int video_fifo_depth; 81 unsigned int host_fifo_depth; 82 83 /* for ganged-mode support */ 84 struct tegra_dsi *master; 85 struct tegra_dsi *slave; 86 }; 87 88 static inline struct tegra_dsi * 89 host1x_client_to_dsi(struct host1x_client *client) 90 { 91 return container_of(client, struct tegra_dsi, client); 92 } 93 94 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host) 95 { 96 return container_of(host, struct tegra_dsi, host); 97 } 98 99 static inline struct tegra_dsi *to_dsi(struct tegra_output *output) 100 { 101 return container_of(output, struct tegra_dsi, output); 102 } 103 104 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) 105 { 106 return to_dsi_state(dsi->output.connector.state); 107 } 108 109 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) 110 { 111 u32 value = readl(dsi->regs + (offset << 2)); 112 113 trace_dsi_readl(dsi->dev, offset, value); 114 115 return value; 116 } 117 118 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, 119 unsigned int offset) 120 { 121 trace_dsi_writel(dsi->dev, offset, value); 122 writel(value, dsi->regs + (offset << 2)); 123 } 124 125 static int tegra_dsi_show_regs(struct seq_file *s, void *data) 126 { 127 struct drm_info_node *node = s->private; 128 struct tegra_dsi *dsi = node->info_ent->data; 129 struct drm_crtc *crtc = dsi->output.encoder.crtc; 130 struct drm_device *drm = node->minor->dev; 131 int err = 0; 132 133 drm_modeset_lock_all(drm); 134 135 if (!crtc || !crtc->state->active) { 136 err = -EBUSY; 137 goto unlock; 138 } 139 140 #define DUMP_REG(name) \ 141 seq_printf(s, "%-32s %#05x %08x\n", #name, name, \ 142 tegra_dsi_readl(dsi, name)) 143 144 DUMP_REG(DSI_INCR_SYNCPT); 145 DUMP_REG(DSI_INCR_SYNCPT_CONTROL); 146 DUMP_REG(DSI_INCR_SYNCPT_ERROR); 147 DUMP_REG(DSI_CTXSW); 148 DUMP_REG(DSI_RD_DATA); 149 DUMP_REG(DSI_WR_DATA); 150 DUMP_REG(DSI_POWER_CONTROL); 151 DUMP_REG(DSI_INT_ENABLE); 152 DUMP_REG(DSI_INT_STATUS); 153 DUMP_REG(DSI_INT_MASK); 154 DUMP_REG(DSI_HOST_CONTROL); 155 DUMP_REG(DSI_CONTROL); 156 DUMP_REG(DSI_SOL_DELAY); 157 DUMP_REG(DSI_MAX_THRESHOLD); 158 DUMP_REG(DSI_TRIGGER); 159 DUMP_REG(DSI_TX_CRC); 160 DUMP_REG(DSI_STATUS); 161 162 DUMP_REG(DSI_INIT_SEQ_CONTROL); 163 DUMP_REG(DSI_INIT_SEQ_DATA_0); 164 DUMP_REG(DSI_INIT_SEQ_DATA_1); 165 DUMP_REG(DSI_INIT_SEQ_DATA_2); 166 DUMP_REG(DSI_INIT_SEQ_DATA_3); 167 DUMP_REG(DSI_INIT_SEQ_DATA_4); 168 DUMP_REG(DSI_INIT_SEQ_DATA_5); 169 DUMP_REG(DSI_INIT_SEQ_DATA_6); 170 DUMP_REG(DSI_INIT_SEQ_DATA_7); 171 172 DUMP_REG(DSI_PKT_SEQ_0_LO); 173 DUMP_REG(DSI_PKT_SEQ_0_HI); 174 DUMP_REG(DSI_PKT_SEQ_1_LO); 175 DUMP_REG(DSI_PKT_SEQ_1_HI); 176 DUMP_REG(DSI_PKT_SEQ_2_LO); 177 DUMP_REG(DSI_PKT_SEQ_2_HI); 178 DUMP_REG(DSI_PKT_SEQ_3_LO); 179 DUMP_REG(DSI_PKT_SEQ_3_HI); 180 DUMP_REG(DSI_PKT_SEQ_4_LO); 181 DUMP_REG(DSI_PKT_SEQ_4_HI); 182 DUMP_REG(DSI_PKT_SEQ_5_LO); 183 DUMP_REG(DSI_PKT_SEQ_5_HI); 184 185 DUMP_REG(DSI_DCS_CMDS); 186 187 DUMP_REG(DSI_PKT_LEN_0_1); 188 DUMP_REG(DSI_PKT_LEN_2_3); 189 DUMP_REG(DSI_PKT_LEN_4_5); 190 DUMP_REG(DSI_PKT_LEN_6_7); 191 192 DUMP_REG(DSI_PHY_TIMING_0); 193 DUMP_REG(DSI_PHY_TIMING_1); 194 DUMP_REG(DSI_PHY_TIMING_2); 195 DUMP_REG(DSI_BTA_TIMING); 196 197 DUMP_REG(DSI_TIMEOUT_0); 198 DUMP_REG(DSI_TIMEOUT_1); 199 DUMP_REG(DSI_TO_TALLY); 200 201 DUMP_REG(DSI_PAD_CONTROL_0); 202 DUMP_REG(DSI_PAD_CONTROL_CD); 203 DUMP_REG(DSI_PAD_CD_STATUS); 204 DUMP_REG(DSI_VIDEO_MODE_CONTROL); 205 DUMP_REG(DSI_PAD_CONTROL_1); 206 DUMP_REG(DSI_PAD_CONTROL_2); 207 DUMP_REG(DSI_PAD_CONTROL_3); 208 DUMP_REG(DSI_PAD_CONTROL_4); 209 210 DUMP_REG(DSI_GANGED_MODE_CONTROL); 211 DUMP_REG(DSI_GANGED_MODE_START); 212 DUMP_REG(DSI_GANGED_MODE_SIZE); 213 214 DUMP_REG(DSI_RAW_DATA_BYTE_COUNT); 215 DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL); 216 217 DUMP_REG(DSI_INIT_SEQ_DATA_8); 218 DUMP_REG(DSI_INIT_SEQ_DATA_9); 219 DUMP_REG(DSI_INIT_SEQ_DATA_10); 220 DUMP_REG(DSI_INIT_SEQ_DATA_11); 221 DUMP_REG(DSI_INIT_SEQ_DATA_12); 222 DUMP_REG(DSI_INIT_SEQ_DATA_13); 223 DUMP_REG(DSI_INIT_SEQ_DATA_14); 224 DUMP_REG(DSI_INIT_SEQ_DATA_15); 225 226 #undef DUMP_REG 227 228 unlock: 229 drm_modeset_unlock_all(drm); 230 return err; 231 } 232 233 static struct drm_info_list debugfs_files[] = { 234 { "regs", tegra_dsi_show_regs, 0, NULL }, 235 }; 236 237 static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi, 238 struct drm_minor *minor) 239 { 240 const char *name = dev_name(dsi->dev); 241 unsigned int i; 242 int err; 243 244 dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root); 245 if (!dsi->debugfs) 246 return -ENOMEM; 247 248 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 249 GFP_KERNEL); 250 if (!dsi->debugfs_files) { 251 err = -ENOMEM; 252 goto remove; 253 } 254 255 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) 256 dsi->debugfs_files[i].data = dsi; 257 258 err = drm_debugfs_create_files(dsi->debugfs_files, 259 ARRAY_SIZE(debugfs_files), 260 dsi->debugfs, minor); 261 if (err < 0) 262 goto free; 263 264 dsi->minor = minor; 265 266 return 0; 267 268 free: 269 kfree(dsi->debugfs_files); 270 dsi->debugfs_files = NULL; 271 remove: 272 debugfs_remove(dsi->debugfs); 273 dsi->debugfs = NULL; 274 275 return err; 276 } 277 278 static void tegra_dsi_debugfs_exit(struct tegra_dsi *dsi) 279 { 280 drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files), 281 dsi->minor); 282 dsi->minor = NULL; 283 284 kfree(dsi->debugfs_files); 285 dsi->debugfs_files = NULL; 286 287 debugfs_remove(dsi->debugfs); 288 dsi->debugfs = NULL; 289 } 290 291 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9)) 292 #define PKT_LEN0(len) (((len) & 0x07) << 0) 293 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19)) 294 #define PKT_LEN1(len) (((len) & 0x07) << 10) 295 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29)) 296 #define PKT_LEN2(len) (((len) & 0x07) << 20) 297 298 #define PKT_LP (1 << 30) 299 #define NUM_PKT_SEQ 12 300 301 /* 302 * non-burst mode with sync pulses 303 */ 304 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = { 305 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 306 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 307 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 308 PKT_LP, 309 [ 1] = 0, 310 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) | 311 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 312 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 313 PKT_LP, 314 [ 3] = 0, 315 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 316 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 317 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 318 PKT_LP, 319 [ 5] = 0, 320 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 321 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 322 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), 323 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | 324 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | 325 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 326 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 327 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 328 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 329 PKT_LP, 330 [ 9] = 0, 331 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 332 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 333 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), 334 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | 335 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | 336 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 337 }; 338 339 /* 340 * non-burst mode with sync events 341 */ 342 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = { 343 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 344 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 345 PKT_LP, 346 [ 1] = 0, 347 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 348 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 349 PKT_LP, 350 [ 3] = 0, 351 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 352 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 353 PKT_LP, 354 [ 5] = 0, 355 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 356 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | 357 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), 358 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), 359 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 360 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 361 PKT_LP, 362 [ 9] = 0, 363 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 364 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | 365 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), 366 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), 367 }; 368 369 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = { 370 [ 0] = 0, 371 [ 1] = 0, 372 [ 2] = 0, 373 [ 3] = 0, 374 [ 4] = 0, 375 [ 5] = 0, 376 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP, 377 [ 7] = 0, 378 [ 8] = 0, 379 [ 9] = 0, 380 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP, 381 [11] = 0, 382 }; 383 384 static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi, 385 unsigned long period, 386 const struct mipi_dphy_timing *timing) 387 { 388 u32 value; 389 390 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 | 391 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 | 392 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 | 393 DSI_TIMING_FIELD(timing->hsprepare, period, 1); 394 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0); 395 396 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | 397 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 | 398 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 | 399 DSI_TIMING_FIELD(timing->lpx, period, 1); 400 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1); 401 402 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 | 403 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 | 404 DSI_TIMING_FIELD(0xff * period, period, 0) << 0; 405 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2); 406 407 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 | 408 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 | 409 DSI_TIMING_FIELD(timing->tago, period, 1); 410 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING); 411 412 if (dsi->slave) 413 tegra_dsi_set_phy_timing(dsi->slave, period, timing); 414 } 415 416 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format, 417 unsigned int *mulp, unsigned int *divp) 418 { 419 switch (format) { 420 case MIPI_DSI_FMT_RGB666_PACKED: 421 case MIPI_DSI_FMT_RGB888: 422 *mulp = 3; 423 *divp = 1; 424 break; 425 426 case MIPI_DSI_FMT_RGB565: 427 *mulp = 2; 428 *divp = 1; 429 break; 430 431 case MIPI_DSI_FMT_RGB666: 432 *mulp = 9; 433 *divp = 4; 434 break; 435 436 default: 437 return -EINVAL; 438 } 439 440 return 0; 441 } 442 443 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format, 444 enum tegra_dsi_format *fmt) 445 { 446 switch (format) { 447 case MIPI_DSI_FMT_RGB888: 448 *fmt = TEGRA_DSI_FORMAT_24P; 449 break; 450 451 case MIPI_DSI_FMT_RGB666: 452 *fmt = TEGRA_DSI_FORMAT_18NP; 453 break; 454 455 case MIPI_DSI_FMT_RGB666_PACKED: 456 *fmt = TEGRA_DSI_FORMAT_18P; 457 break; 458 459 case MIPI_DSI_FMT_RGB565: 460 *fmt = TEGRA_DSI_FORMAT_16P; 461 break; 462 463 default: 464 return -EINVAL; 465 } 466 467 return 0; 468 } 469 470 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start, 471 unsigned int size) 472 { 473 u32 value; 474 475 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START); 476 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE); 477 478 value = DSI_GANGED_MODE_CONTROL_ENABLE; 479 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL); 480 } 481 482 static void tegra_dsi_enable(struct tegra_dsi *dsi) 483 { 484 u32 value; 485 486 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 487 value |= DSI_POWER_CONTROL_ENABLE; 488 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 489 490 if (dsi->slave) 491 tegra_dsi_enable(dsi->slave); 492 } 493 494 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi) 495 { 496 if (dsi->master) 497 return dsi->master->lanes + dsi->lanes; 498 499 if (dsi->slave) 500 return dsi->lanes + dsi->slave->lanes; 501 502 return dsi->lanes; 503 } 504 505 static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe, 506 const struct drm_display_mode *mode) 507 { 508 unsigned int hact, hsw, hbp, hfp, i, mul, div; 509 struct tegra_dsi_state *state; 510 const u32 *pkt_seq; 511 u32 value; 512 513 /* XXX: pass in state into this function? */ 514 if (dsi->master) 515 state = tegra_dsi_get_state(dsi->master); 516 else 517 state = tegra_dsi_get_state(dsi); 518 519 mul = state->mul; 520 div = state->div; 521 522 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 523 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n"); 524 pkt_seq = pkt_seq_video_non_burst_sync_pulses; 525 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) { 526 DRM_DEBUG_KMS("Non-burst video mode with sync events\n"); 527 pkt_seq = pkt_seq_video_non_burst_sync_events; 528 } else { 529 DRM_DEBUG_KMS("Command mode\n"); 530 pkt_seq = pkt_seq_command_mode; 531 } 532 533 value = DSI_CONTROL_CHANNEL(0) | 534 DSI_CONTROL_FORMAT(state->format) | 535 DSI_CONTROL_LANES(dsi->lanes - 1) | 536 DSI_CONTROL_SOURCE(pipe); 537 tegra_dsi_writel(dsi, value, DSI_CONTROL); 538 539 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD); 540 541 value = DSI_HOST_CONTROL_HS; 542 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 543 544 value = tegra_dsi_readl(dsi, DSI_CONTROL); 545 546 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 547 value |= DSI_CONTROL_HS_CLK_CTRL; 548 549 value &= ~DSI_CONTROL_TX_TRIG(3); 550 551 /* enable DCS commands for command mode */ 552 if (dsi->flags & MIPI_DSI_MODE_VIDEO) 553 value &= ~DSI_CONTROL_DCS_ENABLE; 554 else 555 value |= DSI_CONTROL_DCS_ENABLE; 556 557 value |= DSI_CONTROL_VIDEO_ENABLE; 558 value &= ~DSI_CONTROL_HOST_ENABLE; 559 tegra_dsi_writel(dsi, value, DSI_CONTROL); 560 561 for (i = 0; i < NUM_PKT_SEQ; i++) 562 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i); 563 564 if (dsi->flags & MIPI_DSI_MODE_VIDEO) { 565 /* horizontal active pixels */ 566 hact = mode->hdisplay * mul / div; 567 568 /* horizontal sync width */ 569 hsw = (mode->hsync_end - mode->hsync_start) * mul / div; 570 571 /* horizontal back porch */ 572 hbp = (mode->htotal - mode->hsync_end) * mul / div; 573 574 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0) 575 hbp += hsw; 576 577 /* horizontal front porch */ 578 hfp = (mode->hsync_start - mode->hdisplay) * mul / div; 579 580 /* subtract packet overhead */ 581 hsw -= 10; 582 hbp -= 14; 583 hfp -= 8; 584 585 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1); 586 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3); 587 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5); 588 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7); 589 590 /* set SOL delay (for non-burst mode only) */ 591 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); 592 593 /* TODO: implement ganged mode */ 594 } else { 595 u16 bytes; 596 597 if (dsi->master || dsi->slave) { 598 /* 599 * For ganged mode, assume symmetric left-right mode. 600 */ 601 bytes = 1 + (mode->hdisplay / 2) * mul / div; 602 } else { 603 /* 1 byte (DCS command) + pixel data */ 604 bytes = 1 + mode->hdisplay * mul / div; 605 } 606 607 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1); 608 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3); 609 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5); 610 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7); 611 612 value = MIPI_DCS_WRITE_MEMORY_START << 8 | 613 MIPI_DCS_WRITE_MEMORY_CONTINUE; 614 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS); 615 616 /* set SOL delay */ 617 if (dsi->master || dsi->slave) { 618 unsigned long delay, bclk, bclk_ganged; 619 unsigned int lanes = state->lanes; 620 621 /* SOL to valid, valid to FIFO and FIFO write delay */ 622 delay = 4 + 4 + 2; 623 delay = DIV_ROUND_UP(delay * mul, div * lanes); 624 /* FIFO read delay */ 625 delay = delay + 6; 626 627 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); 628 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); 629 value = bclk - bclk_ganged + delay + 20; 630 } else { 631 /* TODO: revisit for non-ganged mode */ 632 value = 8 * mul / div; 633 } 634 635 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY); 636 } 637 638 if (dsi->slave) { 639 tegra_dsi_configure(dsi->slave, pipe, mode); 640 641 /* 642 * TODO: Support modes other than symmetrical left-right 643 * split. 644 */ 645 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2); 646 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2, 647 mode->hdisplay / 2); 648 } 649 } 650 651 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout) 652 { 653 u32 value; 654 655 timeout = jiffies + msecs_to_jiffies(timeout); 656 657 while (time_before(jiffies, timeout)) { 658 value = tegra_dsi_readl(dsi, DSI_STATUS); 659 if (value & DSI_STATUS_IDLE) 660 return 0; 661 662 usleep_range(1000, 2000); 663 } 664 665 return -ETIMEDOUT; 666 } 667 668 static void tegra_dsi_video_disable(struct tegra_dsi *dsi) 669 { 670 u32 value; 671 672 value = tegra_dsi_readl(dsi, DSI_CONTROL); 673 value &= ~DSI_CONTROL_VIDEO_ENABLE; 674 tegra_dsi_writel(dsi, value, DSI_CONTROL); 675 676 if (dsi->slave) 677 tegra_dsi_video_disable(dsi->slave); 678 } 679 680 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi) 681 { 682 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START); 683 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE); 684 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL); 685 } 686 687 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) 688 { 689 u32 value; 690 691 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); 692 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); 693 694 return 0; 695 } 696 697 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) 698 { 699 u32 value; 700 701 /* 702 * XXX Is this still needed? The module reset is deasserted right 703 * before this function is called. 704 */ 705 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); 706 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); 707 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); 708 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); 709 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); 710 711 /* start calibration */ 712 tegra_dsi_pad_enable(dsi); 713 714 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | 715 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | 716 DSI_PAD_OUT_CLK(0x0); 717 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); 718 719 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | 720 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); 721 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); 722 723 return tegra_mipi_calibrate(dsi->mipi); 724 } 725 726 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, 727 unsigned int vrefresh) 728 { 729 unsigned int timeout; 730 u32 value; 731 732 /* one frame high-speed transmission timeout */ 733 timeout = (bclk / vrefresh) / 512; 734 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout); 735 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); 736 737 /* 2 ms peripheral timeout for panel */ 738 timeout = 2 * bclk / 512 * 1000; 739 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000); 740 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); 741 742 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0); 743 tegra_dsi_writel(dsi, value, DSI_TO_TALLY); 744 745 if (dsi->slave) 746 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh); 747 } 748 749 static void tegra_dsi_disable(struct tegra_dsi *dsi) 750 { 751 u32 value; 752 753 if (dsi->slave) { 754 tegra_dsi_ganged_disable(dsi->slave); 755 tegra_dsi_ganged_disable(dsi); 756 } 757 758 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 759 value &= ~DSI_POWER_CONTROL_ENABLE; 760 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 761 762 if (dsi->slave) 763 tegra_dsi_disable(dsi->slave); 764 765 usleep_range(5000, 10000); 766 } 767 768 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi) 769 { 770 u32 value; 771 772 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 773 value &= ~DSI_POWER_CONTROL_ENABLE; 774 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 775 776 usleep_range(300, 1000); 777 778 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 779 value |= DSI_POWER_CONTROL_ENABLE; 780 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 781 782 usleep_range(300, 1000); 783 784 value = tegra_dsi_readl(dsi, DSI_TRIGGER); 785 if (value) 786 tegra_dsi_writel(dsi, 0, DSI_TRIGGER); 787 788 if (dsi->slave) 789 tegra_dsi_soft_reset(dsi->slave); 790 } 791 792 static void tegra_dsi_connector_reset(struct drm_connector *connector) 793 { 794 struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 795 796 if (!state) 797 return; 798 799 if (connector->state) { 800 __drm_atomic_helper_connector_destroy_state(connector->state); 801 kfree(connector->state); 802 } 803 804 __drm_atomic_helper_connector_reset(connector, &state->base); 805 } 806 807 static struct drm_connector_state * 808 tegra_dsi_connector_duplicate_state(struct drm_connector *connector) 809 { 810 struct tegra_dsi_state *state = to_dsi_state(connector->state); 811 struct tegra_dsi_state *copy; 812 813 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 814 if (!copy) 815 return NULL; 816 817 __drm_atomic_helper_connector_duplicate_state(connector, 818 ©->base); 819 820 return ©->base; 821 } 822 823 static const struct drm_connector_funcs tegra_dsi_connector_funcs = { 824 .dpms = drm_atomic_helper_connector_dpms, 825 .reset = tegra_dsi_connector_reset, 826 .detect = tegra_output_connector_detect, 827 .fill_modes = drm_helper_probe_single_connector_modes, 828 .destroy = tegra_output_connector_destroy, 829 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state, 830 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 831 }; 832 833 static enum drm_mode_status 834 tegra_dsi_connector_mode_valid(struct drm_connector *connector, 835 struct drm_display_mode *mode) 836 { 837 return MODE_OK; 838 } 839 840 static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = { 841 .get_modes = tegra_output_connector_get_modes, 842 .mode_valid = tegra_dsi_connector_mode_valid, 843 }; 844 845 static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = { 846 .destroy = tegra_output_encoder_destroy, 847 }; 848 849 static void tegra_dsi_unprepare(struct tegra_dsi *dsi) 850 { 851 int err; 852 853 if (dsi->slave) 854 tegra_dsi_unprepare(dsi->slave); 855 856 err = tegra_mipi_disable(dsi->mipi); 857 if (err < 0) 858 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n", 859 err); 860 861 pm_runtime_put(dsi->dev); 862 } 863 864 static void tegra_dsi_encoder_disable(struct drm_encoder *encoder) 865 { 866 struct tegra_output *output = encoder_to_output(encoder); 867 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 868 struct tegra_dsi *dsi = to_dsi(output); 869 u32 value; 870 int err; 871 872 if (output->panel) 873 drm_panel_disable(output->panel); 874 875 tegra_dsi_video_disable(dsi); 876 877 /* 878 * The following accesses registers of the display controller, so make 879 * sure it's only executed when the output is attached to one. 880 */ 881 if (dc) { 882 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 883 value &= ~DSI_ENABLE; 884 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 885 886 tegra_dc_commit(dc); 887 } 888 889 err = tegra_dsi_wait_idle(dsi, 100); 890 if (err < 0) 891 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err); 892 893 tegra_dsi_soft_reset(dsi); 894 895 if (output->panel) 896 drm_panel_unprepare(output->panel); 897 898 tegra_dsi_disable(dsi); 899 900 tegra_dsi_unprepare(dsi); 901 } 902 903 static void tegra_dsi_prepare(struct tegra_dsi *dsi) 904 { 905 int err; 906 907 pm_runtime_get_sync(dsi->dev); 908 909 err = tegra_mipi_enable(dsi->mipi); 910 if (err < 0) 911 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n", 912 err); 913 914 err = tegra_dsi_pad_calibrate(dsi); 915 if (err < 0) 916 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err); 917 918 if (dsi->slave) 919 tegra_dsi_prepare(dsi->slave); 920 } 921 922 static void tegra_dsi_encoder_enable(struct drm_encoder *encoder) 923 { 924 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 925 struct tegra_output *output = encoder_to_output(encoder); 926 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 927 struct tegra_dsi *dsi = to_dsi(output); 928 struct tegra_dsi_state *state; 929 u32 value; 930 931 tegra_dsi_prepare(dsi); 932 933 state = tegra_dsi_get_state(dsi); 934 935 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh); 936 937 /* 938 * The D-PHY timing fields are expressed in byte-clock cycles, so 939 * multiply the period by 8. 940 */ 941 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing); 942 943 if (output->panel) 944 drm_panel_prepare(output->panel); 945 946 tegra_dsi_configure(dsi, dc->pipe, mode); 947 948 /* enable display controller */ 949 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 950 value |= DSI_ENABLE; 951 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 952 953 tegra_dc_commit(dc); 954 955 /* enable DSI controller */ 956 tegra_dsi_enable(dsi); 957 958 if (output->panel) 959 drm_panel_enable(output->panel); 960 } 961 962 static int 963 tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder, 964 struct drm_crtc_state *crtc_state, 965 struct drm_connector_state *conn_state) 966 { 967 struct tegra_output *output = encoder_to_output(encoder); 968 struct tegra_dsi_state *state = to_dsi_state(conn_state); 969 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 970 struct tegra_dsi *dsi = to_dsi(output); 971 unsigned int scdiv; 972 unsigned long plld; 973 int err; 974 975 state->pclk = crtc_state->mode.clock * 1000; 976 977 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div); 978 if (err < 0) 979 return err; 980 981 state->lanes = tegra_dsi_get_lanes(dsi); 982 983 err = tegra_dsi_get_format(dsi->format, &state->format); 984 if (err < 0) 985 return err; 986 987 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode); 988 989 /* compute byte clock */ 990 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes); 991 992 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div, 993 state->lanes); 994 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format, 995 state->vrefresh); 996 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk); 997 998 /* 999 * Compute bit clock and round up to the next MHz. 1000 */ 1001 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC; 1002 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld); 1003 1004 err = mipi_dphy_timing_get_default(&state->timing, state->period); 1005 if (err < 0) 1006 return err; 1007 1008 err = mipi_dphy_timing_validate(&state->timing, state->period); 1009 if (err < 0) { 1010 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err); 1011 return err; 1012 } 1013 1014 /* 1015 * We divide the frequency by two here, but we make up for that by 1016 * setting the shift clock divider (further below) to half of the 1017 * correct value. 1018 */ 1019 plld /= 2; 1020 1021 /* 1022 * Derive pixel clock from bit clock using the shift clock divider. 1023 * Note that this is only half of what we would expect, but we need 1024 * that to make up for the fact that we divided the bit clock by a 1025 * factor of two above. 1026 * 1027 * It's not clear exactly why this is necessary, but the display is 1028 * not working properly otherwise. Perhaps the PLLs cannot generate 1029 * frequencies sufficiently high. 1030 */ 1031 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2; 1032 1033 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent, 1034 plld, scdiv); 1035 if (err < 0) { 1036 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 1037 return err; 1038 } 1039 1040 return err; 1041 } 1042 1043 static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = { 1044 .disable = tegra_dsi_encoder_disable, 1045 .enable = tegra_dsi_encoder_enable, 1046 .atomic_check = tegra_dsi_encoder_atomic_check, 1047 }; 1048 1049 static int tegra_dsi_init(struct host1x_client *client) 1050 { 1051 struct drm_device *drm = dev_get_drvdata(client->parent); 1052 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1053 int err; 1054 1055 /* Gangsters must not register their own outputs. */ 1056 if (!dsi->master) { 1057 dsi->output.dev = client->dev; 1058 1059 drm_connector_init(drm, &dsi->output.connector, 1060 &tegra_dsi_connector_funcs, 1061 DRM_MODE_CONNECTOR_DSI); 1062 drm_connector_helper_add(&dsi->output.connector, 1063 &tegra_dsi_connector_helper_funcs); 1064 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF; 1065 1066 drm_encoder_init(drm, &dsi->output.encoder, 1067 &tegra_dsi_encoder_funcs, 1068 DRM_MODE_ENCODER_DSI, NULL); 1069 drm_encoder_helper_add(&dsi->output.encoder, 1070 &tegra_dsi_encoder_helper_funcs); 1071 1072 drm_mode_connector_attach_encoder(&dsi->output.connector, 1073 &dsi->output.encoder); 1074 drm_connector_register(&dsi->output.connector); 1075 1076 err = tegra_output_init(drm, &dsi->output); 1077 if (err < 0) 1078 dev_err(dsi->dev, "failed to initialize output: %d\n", 1079 err); 1080 1081 dsi->output.encoder.possible_crtcs = 0x3; 1082 } 1083 1084 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1085 err = tegra_dsi_debugfs_init(dsi, drm->primary); 1086 if (err < 0) 1087 dev_err(dsi->dev, "debugfs setup failed: %d\n", err); 1088 } 1089 1090 return 0; 1091 } 1092 1093 static int tegra_dsi_exit(struct host1x_client *client) 1094 { 1095 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1096 1097 tegra_output_exit(&dsi->output); 1098 1099 if (IS_ENABLED(CONFIG_DEBUG_FS)) 1100 tegra_dsi_debugfs_exit(dsi); 1101 1102 regulator_disable(dsi->vdd); 1103 1104 return 0; 1105 } 1106 1107 static const struct host1x_client_ops dsi_client_ops = { 1108 .init = tegra_dsi_init, 1109 .exit = tegra_dsi_exit, 1110 }; 1111 1112 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi) 1113 { 1114 struct clk *parent; 1115 int err; 1116 1117 parent = clk_get_parent(dsi->clk); 1118 if (!parent) 1119 return -EINVAL; 1120 1121 err = clk_set_parent(parent, dsi->clk_parent); 1122 if (err < 0) 1123 return err; 1124 1125 return 0; 1126 } 1127 1128 static const char * const error_report[16] = { 1129 "SoT Error", 1130 "SoT Sync Error", 1131 "EoT Sync Error", 1132 "Escape Mode Entry Command Error", 1133 "Low-Power Transmit Sync Error", 1134 "Peripheral Timeout Error", 1135 "False Control Error", 1136 "Contention Detected", 1137 "ECC Error, single-bit", 1138 "ECC Error, multi-bit", 1139 "Checksum Error", 1140 "DSI Data Type Not Recognized", 1141 "DSI VC ID Invalid", 1142 "Invalid Transmission Length", 1143 "Reserved", 1144 "DSI Protocol Violation", 1145 }; 1146 1147 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi, 1148 const struct mipi_dsi_msg *msg, 1149 size_t count) 1150 { 1151 u8 *rx = msg->rx_buf; 1152 unsigned int i, j, k; 1153 size_t size = 0; 1154 u16 errors; 1155 u32 value; 1156 1157 /* read and parse packet header */ 1158 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1159 1160 switch (value & 0x3f) { 1161 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1162 errors = (value >> 8) & 0xffff; 1163 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n", 1164 errors); 1165 for (i = 0; i < ARRAY_SIZE(error_report); i++) 1166 if (errors & BIT(i)) 1167 dev_dbg(dsi->dev, " %2u: %s\n", i, 1168 error_report[i]); 1169 break; 1170 1171 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1172 rx[0] = (value >> 8) & 0xff; 1173 size = 1; 1174 break; 1175 1176 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1177 rx[0] = (value >> 8) & 0xff; 1178 rx[1] = (value >> 16) & 0xff; 1179 size = 2; 1180 break; 1181 1182 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 1183 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); 1184 break; 1185 1186 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 1187 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); 1188 break; 1189 1190 default: 1191 dev_err(dsi->dev, "unhandled response type: %02x\n", 1192 value & 0x3f); 1193 return -EPROTO; 1194 } 1195 1196 size = min(size, msg->rx_len); 1197 1198 if (msg->rx_buf && size > 0) { 1199 for (i = 0, j = 0; i < count - 1; i++, j += 4) { 1200 u8 *rx = msg->rx_buf + j; 1201 1202 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1203 1204 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++) 1205 rx[j + k] = (value >> (k << 3)) & 0xff; 1206 } 1207 } 1208 1209 return size; 1210 } 1211 1212 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout) 1213 { 1214 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER); 1215 1216 timeout = jiffies + msecs_to_jiffies(timeout); 1217 1218 while (time_before(jiffies, timeout)) { 1219 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER); 1220 if ((value & DSI_TRIGGER_HOST) == 0) 1221 return 0; 1222 1223 usleep_range(1000, 2000); 1224 } 1225 1226 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n"); 1227 return -ETIMEDOUT; 1228 } 1229 1230 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi, 1231 unsigned long timeout) 1232 { 1233 timeout = jiffies + msecs_to_jiffies(250); 1234 1235 while (time_before(jiffies, timeout)) { 1236 u32 value = tegra_dsi_readl(dsi, DSI_STATUS); 1237 u8 count = value & 0x1f; 1238 1239 if (count > 0) 1240 return count; 1241 1242 usleep_range(1000, 2000); 1243 } 1244 1245 DRM_DEBUG_KMS("peripheral returned no data\n"); 1246 return -ETIMEDOUT; 1247 } 1248 1249 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset, 1250 const void *buffer, size_t size) 1251 { 1252 const u8 *buf = buffer; 1253 size_t i, j; 1254 u32 value; 1255 1256 for (j = 0; j < size; j += 4) { 1257 value = 0; 1258 1259 for (i = 0; i < 4 && j + i < size; i++) 1260 value |= buf[j + i] << (i << 3); 1261 1262 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 1263 } 1264 } 1265 1266 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host, 1267 const struct mipi_dsi_msg *msg) 1268 { 1269 struct tegra_dsi *dsi = host_to_tegra(host); 1270 struct mipi_dsi_packet packet; 1271 const u8 *header; 1272 size_t count; 1273 ssize_t err; 1274 u32 value; 1275 1276 err = mipi_dsi_create_packet(&packet, msg); 1277 if (err < 0) 1278 return err; 1279 1280 header = packet.header; 1281 1282 /* maximum FIFO depth is 1920 words */ 1283 if (packet.size > dsi->video_fifo_depth * 4) 1284 return -ENOSPC; 1285 1286 /* reset underflow/overflow flags */ 1287 value = tegra_dsi_readl(dsi, DSI_STATUS); 1288 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) { 1289 value = DSI_HOST_CONTROL_FIFO_RESET; 1290 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1291 usleep_range(10, 20); 1292 } 1293 1294 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 1295 value |= DSI_POWER_CONTROL_ENABLE; 1296 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 1297 1298 usleep_range(5000, 10000); 1299 1300 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | 1301 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC; 1302 1303 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0) 1304 value |= DSI_HOST_CONTROL_HS; 1305 1306 /* 1307 * The host FIFO has a maximum of 64 words, so larger transmissions 1308 * need to use the video FIFO. 1309 */ 1310 if (packet.size > dsi->host_fifo_depth * 4) 1311 value |= DSI_HOST_CONTROL_FIFO_SEL; 1312 1313 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1314 1315 /* 1316 * For reads and messages with explicitly requested ACK, generate a 1317 * BTA sequence after the transmission of the packet. 1318 */ 1319 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || 1320 (msg->rx_buf && msg->rx_len > 0)) { 1321 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); 1322 value |= DSI_HOST_CONTROL_PKT_BTA; 1323 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1324 } 1325 1326 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE; 1327 tegra_dsi_writel(dsi, value, DSI_CONTROL); 1328 1329 /* write packet header, ECC is generated by hardware */ 1330 value = header[2] << 16 | header[1] << 8 | header[0]; 1331 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 1332 1333 /* write payload (if any) */ 1334 if (packet.payload_length > 0) 1335 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload, 1336 packet.payload_length); 1337 1338 err = tegra_dsi_transmit(dsi, 250); 1339 if (err < 0) 1340 return err; 1341 1342 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || 1343 (msg->rx_buf && msg->rx_len > 0)) { 1344 err = tegra_dsi_wait_for_response(dsi, 250); 1345 if (err < 0) 1346 return err; 1347 1348 count = err; 1349 1350 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1351 switch (value) { 1352 case 0x84: 1353 /* 1354 dev_dbg(dsi->dev, "ACK\n"); 1355 */ 1356 break; 1357 1358 case 0x87: 1359 /* 1360 dev_dbg(dsi->dev, "ESCAPE\n"); 1361 */ 1362 break; 1363 1364 default: 1365 dev_err(dsi->dev, "unknown status: %08x\n", value); 1366 break; 1367 } 1368 1369 if (count > 1) { 1370 err = tegra_dsi_read_response(dsi, msg, count); 1371 if (err < 0) 1372 dev_err(dsi->dev, 1373 "failed to parse response: %zd\n", 1374 err); 1375 else { 1376 /* 1377 * For read commands, return the number of 1378 * bytes returned by the peripheral. 1379 */ 1380 count = err; 1381 } 1382 } 1383 } else { 1384 /* 1385 * For write commands, we have transmitted the 4-byte header 1386 * plus the variable-length payload. 1387 */ 1388 count = 4 + packet.payload_length; 1389 } 1390 1391 return count; 1392 } 1393 1394 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi) 1395 { 1396 struct clk *parent; 1397 int err; 1398 1399 /* make sure both DSI controllers share the same PLL */ 1400 parent = clk_get_parent(dsi->slave->clk); 1401 if (!parent) 1402 return -EINVAL; 1403 1404 err = clk_set_parent(parent, dsi->clk_parent); 1405 if (err < 0) 1406 return err; 1407 1408 return 0; 1409 } 1410 1411 static int tegra_dsi_host_attach(struct mipi_dsi_host *host, 1412 struct mipi_dsi_device *device) 1413 { 1414 struct tegra_dsi *dsi = host_to_tegra(host); 1415 1416 dsi->flags = device->mode_flags; 1417 dsi->format = device->format; 1418 dsi->lanes = device->lanes; 1419 1420 if (dsi->slave) { 1421 int err; 1422 1423 dev_dbg(dsi->dev, "attaching dual-channel device %s\n", 1424 dev_name(&device->dev)); 1425 1426 err = tegra_dsi_ganged_setup(dsi); 1427 if (err < 0) { 1428 dev_err(dsi->dev, "failed to set up ganged mode: %d\n", 1429 err); 1430 return err; 1431 } 1432 } 1433 1434 /* 1435 * Slaves don't have a panel associated with them, so they provide 1436 * merely the second channel. 1437 */ 1438 if (!dsi->master) { 1439 struct tegra_output *output = &dsi->output; 1440 1441 output->panel = of_drm_find_panel(device->dev.of_node); 1442 if (output->panel && output->connector.dev) { 1443 drm_panel_attach(output->panel, &output->connector); 1444 drm_helper_hpd_irq_event(output->connector.dev); 1445 } 1446 } 1447 1448 return 0; 1449 } 1450 1451 static int tegra_dsi_host_detach(struct mipi_dsi_host *host, 1452 struct mipi_dsi_device *device) 1453 { 1454 struct tegra_dsi *dsi = host_to_tegra(host); 1455 struct tegra_output *output = &dsi->output; 1456 1457 if (output->panel && &device->dev == output->panel->dev) { 1458 output->panel = NULL; 1459 1460 if (output->connector.dev) 1461 drm_helper_hpd_irq_event(output->connector.dev); 1462 } 1463 1464 return 0; 1465 } 1466 1467 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = { 1468 .attach = tegra_dsi_host_attach, 1469 .detach = tegra_dsi_host_detach, 1470 .transfer = tegra_dsi_host_transfer, 1471 }; 1472 1473 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi) 1474 { 1475 struct device_node *np; 1476 1477 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0); 1478 if (np) { 1479 struct platform_device *gangster = of_find_device_by_node(np); 1480 1481 dsi->slave = platform_get_drvdata(gangster); 1482 of_node_put(np); 1483 1484 if (!dsi->slave) 1485 return -EPROBE_DEFER; 1486 1487 dsi->slave->master = dsi; 1488 } 1489 1490 return 0; 1491 } 1492 1493 static int tegra_dsi_probe(struct platform_device *pdev) 1494 { 1495 struct tegra_dsi *dsi; 1496 struct resource *regs; 1497 int err; 1498 1499 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); 1500 if (!dsi) 1501 return -ENOMEM; 1502 1503 dsi->output.dev = dsi->dev = &pdev->dev; 1504 dsi->video_fifo_depth = 1920; 1505 dsi->host_fifo_depth = 64; 1506 1507 err = tegra_dsi_ganged_probe(dsi); 1508 if (err < 0) 1509 return err; 1510 1511 err = tegra_output_probe(&dsi->output); 1512 if (err < 0) 1513 return err; 1514 1515 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD; 1516 1517 /* 1518 * Assume these values by default. When a DSI peripheral driver 1519 * attaches to the DSI host, the parameters will be taken from 1520 * the attached device. 1521 */ 1522 dsi->flags = MIPI_DSI_MODE_VIDEO; 1523 dsi->format = MIPI_DSI_FMT_RGB888; 1524 dsi->lanes = 4; 1525 1526 if (!pdev->dev.pm_domain) { 1527 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi"); 1528 if (IS_ERR(dsi->rst)) 1529 return PTR_ERR(dsi->rst); 1530 } 1531 1532 dsi->clk = devm_clk_get(&pdev->dev, NULL); 1533 if (IS_ERR(dsi->clk)) { 1534 dev_err(&pdev->dev, "cannot get DSI clock\n"); 1535 return PTR_ERR(dsi->clk); 1536 } 1537 1538 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp"); 1539 if (IS_ERR(dsi->clk_lp)) { 1540 dev_err(&pdev->dev, "cannot get low-power clock\n"); 1541 return PTR_ERR(dsi->clk_lp); 1542 } 1543 1544 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent"); 1545 if (IS_ERR(dsi->clk_parent)) { 1546 dev_err(&pdev->dev, "cannot get parent clock\n"); 1547 return PTR_ERR(dsi->clk_parent); 1548 } 1549 1550 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi"); 1551 if (IS_ERR(dsi->vdd)) { 1552 dev_err(&pdev->dev, "cannot get VDD supply\n"); 1553 return PTR_ERR(dsi->vdd); 1554 } 1555 1556 err = tegra_dsi_setup_clocks(dsi); 1557 if (err < 0) { 1558 dev_err(&pdev->dev, "cannot setup clocks\n"); 1559 return err; 1560 } 1561 1562 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1563 dsi->regs = devm_ioremap_resource(&pdev->dev, regs); 1564 if (IS_ERR(dsi->regs)) 1565 return PTR_ERR(dsi->regs); 1566 1567 dsi->mipi = tegra_mipi_request(&pdev->dev); 1568 if (IS_ERR(dsi->mipi)) 1569 return PTR_ERR(dsi->mipi); 1570 1571 dsi->host.ops = &tegra_dsi_host_ops; 1572 dsi->host.dev = &pdev->dev; 1573 1574 err = mipi_dsi_host_register(&dsi->host); 1575 if (err < 0) { 1576 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err); 1577 goto mipi_free; 1578 } 1579 1580 platform_set_drvdata(pdev, dsi); 1581 pm_runtime_enable(&pdev->dev); 1582 1583 INIT_LIST_HEAD(&dsi->client.list); 1584 dsi->client.ops = &dsi_client_ops; 1585 dsi->client.dev = &pdev->dev; 1586 1587 err = host1x_client_register(&dsi->client); 1588 if (err < 0) { 1589 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1590 err); 1591 goto unregister; 1592 } 1593 1594 return 0; 1595 1596 unregister: 1597 mipi_dsi_host_unregister(&dsi->host); 1598 mipi_free: 1599 tegra_mipi_free(dsi->mipi); 1600 return err; 1601 } 1602 1603 static int tegra_dsi_remove(struct platform_device *pdev) 1604 { 1605 struct tegra_dsi *dsi = platform_get_drvdata(pdev); 1606 int err; 1607 1608 pm_runtime_disable(&pdev->dev); 1609 1610 err = host1x_client_unregister(&dsi->client); 1611 if (err < 0) { 1612 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 1613 err); 1614 return err; 1615 } 1616 1617 tegra_output_remove(&dsi->output); 1618 1619 mipi_dsi_host_unregister(&dsi->host); 1620 tegra_mipi_free(dsi->mipi); 1621 1622 return 0; 1623 } 1624 1625 #ifdef CONFIG_PM 1626 static int tegra_dsi_suspend(struct device *dev) 1627 { 1628 struct tegra_dsi *dsi = dev_get_drvdata(dev); 1629 int err; 1630 1631 if (dsi->rst) { 1632 err = reset_control_assert(dsi->rst); 1633 if (err < 0) { 1634 dev_err(dev, "failed to assert reset: %d\n", err); 1635 return err; 1636 } 1637 } 1638 1639 usleep_range(1000, 2000); 1640 1641 clk_disable_unprepare(dsi->clk_lp); 1642 clk_disable_unprepare(dsi->clk); 1643 1644 regulator_disable(dsi->vdd); 1645 1646 return 0; 1647 } 1648 1649 static int tegra_dsi_resume(struct device *dev) 1650 { 1651 struct tegra_dsi *dsi = dev_get_drvdata(dev); 1652 int err; 1653 1654 err = regulator_enable(dsi->vdd); 1655 if (err < 0) { 1656 dev_err(dsi->dev, "failed to enable VDD supply: %d\n", err); 1657 return err; 1658 } 1659 1660 err = clk_prepare_enable(dsi->clk); 1661 if (err < 0) { 1662 dev_err(dev, "cannot enable DSI clock: %d\n", err); 1663 goto disable_vdd; 1664 } 1665 1666 err = clk_prepare_enable(dsi->clk_lp); 1667 if (err < 0) { 1668 dev_err(dev, "cannot enable low-power clock: %d\n", err); 1669 goto disable_clk; 1670 } 1671 1672 usleep_range(1000, 2000); 1673 1674 if (dsi->rst) { 1675 err = reset_control_deassert(dsi->rst); 1676 if (err < 0) { 1677 dev_err(dev, "cannot assert reset: %d\n", err); 1678 goto disable_clk_lp; 1679 } 1680 } 1681 1682 return 0; 1683 1684 disable_clk_lp: 1685 clk_disable_unprepare(dsi->clk_lp); 1686 disable_clk: 1687 clk_disable_unprepare(dsi->clk); 1688 disable_vdd: 1689 regulator_disable(dsi->vdd); 1690 return err; 1691 } 1692 #endif 1693 1694 static const struct dev_pm_ops tegra_dsi_pm_ops = { 1695 SET_RUNTIME_PM_OPS(tegra_dsi_suspend, tegra_dsi_resume, NULL) 1696 }; 1697 1698 static const struct of_device_id tegra_dsi_of_match[] = { 1699 { .compatible = "nvidia,tegra210-dsi", }, 1700 { .compatible = "nvidia,tegra132-dsi", }, 1701 { .compatible = "nvidia,tegra124-dsi", }, 1702 { .compatible = "nvidia,tegra114-dsi", }, 1703 { }, 1704 }; 1705 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match); 1706 1707 struct platform_driver tegra_dsi_driver = { 1708 .driver = { 1709 .name = "tegra-dsi", 1710 .of_match_table = tegra_dsi_of_match, 1711 .pm = &tegra_dsi_pm_ops, 1712 }, 1713 .probe = tegra_dsi_probe, 1714 .remove = tegra_dsi_remove, 1715 }; 1716