1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Avionic Design GmbH 4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/debugfs.h> 9 #include <linux/delay.h> 10 #include <linux/iommu.h> 11 #include <linux/interconnect.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/reset.h> 16 17 #include <soc/tegra/pmc.h> 18 19 #include <drm/drm_atomic.h> 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_debugfs.h> 22 #include <drm/drm_fourcc.h> 23 #include <drm/drm_plane_helper.h> 24 #include <drm/drm_vblank.h> 25 26 #include "dc.h" 27 #include "drm.h" 28 #include "gem.h" 29 #include "hub.h" 30 #include "plane.h" 31 32 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, 33 struct drm_crtc_state *state); 34 35 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats) 36 { 37 stats->frames = 0; 38 stats->vblank = 0; 39 stats->underflow = 0; 40 stats->overflow = 0; 41 } 42 43 /* Reads the active copy of a register. */ 44 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) 45 { 46 u32 value; 47 48 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 49 value = tegra_dc_readl(dc, offset); 50 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); 51 52 return value; 53 } 54 55 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane, 56 unsigned int offset) 57 { 58 if (offset >= 0x500 && offset <= 0x638) { 59 offset = 0x000 + (offset - 0x500); 60 return plane->offset + offset; 61 } 62 63 if (offset >= 0x700 && offset <= 0x719) { 64 offset = 0x180 + (offset - 0x700); 65 return plane->offset + offset; 66 } 67 68 if (offset >= 0x800 && offset <= 0x839) { 69 offset = 0x1c0 + (offset - 0x800); 70 return plane->offset + offset; 71 } 72 73 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); 74 75 return plane->offset + offset; 76 } 77 78 static inline u32 tegra_plane_readl(struct tegra_plane *plane, 79 unsigned int offset) 80 { 81 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); 82 } 83 84 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value, 85 unsigned int offset) 86 { 87 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); 88 } 89 90 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) 91 { 92 struct device_node *np = dc->dev->of_node; 93 struct of_phandle_iterator it; 94 int err; 95 96 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0) 97 if (it.node == dev->of_node) 98 return true; 99 100 return false; 101 } 102 103 /* 104 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the 105 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy. 106 * Latching happens mmediately if the display controller is in STOP mode or 107 * on the next frame boundary otherwise. 108 * 109 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The 110 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits 111 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched 112 * into the ACTIVE copy, either immediately if the display controller is in 113 * STOP mode, or at the next frame boundary otherwise. 114 */ 115 void tegra_dc_commit(struct tegra_dc *dc) 116 { 117 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 118 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 119 } 120 121 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, 122 unsigned int bpp) 123 { 124 fixed20_12 outf = dfixed_init(out); 125 fixed20_12 inf = dfixed_init(in); 126 u32 dda_inc; 127 int max; 128 129 if (v) 130 max = 15; 131 else { 132 switch (bpp) { 133 case 2: 134 max = 8; 135 break; 136 137 default: 138 WARN_ON_ONCE(1); 139 fallthrough; 140 case 4: 141 max = 4; 142 break; 143 } 144 } 145 146 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); 147 inf.full -= dfixed_const(1); 148 149 dda_inc = dfixed_div(inf, outf); 150 dda_inc = min_t(u32, dda_inc, dfixed_const(max)); 151 152 return dda_inc; 153 } 154 155 static inline u32 compute_initial_dda(unsigned int in) 156 { 157 fixed20_12 inf = dfixed_init(in); 158 return dfixed_frac(inf); 159 } 160 161 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane) 162 { 163 u32 background[3] = { 164 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 165 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 166 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 167 }; 168 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) | 169 BLEND_COLOR_KEY_NONE; 170 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255); 171 struct tegra_plane_state *state; 172 u32 blending[2]; 173 unsigned int i; 174 175 /* disable blending for non-overlapping case */ 176 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY); 177 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN); 178 179 state = to_tegra_plane_state(plane->base.state); 180 181 if (state->opaque) { 182 /* 183 * Since custom fix-weight blending isn't utilized and weight 184 * of top window is set to max, we can enforce dependent 185 * blending which in this case results in transparent bottom 186 * window if top window is opaque and if top window enables 187 * alpha blending, then bottom window is getting alpha value 188 * of 1 minus the sum of alpha components of the overlapping 189 * plane. 190 */ 191 background[0] |= BLEND_CONTROL_DEPENDENT; 192 background[1] |= BLEND_CONTROL_DEPENDENT; 193 194 /* 195 * The region where three windows overlap is the intersection 196 * of the two regions where two windows overlap. It contributes 197 * to the area if all of the windows on top of it have an alpha 198 * component. 199 */ 200 switch (state->base.normalized_zpos) { 201 case 0: 202 if (state->blending[0].alpha && 203 state->blending[1].alpha) 204 background[2] |= BLEND_CONTROL_DEPENDENT; 205 break; 206 207 case 1: 208 background[2] |= BLEND_CONTROL_DEPENDENT; 209 break; 210 } 211 } else { 212 /* 213 * Enable alpha blending if pixel format has an alpha 214 * component. 215 */ 216 foreground |= BLEND_CONTROL_ALPHA; 217 218 /* 219 * If any of the windows on top of this window is opaque, it 220 * will completely conceal this window within that area. If 221 * top window has an alpha component, it is blended over the 222 * bottom window. 223 */ 224 for (i = 0; i < 2; i++) { 225 if (state->blending[i].alpha && 226 state->blending[i].top) 227 background[i] |= BLEND_CONTROL_DEPENDENT; 228 } 229 230 switch (state->base.normalized_zpos) { 231 case 0: 232 if (state->blending[0].alpha && 233 state->blending[1].alpha) 234 background[2] |= BLEND_CONTROL_DEPENDENT; 235 break; 236 237 case 1: 238 /* 239 * When both middle and topmost windows have an alpha, 240 * these windows a mixed together and then the result 241 * is blended over the bottom window. 242 */ 243 if (state->blending[0].alpha && 244 state->blending[0].top) 245 background[2] |= BLEND_CONTROL_ALPHA; 246 247 if (state->blending[1].alpha && 248 state->blending[1].top) 249 background[2] |= BLEND_CONTROL_ALPHA; 250 break; 251 } 252 } 253 254 switch (state->base.normalized_zpos) { 255 case 0: 256 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X); 257 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y); 258 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY); 259 break; 260 261 case 1: 262 /* 263 * If window B / C is topmost, then X / Y registers are 264 * matching the order of blending[...] state indices, 265 * otherwise a swap is required. 266 */ 267 if (!state->blending[0].top && state->blending[1].top) { 268 blending[0] = foreground; 269 blending[1] = background[1]; 270 } else { 271 blending[0] = background[0]; 272 blending[1] = foreground; 273 } 274 275 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X); 276 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y); 277 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY); 278 break; 279 280 case 2: 281 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X); 282 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y); 283 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY); 284 break; 285 } 286 } 287 288 static void tegra_plane_setup_blending(struct tegra_plane *plane, 289 const struct tegra_dc_window *window) 290 { 291 u32 value; 292 293 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 294 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 295 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 296 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT); 297 298 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 299 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 300 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 301 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT); 302 303 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos); 304 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL); 305 } 306 307 static bool 308 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane, 309 const struct tegra_dc_window *window) 310 { 311 struct tegra_dc *dc = plane->dc; 312 313 if (window->src.w == window->dst.w) 314 return false; 315 316 if (plane->index == 0 && dc->soc->has_win_a_without_filters) 317 return false; 318 319 return true; 320 } 321 322 static bool 323 tegra_plane_use_vertical_filtering(struct tegra_plane *plane, 324 const struct tegra_dc_window *window) 325 { 326 struct tegra_dc *dc = plane->dc; 327 328 if (window->src.h == window->dst.h) 329 return false; 330 331 if (plane->index == 0 && dc->soc->has_win_a_without_filters) 332 return false; 333 334 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter) 335 return false; 336 337 return true; 338 } 339 340 static void tegra_dc_setup_window(struct tegra_plane *plane, 341 const struct tegra_dc_window *window) 342 { 343 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; 344 struct tegra_dc *dc = plane->dc; 345 bool yuv, planar; 346 u32 value; 347 348 /* 349 * For YUV planar modes, the number of bytes per pixel takes into 350 * account only the luma component and therefore is 1. 351 */ 352 yuv = tegra_plane_format_is_yuv(window->format, &planar, NULL); 353 if (!yuv) 354 bpp = window->bits_per_pixel / 8; 355 else 356 bpp = planar ? 1 : 2; 357 358 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH); 359 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP); 360 361 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); 362 tegra_plane_writel(plane, value, DC_WIN_POSITION); 363 364 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); 365 tegra_plane_writel(plane, value, DC_WIN_SIZE); 366 367 h_offset = window->src.x * bpp; 368 v_offset = window->src.y; 369 h_size = window->src.w * bpp; 370 v_size = window->src.h; 371 372 if (window->reflect_x) 373 h_offset += (window->src.w - 1) * bpp; 374 375 if (window->reflect_y) 376 v_offset += window->src.h - 1; 377 378 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); 379 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE); 380 381 /* 382 * For DDA computations the number of bytes per pixel for YUV planar 383 * modes needs to take into account all Y, U and V components. 384 */ 385 if (yuv && planar) 386 bpp = 2; 387 388 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); 389 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); 390 391 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); 392 tegra_plane_writel(plane, value, DC_WIN_DDA_INC); 393 394 h_dda = compute_initial_dda(window->src.x); 395 v_dda = compute_initial_dda(window->src.y); 396 397 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA); 398 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA); 399 400 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE); 401 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE); 402 403 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR); 404 405 if (yuv && planar) { 406 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U); 407 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V); 408 value = window->stride[1] << 16 | window->stride[0]; 409 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE); 410 } else { 411 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE); 412 } 413 414 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET); 415 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET); 416 417 if (dc->soc->supports_block_linear) { 418 unsigned long height = window->tiling.value; 419 420 switch (window->tiling.mode) { 421 case TEGRA_BO_TILING_MODE_PITCH: 422 value = DC_WINBUF_SURFACE_KIND_PITCH; 423 break; 424 425 case TEGRA_BO_TILING_MODE_TILED: 426 value = DC_WINBUF_SURFACE_KIND_TILED; 427 break; 428 429 case TEGRA_BO_TILING_MODE_BLOCK: 430 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | 431 DC_WINBUF_SURFACE_KIND_BLOCK; 432 break; 433 } 434 435 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND); 436 } else { 437 switch (window->tiling.mode) { 438 case TEGRA_BO_TILING_MODE_PITCH: 439 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | 440 DC_WIN_BUFFER_ADDR_MODE_LINEAR; 441 break; 442 443 case TEGRA_BO_TILING_MODE_TILED: 444 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | 445 DC_WIN_BUFFER_ADDR_MODE_TILE; 446 break; 447 448 case TEGRA_BO_TILING_MODE_BLOCK: 449 /* 450 * No need to handle this here because ->atomic_check 451 * will already have filtered it out. 452 */ 453 break; 454 } 455 456 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE); 457 } 458 459 value = WIN_ENABLE; 460 461 if (yuv) { 462 /* setup default colorspace conversion coefficients */ 463 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF); 464 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB); 465 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR); 466 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR); 467 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG); 468 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG); 469 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB); 470 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB); 471 472 value |= CSC_ENABLE; 473 } else if (window->bits_per_pixel < 24) { 474 value |= COLOR_EXPAND; 475 } 476 477 if (window->reflect_x) 478 value |= H_DIRECTION; 479 480 if (window->reflect_y) 481 value |= V_DIRECTION; 482 483 if (tegra_plane_use_horizontal_filtering(plane, window)) { 484 /* 485 * Enable horizontal 6-tap filter and set filtering 486 * coefficients to the default values defined in TRM. 487 */ 488 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0)); 489 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1)); 490 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2)); 491 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3)); 492 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4)); 493 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5)); 494 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6)); 495 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7)); 496 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8)); 497 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9)); 498 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10)); 499 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11)); 500 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12)); 501 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13)); 502 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14)); 503 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15)); 504 505 value |= H_FILTER; 506 } 507 508 if (tegra_plane_use_vertical_filtering(plane, window)) { 509 unsigned int i, k; 510 511 /* 512 * Enable vertical 2-tap filter and set filtering 513 * coefficients to the default values defined in TRM. 514 */ 515 for (i = 0, k = 128; i < 16; i++, k -= 8) 516 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i)); 517 518 value |= V_FILTER; 519 } 520 521 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS); 522 523 if (dc->soc->has_legacy_blending) 524 tegra_plane_setup_blending_legacy(plane); 525 else 526 tegra_plane_setup_blending(plane, window); 527 } 528 529 static const u32 tegra20_primary_formats[] = { 530 DRM_FORMAT_ARGB4444, 531 DRM_FORMAT_ARGB1555, 532 DRM_FORMAT_RGB565, 533 DRM_FORMAT_RGBA5551, 534 DRM_FORMAT_ABGR8888, 535 DRM_FORMAT_ARGB8888, 536 /* non-native formats */ 537 DRM_FORMAT_XRGB1555, 538 DRM_FORMAT_RGBX5551, 539 DRM_FORMAT_XBGR8888, 540 DRM_FORMAT_XRGB8888, 541 }; 542 543 static const u64 tegra20_modifiers[] = { 544 DRM_FORMAT_MOD_LINEAR, 545 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED, 546 DRM_FORMAT_MOD_INVALID 547 }; 548 549 static const u32 tegra114_primary_formats[] = { 550 DRM_FORMAT_ARGB4444, 551 DRM_FORMAT_ARGB1555, 552 DRM_FORMAT_RGB565, 553 DRM_FORMAT_RGBA5551, 554 DRM_FORMAT_ABGR8888, 555 DRM_FORMAT_ARGB8888, 556 /* new on Tegra114 */ 557 DRM_FORMAT_ABGR4444, 558 DRM_FORMAT_ABGR1555, 559 DRM_FORMAT_BGRA5551, 560 DRM_FORMAT_XRGB1555, 561 DRM_FORMAT_RGBX5551, 562 DRM_FORMAT_XBGR1555, 563 DRM_FORMAT_BGRX5551, 564 DRM_FORMAT_BGR565, 565 DRM_FORMAT_BGRA8888, 566 DRM_FORMAT_RGBA8888, 567 DRM_FORMAT_XRGB8888, 568 DRM_FORMAT_XBGR8888, 569 }; 570 571 static const u32 tegra124_primary_formats[] = { 572 DRM_FORMAT_ARGB4444, 573 DRM_FORMAT_ARGB1555, 574 DRM_FORMAT_RGB565, 575 DRM_FORMAT_RGBA5551, 576 DRM_FORMAT_ABGR8888, 577 DRM_FORMAT_ARGB8888, 578 /* new on Tegra114 */ 579 DRM_FORMAT_ABGR4444, 580 DRM_FORMAT_ABGR1555, 581 DRM_FORMAT_BGRA5551, 582 DRM_FORMAT_XRGB1555, 583 DRM_FORMAT_RGBX5551, 584 DRM_FORMAT_XBGR1555, 585 DRM_FORMAT_BGRX5551, 586 DRM_FORMAT_BGR565, 587 DRM_FORMAT_BGRA8888, 588 DRM_FORMAT_RGBA8888, 589 DRM_FORMAT_XRGB8888, 590 DRM_FORMAT_XBGR8888, 591 /* new on Tegra124 */ 592 DRM_FORMAT_RGBX8888, 593 DRM_FORMAT_BGRX8888, 594 }; 595 596 static const u64 tegra124_modifiers[] = { 597 DRM_FORMAT_MOD_LINEAR, 598 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0), 599 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1), 600 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2), 601 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3), 602 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4), 603 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5), 604 DRM_FORMAT_MOD_INVALID 605 }; 606 607 static int tegra_plane_atomic_check(struct drm_plane *plane, 608 struct drm_atomic_state *state) 609 { 610 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 611 plane); 612 struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state); 613 unsigned int supported_rotation = DRM_MODE_ROTATE_0 | 614 DRM_MODE_REFLECT_X | 615 DRM_MODE_REFLECT_Y; 616 unsigned int rotation = new_plane_state->rotation; 617 struct tegra_bo_tiling *tiling = &plane_state->tiling; 618 struct tegra_plane *tegra = to_tegra_plane(plane); 619 struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc); 620 int err; 621 622 plane_state->peak_memory_bandwidth = 0; 623 plane_state->avg_memory_bandwidth = 0; 624 625 /* no need for further checks if the plane is being disabled */ 626 if (!new_plane_state->crtc) { 627 plane_state->total_peak_memory_bandwidth = 0; 628 return 0; 629 } 630 631 err = tegra_plane_format(new_plane_state->fb->format->format, 632 &plane_state->format, 633 &plane_state->swap); 634 if (err < 0) 635 return err; 636 637 /* 638 * Tegra20 and Tegra30 are special cases here because they support 639 * only variants of specific formats with an alpha component, but not 640 * the corresponding opaque formats. However, the opaque formats can 641 * be emulated by disabling alpha blending for the plane. 642 */ 643 if (dc->soc->has_legacy_blending) { 644 err = tegra_plane_setup_legacy_state(tegra, plane_state); 645 if (err < 0) 646 return err; 647 } 648 649 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); 650 if (err < 0) 651 return err; 652 653 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && 654 !dc->soc->supports_block_linear) { 655 DRM_ERROR("hardware doesn't support block linear mode\n"); 656 return -EINVAL; 657 } 658 659 /* 660 * Older userspace used custom BO flag in order to specify the Y 661 * reflection, while modern userspace uses the generic DRM rotation 662 * property in order to achieve the same result. The legacy BO flag 663 * duplicates the DRM rotation property when both are set. 664 */ 665 if (tegra_fb_is_bottom_up(new_plane_state->fb)) 666 rotation |= DRM_MODE_REFLECT_Y; 667 668 rotation = drm_rotation_simplify(rotation, supported_rotation); 669 670 if (rotation & DRM_MODE_REFLECT_X) 671 plane_state->reflect_x = true; 672 else 673 plane_state->reflect_x = false; 674 675 if (rotation & DRM_MODE_REFLECT_Y) 676 plane_state->reflect_y = true; 677 else 678 plane_state->reflect_y = false; 679 680 /* 681 * Tegra doesn't support different strides for U and V planes so we 682 * error out if the user tries to display a framebuffer with such a 683 * configuration. 684 */ 685 if (new_plane_state->fb->format->num_planes > 2) { 686 if (new_plane_state->fb->pitches[2] != new_plane_state->fb->pitches[1]) { 687 DRM_ERROR("unsupported UV-plane configuration\n"); 688 return -EINVAL; 689 } 690 } 691 692 err = tegra_plane_state_add(tegra, new_plane_state); 693 if (err < 0) 694 return err; 695 696 return 0; 697 } 698 699 static void tegra_plane_atomic_disable(struct drm_plane *plane, 700 struct drm_atomic_state *state) 701 { 702 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 703 plane); 704 struct tegra_plane *p = to_tegra_plane(plane); 705 u32 value; 706 707 /* rien ne va plus */ 708 if (!old_state || !old_state->crtc) 709 return; 710 711 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS); 712 value &= ~WIN_ENABLE; 713 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS); 714 } 715 716 static void tegra_plane_atomic_update(struct drm_plane *plane, 717 struct drm_atomic_state *state) 718 { 719 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 720 plane); 721 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state); 722 struct drm_framebuffer *fb = new_state->fb; 723 struct tegra_plane *p = to_tegra_plane(plane); 724 struct tegra_dc_window window; 725 unsigned int i; 726 727 /* rien ne va plus */ 728 if (!new_state->crtc || !new_state->fb) 729 return; 730 731 if (!new_state->visible) 732 return tegra_plane_atomic_disable(plane, state); 733 734 memset(&window, 0, sizeof(window)); 735 window.src.x = new_state->src.x1 >> 16; 736 window.src.y = new_state->src.y1 >> 16; 737 window.src.w = drm_rect_width(&new_state->src) >> 16; 738 window.src.h = drm_rect_height(&new_state->src) >> 16; 739 window.dst.x = new_state->dst.x1; 740 window.dst.y = new_state->dst.y1; 741 window.dst.w = drm_rect_width(&new_state->dst); 742 window.dst.h = drm_rect_height(&new_state->dst); 743 window.bits_per_pixel = fb->format->cpp[0] * 8; 744 window.reflect_x = tegra_plane_state->reflect_x; 745 window.reflect_y = tegra_plane_state->reflect_y; 746 747 /* copy from state */ 748 window.zpos = new_state->normalized_zpos; 749 window.tiling = tegra_plane_state->tiling; 750 window.format = tegra_plane_state->format; 751 window.swap = tegra_plane_state->swap; 752 753 for (i = 0; i < fb->format->num_planes; i++) { 754 window.base[i] = tegra_plane_state->iova[i] + fb->offsets[i]; 755 756 /* 757 * Tegra uses a shared stride for UV planes. Framebuffers are 758 * already checked for this in the tegra_plane_atomic_check() 759 * function, so it's safe to ignore the V-plane pitch here. 760 */ 761 if (i < 2) 762 window.stride[i] = fb->pitches[i]; 763 } 764 765 tegra_dc_setup_window(p, &window); 766 } 767 768 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = { 769 .prepare_fb = tegra_plane_prepare_fb, 770 .cleanup_fb = tegra_plane_cleanup_fb, 771 .atomic_check = tegra_plane_atomic_check, 772 .atomic_disable = tegra_plane_atomic_disable, 773 .atomic_update = tegra_plane_atomic_update, 774 }; 775 776 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm) 777 { 778 /* 779 * Ideally this would use drm_crtc_mask(), but that would require the 780 * CRTC to already be in the mode_config's list of CRTCs. However, it 781 * will only be added to that list in the drm_crtc_init_with_planes() 782 * (in tegra_dc_init()), which in turn requires registration of these 783 * planes. So we have ourselves a nice little chicken and egg problem 784 * here. 785 * 786 * We work around this by manually creating the mask from the number 787 * of CRTCs that have been registered, and should therefore always be 788 * the same as drm_crtc_index() after registration. 789 */ 790 return 1 << drm->mode_config.num_crtc; 791 } 792 793 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm, 794 struct tegra_dc *dc) 795 { 796 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 797 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY; 798 struct tegra_plane *plane; 799 unsigned int num_formats; 800 const u64 *modifiers; 801 const u32 *formats; 802 int err; 803 804 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 805 if (!plane) 806 return ERR_PTR(-ENOMEM); 807 808 /* Always use window A as primary window */ 809 plane->offset = 0xa00; 810 plane->index = 0; 811 plane->dc = dc; 812 813 num_formats = dc->soc->num_primary_formats; 814 formats = dc->soc->primary_formats; 815 modifiers = dc->soc->modifiers; 816 817 err = tegra_plane_interconnect_init(plane); 818 if (err) { 819 kfree(plane); 820 return ERR_PTR(err); 821 } 822 823 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 824 &tegra_plane_funcs, formats, 825 num_formats, modifiers, type, NULL); 826 if (err < 0) { 827 kfree(plane); 828 return ERR_PTR(err); 829 } 830 831 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 832 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); 833 834 err = drm_plane_create_rotation_property(&plane->base, 835 DRM_MODE_ROTATE_0, 836 DRM_MODE_ROTATE_0 | 837 DRM_MODE_ROTATE_180 | 838 DRM_MODE_REFLECT_X | 839 DRM_MODE_REFLECT_Y); 840 if (err < 0) 841 dev_err(dc->dev, "failed to create rotation property: %d\n", 842 err); 843 844 return &plane->base; 845 } 846 847 static const u32 tegra_legacy_cursor_plane_formats[] = { 848 DRM_FORMAT_RGBA8888, 849 }; 850 851 static const u32 tegra_cursor_plane_formats[] = { 852 DRM_FORMAT_ARGB8888, 853 }; 854 855 static int tegra_cursor_atomic_check(struct drm_plane *plane, 856 struct drm_atomic_state *state) 857 { 858 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 859 plane); 860 struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state); 861 struct tegra_plane *tegra = to_tegra_plane(plane); 862 int err; 863 864 plane_state->peak_memory_bandwidth = 0; 865 plane_state->avg_memory_bandwidth = 0; 866 867 /* no need for further checks if the plane is being disabled */ 868 if (!new_plane_state->crtc) { 869 plane_state->total_peak_memory_bandwidth = 0; 870 return 0; 871 } 872 873 /* scaling not supported for cursor */ 874 if ((new_plane_state->src_w >> 16 != new_plane_state->crtc_w) || 875 (new_plane_state->src_h >> 16 != new_plane_state->crtc_h)) 876 return -EINVAL; 877 878 /* only square cursors supported */ 879 if (new_plane_state->src_w != new_plane_state->src_h) 880 return -EINVAL; 881 882 if (new_plane_state->crtc_w != 32 && new_plane_state->crtc_w != 64 && 883 new_plane_state->crtc_w != 128 && new_plane_state->crtc_w != 256) 884 return -EINVAL; 885 886 err = tegra_plane_state_add(tegra, new_plane_state); 887 if (err < 0) 888 return err; 889 890 return 0; 891 } 892 893 static void __tegra_cursor_atomic_update(struct drm_plane *plane, 894 struct drm_plane_state *new_state) 895 { 896 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state); 897 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); 898 struct tegra_drm *tegra = plane->dev->dev_private; 899 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 900 u64 dma_mask = *dc->dev->dma_mask; 901 #endif 902 unsigned int x, y; 903 u32 value = 0; 904 905 /* rien ne va plus */ 906 if (!new_state->crtc || !new_state->fb) 907 return; 908 909 /* 910 * Legacy display supports hardware clipping of the cursor, but 911 * nvdisplay relies on software to clip the cursor to the screen. 912 */ 913 if (!dc->soc->has_nvdisplay) 914 value |= CURSOR_CLIP_DISPLAY; 915 916 switch (new_state->crtc_w) { 917 case 32: 918 value |= CURSOR_SIZE_32x32; 919 break; 920 921 case 64: 922 value |= CURSOR_SIZE_64x64; 923 break; 924 925 case 128: 926 value |= CURSOR_SIZE_128x128; 927 break; 928 929 case 256: 930 value |= CURSOR_SIZE_256x256; 931 break; 932 933 default: 934 WARN(1, "cursor size %ux%u not supported\n", 935 new_state->crtc_w, new_state->crtc_h); 936 return; 937 } 938 939 value |= (tegra_plane_state->iova[0] >> 10) & 0x3fffff; 940 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); 941 942 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 943 value = (tegra_plane_state->iova[0] >> 32) & (dma_mask >> 32); 944 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); 945 #endif 946 947 /* enable cursor and set blend mode */ 948 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 949 value |= CURSOR_ENABLE; 950 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 951 952 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); 953 value &= ~CURSOR_DST_BLEND_MASK; 954 value &= ~CURSOR_SRC_BLEND_MASK; 955 956 if (dc->soc->has_nvdisplay) 957 value &= ~CURSOR_COMPOSITION_MODE_XOR; 958 else 959 value |= CURSOR_MODE_NORMAL; 960 961 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; 962 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; 963 value |= CURSOR_ALPHA; 964 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); 965 966 /* nvdisplay relies on software for clipping */ 967 if (dc->soc->has_nvdisplay) { 968 struct drm_rect src; 969 970 x = new_state->dst.x1; 971 y = new_state->dst.y1; 972 973 drm_rect_fp_to_int(&src, &new_state->src); 974 975 value = (src.y1 & tegra->vmask) << 16 | (src.x1 & tegra->hmask); 976 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR); 977 978 value = (drm_rect_height(&src) & tegra->vmask) << 16 | 979 (drm_rect_width(&src) & tegra->hmask); 980 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR); 981 } else { 982 x = new_state->crtc_x; 983 y = new_state->crtc_y; 984 } 985 986 /* position the cursor */ 987 value = ((y & tegra->vmask) << 16) | (x & tegra->hmask); 988 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); 989 } 990 991 static void tegra_cursor_atomic_update(struct drm_plane *plane, 992 struct drm_atomic_state *state) 993 { 994 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); 995 996 __tegra_cursor_atomic_update(plane, new_state); 997 } 998 999 static void tegra_cursor_atomic_disable(struct drm_plane *plane, 1000 struct drm_atomic_state *state) 1001 { 1002 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 1003 plane); 1004 struct tegra_dc *dc; 1005 u32 value; 1006 1007 /* rien ne va plus */ 1008 if (!old_state || !old_state->crtc) 1009 return; 1010 1011 dc = to_tegra_dc(old_state->crtc); 1012 1013 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1014 value &= ~CURSOR_ENABLE; 1015 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1016 } 1017 1018 static int tegra_cursor_atomic_async_check(struct drm_plane *plane, struct drm_atomic_state *state) 1019 { 1020 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); 1021 struct drm_crtc_state *crtc_state; 1022 int min_scale, max_scale; 1023 int err; 1024 1025 crtc_state = drm_atomic_get_existing_crtc_state(state, new_state->crtc); 1026 if (WARN_ON(!crtc_state)) 1027 return -EINVAL; 1028 1029 if (!crtc_state->active) 1030 return -EINVAL; 1031 1032 if (plane->state->crtc != new_state->crtc || 1033 plane->state->src_w != new_state->src_w || 1034 plane->state->src_h != new_state->src_h || 1035 plane->state->crtc_w != new_state->crtc_w || 1036 plane->state->crtc_h != new_state->crtc_h || 1037 plane->state->fb != new_state->fb || 1038 plane->state->fb == NULL) 1039 return -EINVAL; 1040 1041 min_scale = (1 << 16) / 8; 1042 max_scale = (8 << 16) / 1; 1043 1044 err = drm_atomic_helper_check_plane_state(new_state, crtc_state, min_scale, max_scale, 1045 true, true); 1046 if (err < 0) 1047 return err; 1048 1049 if (new_state->visible != plane->state->visible) 1050 return -EINVAL; 1051 1052 return 0; 1053 } 1054 1055 static void tegra_cursor_atomic_async_update(struct drm_plane *plane, 1056 struct drm_atomic_state *state) 1057 { 1058 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); 1059 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); 1060 1061 plane->state->src_x = new_state->src_x; 1062 plane->state->src_y = new_state->src_y; 1063 plane->state->crtc_x = new_state->crtc_x; 1064 plane->state->crtc_y = new_state->crtc_y; 1065 1066 if (new_state->visible) { 1067 struct tegra_plane *p = to_tegra_plane(plane); 1068 u32 value; 1069 1070 __tegra_cursor_atomic_update(plane, new_state); 1071 1072 value = (WIN_A_ACT_REQ << p->index) << 8 | GENERAL_UPDATE; 1073 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 1074 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 1075 1076 value = (WIN_A_ACT_REQ << p->index) | GENERAL_ACT_REQ; 1077 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 1078 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 1079 } 1080 } 1081 1082 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = { 1083 .prepare_fb = tegra_plane_prepare_fb, 1084 .cleanup_fb = tegra_plane_cleanup_fb, 1085 .atomic_check = tegra_cursor_atomic_check, 1086 .atomic_update = tegra_cursor_atomic_update, 1087 .atomic_disable = tegra_cursor_atomic_disable, 1088 .atomic_async_check = tegra_cursor_atomic_async_check, 1089 .atomic_async_update = tegra_cursor_atomic_async_update, 1090 }; 1091 1092 static const uint64_t linear_modifiers[] = { 1093 DRM_FORMAT_MOD_LINEAR, 1094 DRM_FORMAT_MOD_INVALID 1095 }; 1096 1097 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, 1098 struct tegra_dc *dc) 1099 { 1100 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 1101 struct tegra_plane *plane; 1102 unsigned int num_formats; 1103 const u32 *formats; 1104 int err; 1105 1106 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 1107 if (!plane) 1108 return ERR_PTR(-ENOMEM); 1109 1110 /* 1111 * This index is kind of fake. The cursor isn't a regular plane, but 1112 * its update and activation request bits in DC_CMD_STATE_CONTROL do 1113 * use the same programming. Setting this fake index here allows the 1114 * code in tegra_add_plane_state() to do the right thing without the 1115 * need to special-casing the cursor plane. 1116 */ 1117 plane->index = 6; 1118 plane->dc = dc; 1119 1120 if (!dc->soc->has_nvdisplay) { 1121 num_formats = ARRAY_SIZE(tegra_legacy_cursor_plane_formats); 1122 formats = tegra_legacy_cursor_plane_formats; 1123 1124 err = tegra_plane_interconnect_init(plane); 1125 if (err) { 1126 kfree(plane); 1127 return ERR_PTR(err); 1128 } 1129 } else { 1130 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); 1131 formats = tegra_cursor_plane_formats; 1132 } 1133 1134 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 1135 &tegra_plane_funcs, formats, 1136 num_formats, linear_modifiers, 1137 DRM_PLANE_TYPE_CURSOR, NULL); 1138 if (err < 0) { 1139 kfree(plane); 1140 return ERR_PTR(err); 1141 } 1142 1143 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); 1144 drm_plane_create_zpos_immutable_property(&plane->base, 255); 1145 1146 return &plane->base; 1147 } 1148 1149 static const u32 tegra20_overlay_formats[] = { 1150 DRM_FORMAT_ARGB4444, 1151 DRM_FORMAT_ARGB1555, 1152 DRM_FORMAT_RGB565, 1153 DRM_FORMAT_RGBA5551, 1154 DRM_FORMAT_ABGR8888, 1155 DRM_FORMAT_ARGB8888, 1156 /* non-native formats */ 1157 DRM_FORMAT_XRGB1555, 1158 DRM_FORMAT_RGBX5551, 1159 DRM_FORMAT_XBGR8888, 1160 DRM_FORMAT_XRGB8888, 1161 /* planar formats */ 1162 DRM_FORMAT_UYVY, 1163 DRM_FORMAT_YUYV, 1164 DRM_FORMAT_YUV420, 1165 DRM_FORMAT_YUV422, 1166 }; 1167 1168 static const u32 tegra114_overlay_formats[] = { 1169 DRM_FORMAT_ARGB4444, 1170 DRM_FORMAT_ARGB1555, 1171 DRM_FORMAT_RGB565, 1172 DRM_FORMAT_RGBA5551, 1173 DRM_FORMAT_ABGR8888, 1174 DRM_FORMAT_ARGB8888, 1175 /* new on Tegra114 */ 1176 DRM_FORMAT_ABGR4444, 1177 DRM_FORMAT_ABGR1555, 1178 DRM_FORMAT_BGRA5551, 1179 DRM_FORMAT_XRGB1555, 1180 DRM_FORMAT_RGBX5551, 1181 DRM_FORMAT_XBGR1555, 1182 DRM_FORMAT_BGRX5551, 1183 DRM_FORMAT_BGR565, 1184 DRM_FORMAT_BGRA8888, 1185 DRM_FORMAT_RGBA8888, 1186 DRM_FORMAT_XRGB8888, 1187 DRM_FORMAT_XBGR8888, 1188 /* planar formats */ 1189 DRM_FORMAT_UYVY, 1190 DRM_FORMAT_YUYV, 1191 DRM_FORMAT_YUV420, 1192 DRM_FORMAT_YUV422, 1193 }; 1194 1195 static const u32 tegra124_overlay_formats[] = { 1196 DRM_FORMAT_ARGB4444, 1197 DRM_FORMAT_ARGB1555, 1198 DRM_FORMAT_RGB565, 1199 DRM_FORMAT_RGBA5551, 1200 DRM_FORMAT_ABGR8888, 1201 DRM_FORMAT_ARGB8888, 1202 /* new on Tegra114 */ 1203 DRM_FORMAT_ABGR4444, 1204 DRM_FORMAT_ABGR1555, 1205 DRM_FORMAT_BGRA5551, 1206 DRM_FORMAT_XRGB1555, 1207 DRM_FORMAT_RGBX5551, 1208 DRM_FORMAT_XBGR1555, 1209 DRM_FORMAT_BGRX5551, 1210 DRM_FORMAT_BGR565, 1211 DRM_FORMAT_BGRA8888, 1212 DRM_FORMAT_RGBA8888, 1213 DRM_FORMAT_XRGB8888, 1214 DRM_FORMAT_XBGR8888, 1215 /* new on Tegra124 */ 1216 DRM_FORMAT_RGBX8888, 1217 DRM_FORMAT_BGRX8888, 1218 /* planar formats */ 1219 DRM_FORMAT_UYVY, 1220 DRM_FORMAT_YUYV, 1221 DRM_FORMAT_YUV420, 1222 DRM_FORMAT_YUV422, 1223 }; 1224 1225 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, 1226 struct tegra_dc *dc, 1227 unsigned int index, 1228 bool cursor) 1229 { 1230 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 1231 struct tegra_plane *plane; 1232 unsigned int num_formats; 1233 enum drm_plane_type type; 1234 const u32 *formats; 1235 int err; 1236 1237 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 1238 if (!plane) 1239 return ERR_PTR(-ENOMEM); 1240 1241 plane->offset = 0xa00 + 0x200 * index; 1242 plane->index = index; 1243 plane->dc = dc; 1244 1245 num_formats = dc->soc->num_overlay_formats; 1246 formats = dc->soc->overlay_formats; 1247 1248 err = tegra_plane_interconnect_init(plane); 1249 if (err) { 1250 kfree(plane); 1251 return ERR_PTR(err); 1252 } 1253 1254 if (!cursor) 1255 type = DRM_PLANE_TYPE_OVERLAY; 1256 else 1257 type = DRM_PLANE_TYPE_CURSOR; 1258 1259 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 1260 &tegra_plane_funcs, formats, 1261 num_formats, linear_modifiers, 1262 type, NULL); 1263 if (err < 0) { 1264 kfree(plane); 1265 return ERR_PTR(err); 1266 } 1267 1268 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 1269 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); 1270 1271 err = drm_plane_create_rotation_property(&plane->base, 1272 DRM_MODE_ROTATE_0, 1273 DRM_MODE_ROTATE_0 | 1274 DRM_MODE_ROTATE_180 | 1275 DRM_MODE_REFLECT_X | 1276 DRM_MODE_REFLECT_Y); 1277 if (err < 0) 1278 dev_err(dc->dev, "failed to create rotation property: %d\n", 1279 err); 1280 1281 return &plane->base; 1282 } 1283 1284 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm, 1285 struct tegra_dc *dc) 1286 { 1287 struct drm_plane *plane, *primary = NULL; 1288 unsigned int i, j; 1289 1290 for (i = 0; i < dc->soc->num_wgrps; i++) { 1291 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; 1292 1293 if (wgrp->dc == dc->pipe) { 1294 for (j = 0; j < wgrp->num_windows; j++) { 1295 unsigned int index = wgrp->windows[j]; 1296 1297 plane = tegra_shared_plane_create(drm, dc, 1298 wgrp->index, 1299 index); 1300 if (IS_ERR(plane)) 1301 return plane; 1302 1303 /* 1304 * Choose the first shared plane owned by this 1305 * head as the primary plane. 1306 */ 1307 if (!primary) { 1308 plane->type = DRM_PLANE_TYPE_PRIMARY; 1309 primary = plane; 1310 } 1311 } 1312 } 1313 } 1314 1315 return primary; 1316 } 1317 1318 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm, 1319 struct tegra_dc *dc) 1320 { 1321 struct drm_plane *planes[2], *primary; 1322 unsigned int planes_num; 1323 unsigned int i; 1324 int err; 1325 1326 primary = tegra_primary_plane_create(drm, dc); 1327 if (IS_ERR(primary)) 1328 return primary; 1329 1330 if (dc->soc->supports_cursor) 1331 planes_num = 2; 1332 else 1333 planes_num = 1; 1334 1335 for (i = 0; i < planes_num; i++) { 1336 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i, 1337 false); 1338 if (IS_ERR(planes[i])) { 1339 err = PTR_ERR(planes[i]); 1340 1341 while (i--) 1342 planes[i]->funcs->destroy(planes[i]); 1343 1344 primary->funcs->destroy(primary); 1345 return ERR_PTR(err); 1346 } 1347 } 1348 1349 return primary; 1350 } 1351 1352 static void tegra_dc_destroy(struct drm_crtc *crtc) 1353 { 1354 drm_crtc_cleanup(crtc); 1355 } 1356 1357 static void tegra_crtc_reset(struct drm_crtc *crtc) 1358 { 1359 struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 1360 1361 if (crtc->state) 1362 tegra_crtc_atomic_destroy_state(crtc, crtc->state); 1363 1364 __drm_atomic_helper_crtc_reset(crtc, &state->base); 1365 } 1366 1367 static struct drm_crtc_state * 1368 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 1369 { 1370 struct tegra_dc_state *state = to_dc_state(crtc->state); 1371 struct tegra_dc_state *copy; 1372 1373 copy = kmalloc(sizeof(*copy), GFP_KERNEL); 1374 if (!copy) 1375 return NULL; 1376 1377 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base); 1378 copy->clk = state->clk; 1379 copy->pclk = state->pclk; 1380 copy->div = state->div; 1381 copy->planes = state->planes; 1382 1383 return ©->base; 1384 } 1385 1386 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, 1387 struct drm_crtc_state *state) 1388 { 1389 __drm_atomic_helper_crtc_destroy_state(state); 1390 kfree(state); 1391 } 1392 1393 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 1394 1395 static const struct debugfs_reg32 tegra_dc_regs[] = { 1396 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT), 1397 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL), 1398 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR), 1399 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT), 1400 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL), 1401 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR), 1402 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT), 1403 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL), 1404 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR), 1405 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT), 1406 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL), 1407 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR), 1408 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC), 1409 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0), 1410 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND), 1411 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE), 1412 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL), 1413 DEBUGFS_REG32(DC_CMD_INT_STATUS), 1414 DEBUGFS_REG32(DC_CMD_INT_MASK), 1415 DEBUGFS_REG32(DC_CMD_INT_ENABLE), 1416 DEBUGFS_REG32(DC_CMD_INT_TYPE), 1417 DEBUGFS_REG32(DC_CMD_INT_POLARITY), 1418 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1), 1419 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2), 1420 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3), 1421 DEBUGFS_REG32(DC_CMD_STATE_ACCESS), 1422 DEBUGFS_REG32(DC_CMD_STATE_CONTROL), 1423 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER), 1424 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL), 1425 DEBUGFS_REG32(DC_COM_CRC_CONTROL), 1426 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM), 1427 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)), 1428 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)), 1429 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)), 1430 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)), 1431 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)), 1432 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)), 1433 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)), 1434 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)), 1435 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)), 1436 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)), 1437 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)), 1438 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)), 1439 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)), 1440 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)), 1441 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)), 1442 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)), 1443 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)), 1444 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)), 1445 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)), 1446 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)), 1447 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)), 1448 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)), 1449 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)), 1450 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)), 1451 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)), 1452 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL), 1453 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL), 1454 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE), 1455 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL), 1456 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE), 1457 DEBUGFS_REG32(DC_COM_SPI_CONTROL), 1458 DEBUGFS_REG32(DC_COM_SPI_START_BYTE), 1459 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB), 1460 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD), 1461 DEBUGFS_REG32(DC_COM_HSPI_CS_DC), 1462 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A), 1463 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B), 1464 DEBUGFS_REG32(DC_COM_GPIO_CTRL), 1465 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER), 1466 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED), 1467 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0), 1468 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1), 1469 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS), 1470 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY), 1471 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER), 1472 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS), 1473 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC), 1474 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH), 1475 DEBUGFS_REG32(DC_DISP_BACK_PORCH), 1476 DEBUGFS_REG32(DC_DISP_ACTIVE), 1477 DEBUGFS_REG32(DC_DISP_FRONT_PORCH), 1478 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL), 1479 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A), 1480 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B), 1481 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C), 1482 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D), 1483 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL), 1484 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A), 1485 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B), 1486 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C), 1487 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D), 1488 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL), 1489 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A), 1490 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B), 1491 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C), 1492 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D), 1493 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL), 1494 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A), 1495 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B), 1496 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C), 1497 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL), 1498 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A), 1499 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B), 1500 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C), 1501 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL), 1502 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A), 1503 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL), 1504 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A), 1505 DEBUGFS_REG32(DC_DISP_M0_CONTROL), 1506 DEBUGFS_REG32(DC_DISP_M1_CONTROL), 1507 DEBUGFS_REG32(DC_DISP_DI_CONTROL), 1508 DEBUGFS_REG32(DC_DISP_PP_CONTROL), 1509 DEBUGFS_REG32(DC_DISP_PP_SELECT_A), 1510 DEBUGFS_REG32(DC_DISP_PP_SELECT_B), 1511 DEBUGFS_REG32(DC_DISP_PP_SELECT_C), 1512 DEBUGFS_REG32(DC_DISP_PP_SELECT_D), 1513 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL), 1514 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL), 1515 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL), 1516 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS), 1517 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS), 1518 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS), 1519 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS), 1520 DEBUGFS_REG32(DC_DISP_BORDER_COLOR), 1521 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER), 1522 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER), 1523 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER), 1524 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER), 1525 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND), 1526 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND), 1527 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR), 1528 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS), 1529 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION), 1530 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS), 1531 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL), 1532 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A), 1533 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B), 1534 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C), 1535 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D), 1536 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL), 1537 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST), 1538 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST), 1539 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST), 1540 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST), 1541 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL), 1542 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL), 1543 DEBUGFS_REG32(DC_DISP_SD_CONTROL), 1544 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF), 1545 DEBUGFS_REG32(DC_DISP_SD_LUT(0)), 1546 DEBUGFS_REG32(DC_DISP_SD_LUT(1)), 1547 DEBUGFS_REG32(DC_DISP_SD_LUT(2)), 1548 DEBUGFS_REG32(DC_DISP_SD_LUT(3)), 1549 DEBUGFS_REG32(DC_DISP_SD_LUT(4)), 1550 DEBUGFS_REG32(DC_DISP_SD_LUT(5)), 1551 DEBUGFS_REG32(DC_DISP_SD_LUT(6)), 1552 DEBUGFS_REG32(DC_DISP_SD_LUT(7)), 1553 DEBUGFS_REG32(DC_DISP_SD_LUT(8)), 1554 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL), 1555 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT), 1556 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)), 1557 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)), 1558 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)), 1559 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)), 1560 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)), 1561 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)), 1562 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)), 1563 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)), 1564 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)), 1565 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)), 1566 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)), 1567 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)), 1568 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL), 1569 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES), 1570 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES), 1571 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI), 1572 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL), 1573 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS), 1574 DEBUGFS_REG32(DC_WIN_BYTE_SWAP), 1575 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL), 1576 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH), 1577 DEBUGFS_REG32(DC_WIN_POSITION), 1578 DEBUGFS_REG32(DC_WIN_SIZE), 1579 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE), 1580 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA), 1581 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA), 1582 DEBUGFS_REG32(DC_WIN_DDA_INC), 1583 DEBUGFS_REG32(DC_WIN_LINE_STRIDE), 1584 DEBUGFS_REG32(DC_WIN_BUF_STRIDE), 1585 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE), 1586 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE), 1587 DEBUGFS_REG32(DC_WIN_DV_CONTROL), 1588 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY), 1589 DEBUGFS_REG32(DC_WIN_BLEND_1WIN), 1590 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X), 1591 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y), 1592 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY), 1593 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL), 1594 DEBUGFS_REG32(DC_WINBUF_START_ADDR), 1595 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS), 1596 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U), 1597 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS), 1598 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V), 1599 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS), 1600 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET), 1601 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS), 1602 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET), 1603 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS), 1604 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS), 1605 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS), 1606 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS), 1607 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS), 1608 }; 1609 1610 static int tegra_dc_show_regs(struct seq_file *s, void *data) 1611 { 1612 struct drm_info_node *node = s->private; 1613 struct tegra_dc *dc = node->info_ent->data; 1614 unsigned int i; 1615 int err = 0; 1616 1617 drm_modeset_lock(&dc->base.mutex, NULL); 1618 1619 if (!dc->base.state->active) { 1620 err = -EBUSY; 1621 goto unlock; 1622 } 1623 1624 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) { 1625 unsigned int offset = tegra_dc_regs[i].offset; 1626 1627 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name, 1628 offset, tegra_dc_readl(dc, offset)); 1629 } 1630 1631 unlock: 1632 drm_modeset_unlock(&dc->base.mutex); 1633 return err; 1634 } 1635 1636 static int tegra_dc_show_crc(struct seq_file *s, void *data) 1637 { 1638 struct drm_info_node *node = s->private; 1639 struct tegra_dc *dc = node->info_ent->data; 1640 int err = 0; 1641 u32 value; 1642 1643 drm_modeset_lock(&dc->base.mutex, NULL); 1644 1645 if (!dc->base.state->active) { 1646 err = -EBUSY; 1647 goto unlock; 1648 } 1649 1650 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE; 1651 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); 1652 tegra_dc_commit(dc); 1653 1654 drm_crtc_wait_one_vblank(&dc->base); 1655 drm_crtc_wait_one_vblank(&dc->base); 1656 1657 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); 1658 seq_printf(s, "%08x\n", value); 1659 1660 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); 1661 1662 unlock: 1663 drm_modeset_unlock(&dc->base.mutex); 1664 return err; 1665 } 1666 1667 static int tegra_dc_show_stats(struct seq_file *s, void *data) 1668 { 1669 struct drm_info_node *node = s->private; 1670 struct tegra_dc *dc = node->info_ent->data; 1671 1672 seq_printf(s, "frames: %lu\n", dc->stats.frames); 1673 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); 1674 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); 1675 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); 1676 1677 seq_printf(s, "frames total: %lu\n", dc->stats.frames_total); 1678 seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total); 1679 seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total); 1680 seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total); 1681 1682 return 0; 1683 } 1684 1685 static struct drm_info_list debugfs_files[] = { 1686 { "regs", tegra_dc_show_regs, 0, NULL }, 1687 { "crc", tegra_dc_show_crc, 0, NULL }, 1688 { "stats", tegra_dc_show_stats, 0, NULL }, 1689 }; 1690 1691 static int tegra_dc_late_register(struct drm_crtc *crtc) 1692 { 1693 unsigned int i, count = ARRAY_SIZE(debugfs_files); 1694 struct drm_minor *minor = crtc->dev->primary; 1695 struct dentry *root; 1696 struct tegra_dc *dc = to_tegra_dc(crtc); 1697 1698 #ifdef CONFIG_DEBUG_FS 1699 root = crtc->debugfs_entry; 1700 #else 1701 root = NULL; 1702 #endif 1703 1704 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1705 GFP_KERNEL); 1706 if (!dc->debugfs_files) 1707 return -ENOMEM; 1708 1709 for (i = 0; i < count; i++) 1710 dc->debugfs_files[i].data = dc; 1711 1712 drm_debugfs_create_files(dc->debugfs_files, count, root, minor); 1713 1714 return 0; 1715 } 1716 1717 static void tegra_dc_early_unregister(struct drm_crtc *crtc) 1718 { 1719 unsigned int count = ARRAY_SIZE(debugfs_files); 1720 struct drm_minor *minor = crtc->dev->primary; 1721 struct tegra_dc *dc = to_tegra_dc(crtc); 1722 1723 drm_debugfs_remove_files(dc->debugfs_files, count, minor); 1724 kfree(dc->debugfs_files); 1725 dc->debugfs_files = NULL; 1726 } 1727 1728 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc) 1729 { 1730 struct tegra_dc *dc = to_tegra_dc(crtc); 1731 1732 /* XXX vblank syncpoints don't work with nvdisplay yet */ 1733 if (dc->syncpt && !dc->soc->has_nvdisplay) 1734 return host1x_syncpt_read(dc->syncpt); 1735 1736 /* fallback to software emulated VBLANK counter */ 1737 return (u32)drm_crtc_vblank_count(&dc->base); 1738 } 1739 1740 static int tegra_dc_enable_vblank(struct drm_crtc *crtc) 1741 { 1742 struct tegra_dc *dc = to_tegra_dc(crtc); 1743 u32 value; 1744 1745 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 1746 value |= VBLANK_INT; 1747 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1748 1749 return 0; 1750 } 1751 1752 static void tegra_dc_disable_vblank(struct drm_crtc *crtc) 1753 { 1754 struct tegra_dc *dc = to_tegra_dc(crtc); 1755 u32 value; 1756 1757 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 1758 value &= ~VBLANK_INT; 1759 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1760 } 1761 1762 static const struct drm_crtc_funcs tegra_crtc_funcs = { 1763 .page_flip = drm_atomic_helper_page_flip, 1764 .set_config = drm_atomic_helper_set_config, 1765 .destroy = tegra_dc_destroy, 1766 .reset = tegra_crtc_reset, 1767 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state, 1768 .atomic_destroy_state = tegra_crtc_atomic_destroy_state, 1769 .late_register = tegra_dc_late_register, 1770 .early_unregister = tegra_dc_early_unregister, 1771 .get_vblank_counter = tegra_dc_get_vblank_counter, 1772 .enable_vblank = tegra_dc_enable_vblank, 1773 .disable_vblank = tegra_dc_disable_vblank, 1774 }; 1775 1776 static int tegra_dc_set_timings(struct tegra_dc *dc, 1777 struct drm_display_mode *mode) 1778 { 1779 unsigned int h_ref_to_sync = 1; 1780 unsigned int v_ref_to_sync = 1; 1781 unsigned long value; 1782 1783 if (!dc->soc->has_nvdisplay) { 1784 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); 1785 1786 value = (v_ref_to_sync << 16) | h_ref_to_sync; 1787 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); 1788 } 1789 1790 value = ((mode->vsync_end - mode->vsync_start) << 16) | 1791 ((mode->hsync_end - mode->hsync_start) << 0); 1792 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); 1793 1794 value = ((mode->vtotal - mode->vsync_end) << 16) | 1795 ((mode->htotal - mode->hsync_end) << 0); 1796 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); 1797 1798 value = ((mode->vsync_start - mode->vdisplay) << 16) | 1799 ((mode->hsync_start - mode->hdisplay) << 0); 1800 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); 1801 1802 value = (mode->vdisplay << 16) | mode->hdisplay; 1803 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); 1804 1805 return 0; 1806 } 1807 1808 /** 1809 * tegra_dc_state_setup_clock - check clock settings and store them in atomic 1810 * state 1811 * @dc: display controller 1812 * @crtc_state: CRTC atomic state 1813 * @clk: parent clock for display controller 1814 * @pclk: pixel clock 1815 * @div: shift clock divider 1816 * 1817 * Returns: 1818 * 0 on success or a negative error-code on failure. 1819 */ 1820 int tegra_dc_state_setup_clock(struct tegra_dc *dc, 1821 struct drm_crtc_state *crtc_state, 1822 struct clk *clk, unsigned long pclk, 1823 unsigned int div) 1824 { 1825 struct tegra_dc_state *state = to_dc_state(crtc_state); 1826 1827 if (!clk_has_parent(dc->clk, clk)) 1828 return -EINVAL; 1829 1830 state->clk = clk; 1831 state->pclk = pclk; 1832 state->div = div; 1833 1834 return 0; 1835 } 1836 1837 static void tegra_dc_commit_state(struct tegra_dc *dc, 1838 struct tegra_dc_state *state) 1839 { 1840 u32 value; 1841 int err; 1842 1843 err = clk_set_parent(dc->clk, state->clk); 1844 if (err < 0) 1845 dev_err(dc->dev, "failed to set parent clock: %d\n", err); 1846 1847 /* 1848 * Outputs may not want to change the parent clock rate. This is only 1849 * relevant to Tegra20 where only a single display PLL is available. 1850 * Since that PLL would typically be used for HDMI, an internal LVDS 1851 * panel would need to be driven by some other clock such as PLL_P 1852 * which is shared with other peripherals. Changing the clock rate 1853 * should therefore be avoided. 1854 */ 1855 if (state->pclk > 0) { 1856 err = clk_set_rate(state->clk, state->pclk); 1857 if (err < 0) 1858 dev_err(dc->dev, 1859 "failed to set clock rate to %lu Hz\n", 1860 state->pclk); 1861 1862 err = clk_set_rate(dc->clk, state->pclk); 1863 if (err < 0) 1864 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", 1865 dc->clk, state->pclk, err); 1866 } 1867 1868 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), 1869 state->div); 1870 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); 1871 1872 if (!dc->soc->has_nvdisplay) { 1873 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1; 1874 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); 1875 } 1876 } 1877 1878 static void tegra_dc_stop(struct tegra_dc *dc) 1879 { 1880 u32 value; 1881 1882 /* stop the display controller */ 1883 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 1884 value &= ~DISP_CTRL_MODE_MASK; 1885 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 1886 1887 tegra_dc_commit(dc); 1888 } 1889 1890 static bool tegra_dc_idle(struct tegra_dc *dc) 1891 { 1892 u32 value; 1893 1894 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); 1895 1896 return (value & DISP_CTRL_MODE_MASK) == 0; 1897 } 1898 1899 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) 1900 { 1901 timeout = jiffies + msecs_to_jiffies(timeout); 1902 1903 while (time_before(jiffies, timeout)) { 1904 if (tegra_dc_idle(dc)) 1905 return 0; 1906 1907 usleep_range(1000, 2000); 1908 } 1909 1910 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); 1911 return -ETIMEDOUT; 1912 } 1913 1914 static void 1915 tegra_crtc_update_memory_bandwidth(struct drm_crtc *crtc, 1916 struct drm_atomic_state *state, 1917 bool prepare_bandwidth_transition) 1918 { 1919 const struct tegra_plane_state *old_tegra_state, *new_tegra_state; 1920 u32 i, new_avg_bw, old_avg_bw, new_peak_bw, old_peak_bw; 1921 const struct drm_plane_state *old_plane_state; 1922 const struct drm_crtc_state *old_crtc_state; 1923 struct tegra_dc_window window, old_window; 1924 struct tegra_dc *dc = to_tegra_dc(crtc); 1925 struct tegra_plane *tegra; 1926 struct drm_plane *plane; 1927 1928 if (dc->soc->has_nvdisplay) 1929 return; 1930 1931 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); 1932 1933 if (!crtc->state->active) { 1934 if (!old_crtc_state->active) 1935 return; 1936 1937 /* 1938 * When CRTC is disabled on DPMS, the state of attached planes 1939 * is kept unchanged. Hence we need to enforce removal of the 1940 * bandwidths from the ICC paths. 1941 */ 1942 drm_atomic_crtc_for_each_plane(plane, crtc) { 1943 tegra = to_tegra_plane(plane); 1944 1945 icc_set_bw(tegra->icc_mem, 0, 0); 1946 icc_set_bw(tegra->icc_mem_vfilter, 0, 0); 1947 } 1948 1949 return; 1950 } 1951 1952 for_each_old_plane_in_state(old_crtc_state->state, plane, 1953 old_plane_state, i) { 1954 old_tegra_state = to_const_tegra_plane_state(old_plane_state); 1955 new_tegra_state = to_const_tegra_plane_state(plane->state); 1956 tegra = to_tegra_plane(plane); 1957 1958 /* 1959 * We're iterating over the global atomic state and it contains 1960 * planes from another CRTC, hence we need to filter out the 1961 * planes unrelated to this CRTC. 1962 */ 1963 if (tegra->dc != dc) 1964 continue; 1965 1966 new_avg_bw = new_tegra_state->avg_memory_bandwidth; 1967 old_avg_bw = old_tegra_state->avg_memory_bandwidth; 1968 1969 new_peak_bw = new_tegra_state->total_peak_memory_bandwidth; 1970 old_peak_bw = old_tegra_state->total_peak_memory_bandwidth; 1971 1972 /* 1973 * See the comment related to !crtc->state->active above, 1974 * which explains why bandwidths need to be updated when 1975 * CRTC is turning ON. 1976 */ 1977 if (new_avg_bw == old_avg_bw && new_peak_bw == old_peak_bw && 1978 old_crtc_state->active) 1979 continue; 1980 1981 window.src.h = drm_rect_height(&plane->state->src) >> 16; 1982 window.dst.h = drm_rect_height(&plane->state->dst); 1983 1984 old_window.src.h = drm_rect_height(&old_plane_state->src) >> 16; 1985 old_window.dst.h = drm_rect_height(&old_plane_state->dst); 1986 1987 /* 1988 * During the preparation phase (atomic_begin), the memory 1989 * freq should go high before the DC changes are committed 1990 * if bandwidth requirement goes up, otherwise memory freq 1991 * should to stay high if BW requirement goes down. The 1992 * opposite applies to the completion phase (post_commit). 1993 */ 1994 if (prepare_bandwidth_transition) { 1995 new_avg_bw = max(old_avg_bw, new_avg_bw); 1996 new_peak_bw = max(old_peak_bw, new_peak_bw); 1997 1998 if (tegra_plane_use_vertical_filtering(tegra, &old_window)) 1999 window = old_window; 2000 } 2001 2002 icc_set_bw(tegra->icc_mem, new_avg_bw, new_peak_bw); 2003 2004 if (tegra_plane_use_vertical_filtering(tegra, &window)) 2005 icc_set_bw(tegra->icc_mem_vfilter, new_avg_bw, new_peak_bw); 2006 else 2007 icc_set_bw(tegra->icc_mem_vfilter, 0, 0); 2008 } 2009 } 2010 2011 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, 2012 struct drm_atomic_state *state) 2013 { 2014 struct tegra_dc *dc = to_tegra_dc(crtc); 2015 u32 value; 2016 int err; 2017 2018 if (!tegra_dc_idle(dc)) { 2019 tegra_dc_stop(dc); 2020 2021 /* 2022 * Ignore the return value, there isn't anything useful to do 2023 * in case this fails. 2024 */ 2025 tegra_dc_wait_idle(dc, 100); 2026 } 2027 2028 /* 2029 * This should really be part of the RGB encoder driver, but clearing 2030 * these bits has the side-effect of stopping the display controller. 2031 * When that happens no VBLANK interrupts will be raised. At the same 2032 * time the encoder is disabled before the display controller, so the 2033 * above code is always going to timeout waiting for the controller 2034 * to go idle. 2035 * 2036 * Given the close coupling between the RGB encoder and the display 2037 * controller doing it here is still kind of okay. None of the other 2038 * encoder drivers require these bits to be cleared. 2039 * 2040 * XXX: Perhaps given that the display controller is switched off at 2041 * this point anyway maybe clearing these bits isn't even useful for 2042 * the RGB encoder? 2043 */ 2044 if (dc->rgb) { 2045 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 2046 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 2047 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); 2048 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 2049 } 2050 2051 tegra_dc_stats_reset(&dc->stats); 2052 drm_crtc_vblank_off(crtc); 2053 2054 spin_lock_irq(&crtc->dev->event_lock); 2055 2056 if (crtc->state->event) { 2057 drm_crtc_send_vblank_event(crtc, crtc->state->event); 2058 crtc->state->event = NULL; 2059 } 2060 2061 spin_unlock_irq(&crtc->dev->event_lock); 2062 2063 err = host1x_client_suspend(&dc->client); 2064 if (err < 0) 2065 dev_err(dc->dev, "failed to suspend: %d\n", err); 2066 } 2067 2068 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, 2069 struct drm_atomic_state *state) 2070 { 2071 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 2072 struct tegra_dc_state *crtc_state = to_dc_state(crtc->state); 2073 struct tegra_dc *dc = to_tegra_dc(crtc); 2074 u32 value; 2075 int err; 2076 2077 err = host1x_client_resume(&dc->client); 2078 if (err < 0) { 2079 dev_err(dc->dev, "failed to resume: %d\n", err); 2080 return; 2081 } 2082 2083 /* initialize display controller */ 2084 if (dc->syncpt) { 2085 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; 2086 2087 if (dc->soc->has_nvdisplay) 2088 enable = 1 << 31; 2089 else 2090 enable = 1 << 8; 2091 2092 value = SYNCPT_CNTRL_NO_STALL; 2093 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); 2094 2095 value = enable | syncpt; 2096 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); 2097 } 2098 2099 if (dc->soc->has_nvdisplay) { 2100 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT | 2101 DSC_OBUF_UF_INT; 2102 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 2103 2104 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT | 2105 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT | 2106 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT | 2107 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT | 2108 VBLANK_INT | FRAME_END_INT; 2109 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 2110 2111 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT | 2112 FRAME_END_INT; 2113 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 2114 2115 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT; 2116 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 2117 2118 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 2119 } else { 2120 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 2121 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 2122 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 2123 2124 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 2125 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 2126 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 2127 2128 /* initialize timer */ 2129 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | 2130 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); 2131 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); 2132 2133 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | 2134 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); 2135 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); 2136 2137 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 2138 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 2139 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 2140 2141 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 2142 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 2143 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 2144 } 2145 2146 if (dc->soc->supports_background_color) 2147 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR); 2148 else 2149 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); 2150 2151 /* apply PLL and pixel clock changes */ 2152 tegra_dc_commit_state(dc, crtc_state); 2153 2154 /* program display mode */ 2155 tegra_dc_set_timings(dc, mode); 2156 2157 /* interlacing isn't supported yet, so disable it */ 2158 if (dc->soc->supports_interlacing) { 2159 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); 2160 value &= ~INTERLACE_ENABLE; 2161 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); 2162 } 2163 2164 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 2165 value &= ~DISP_CTRL_MODE_MASK; 2166 value |= DISP_CTRL_MODE_C_DISPLAY; 2167 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 2168 2169 if (!dc->soc->has_nvdisplay) { 2170 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 2171 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 2172 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; 2173 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 2174 } 2175 2176 /* enable underflow reporting and display red for missing pixels */ 2177 if (dc->soc->has_nvdisplay) { 2178 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE; 2179 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW); 2180 } 2181 2182 tegra_dc_commit(dc); 2183 2184 drm_crtc_vblank_on(crtc); 2185 } 2186 2187 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, 2188 struct drm_atomic_state *state) 2189 { 2190 unsigned long flags; 2191 2192 tegra_crtc_update_memory_bandwidth(crtc, state, true); 2193 2194 if (crtc->state->event) { 2195 spin_lock_irqsave(&crtc->dev->event_lock, flags); 2196 2197 if (drm_crtc_vblank_get(crtc) != 0) 2198 drm_crtc_send_vblank_event(crtc, crtc->state->event); 2199 else 2200 drm_crtc_arm_vblank_event(crtc, crtc->state->event); 2201 2202 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 2203 2204 crtc->state->event = NULL; 2205 } 2206 } 2207 2208 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, 2209 struct drm_atomic_state *state) 2210 { 2211 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 2212 crtc); 2213 struct tegra_dc_state *dc_state = to_dc_state(crtc_state); 2214 struct tegra_dc *dc = to_tegra_dc(crtc); 2215 u32 value; 2216 2217 value = dc_state->planes << 8 | GENERAL_UPDATE; 2218 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 2219 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 2220 2221 value = dc_state->planes | GENERAL_ACT_REQ; 2222 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 2223 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 2224 } 2225 2226 static bool tegra_plane_is_cursor(const struct drm_plane_state *state) 2227 { 2228 const struct tegra_dc_soc_info *soc = to_tegra_dc(state->crtc)->soc; 2229 const struct drm_format_info *fmt = state->fb->format; 2230 unsigned int src_w = drm_rect_width(&state->src) >> 16; 2231 unsigned int dst_w = drm_rect_width(&state->dst); 2232 2233 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) 2234 return false; 2235 2236 if (soc->supports_cursor) 2237 return true; 2238 2239 if (src_w != dst_w || fmt->num_planes != 1 || src_w * fmt->cpp[0] > 256) 2240 return false; 2241 2242 return true; 2243 } 2244 2245 static unsigned long 2246 tegra_plane_overlap_mask(struct drm_crtc_state *state, 2247 const struct drm_plane_state *plane_state) 2248 { 2249 const struct drm_plane_state *other_state; 2250 const struct tegra_plane *tegra; 2251 unsigned long overlap_mask = 0; 2252 struct drm_plane *plane; 2253 struct drm_rect rect; 2254 2255 if (!plane_state->visible || !plane_state->fb) 2256 return 0; 2257 2258 /* 2259 * Data-prefetch FIFO will easily help to overcome temporal memory 2260 * pressure if other plane overlaps with the cursor plane. 2261 */ 2262 if (tegra_plane_is_cursor(plane_state)) 2263 return 0; 2264 2265 drm_atomic_crtc_state_for_each_plane_state(plane, other_state, state) { 2266 rect = plane_state->dst; 2267 2268 tegra = to_tegra_plane(other_state->plane); 2269 2270 if (!other_state->visible || !other_state->fb) 2271 continue; 2272 2273 /* 2274 * Ignore cursor plane overlaps because it's not practical to 2275 * assume that it contributes to the bandwidth in overlapping 2276 * area if window width is small. 2277 */ 2278 if (tegra_plane_is_cursor(other_state)) 2279 continue; 2280 2281 if (drm_rect_intersect(&rect, &other_state->dst)) 2282 overlap_mask |= BIT(tegra->index); 2283 } 2284 2285 return overlap_mask; 2286 } 2287 2288 static int tegra_crtc_calculate_memory_bandwidth(struct drm_crtc *crtc, 2289 struct drm_atomic_state *state) 2290 { 2291 ulong overlap_mask[TEGRA_DC_LEGACY_PLANES_NUM] = {}, mask; 2292 u32 plane_peak_bw[TEGRA_DC_LEGACY_PLANES_NUM] = {}; 2293 bool all_planes_overlap_simultaneously = true; 2294 const struct tegra_plane_state *tegra_state; 2295 const struct drm_plane_state *plane_state; 2296 struct tegra_dc *dc = to_tegra_dc(crtc); 2297 const struct drm_crtc_state *old_state; 2298 struct drm_crtc_state *new_state; 2299 struct tegra_plane *tegra; 2300 struct drm_plane *plane; 2301 2302 /* 2303 * The nv-display uses shared planes. The algorithm below assumes 2304 * maximum 3 planes per-CRTC, this assumption isn't applicable to 2305 * the nv-display. Note that T124 support has additional windows, 2306 * but currently they aren't supported by the driver. 2307 */ 2308 if (dc->soc->has_nvdisplay) 2309 return 0; 2310 2311 new_state = drm_atomic_get_new_crtc_state(state, crtc); 2312 old_state = drm_atomic_get_old_crtc_state(state, crtc); 2313 2314 /* 2315 * For overlapping planes pixel's data is fetched for each plane at 2316 * the same time, hence bandwidths are accumulated in this case. 2317 * This needs to be taken into account for calculating total bandwidth 2318 * consumed by all planes. 2319 * 2320 * Here we get the overlapping state of each plane, which is a 2321 * bitmask of plane indices telling with what planes there is an 2322 * overlap. Note that bitmask[plane] includes BIT(plane) in order 2323 * to make further code nicer and simpler. 2324 */ 2325 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) { 2326 tegra_state = to_const_tegra_plane_state(plane_state); 2327 tegra = to_tegra_plane(plane); 2328 2329 if (WARN_ON_ONCE(tegra->index >= TEGRA_DC_LEGACY_PLANES_NUM)) 2330 return -EINVAL; 2331 2332 plane_peak_bw[tegra->index] = tegra_state->peak_memory_bandwidth; 2333 mask = tegra_plane_overlap_mask(new_state, plane_state); 2334 overlap_mask[tegra->index] = mask; 2335 2336 if (hweight_long(mask) != 3) 2337 all_planes_overlap_simultaneously = false; 2338 } 2339 2340 /* 2341 * Then we calculate maximum bandwidth of each plane state. 2342 * The bandwidth includes the plane BW + BW of the "simultaneously" 2343 * overlapping planes, where "simultaneously" means areas where DC 2344 * fetches from the planes simultaneously during of scan-out process. 2345 * 2346 * For example, if plane A overlaps with planes B and C, but B and C 2347 * don't overlap, then the peak bandwidth will be either in area where 2348 * A-and-B or A-and-C planes overlap. 2349 * 2350 * The plane_peak_bw[] contains peak memory bandwidth values of 2351 * each plane, this information is needed by interconnect provider 2352 * in order to set up latency allowance based on the peak BW, see 2353 * tegra_crtc_update_memory_bandwidth(). 2354 */ 2355 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) { 2356 u32 i, old_peak_bw, new_peak_bw, overlap_bw = 0; 2357 2358 /* 2359 * Note that plane's atomic check doesn't touch the 2360 * total_peak_memory_bandwidth of enabled plane, hence the 2361 * current state contains the old bandwidth state from the 2362 * previous CRTC commit. 2363 */ 2364 tegra_state = to_const_tegra_plane_state(plane_state); 2365 tegra = to_tegra_plane(plane); 2366 2367 for_each_set_bit(i, &overlap_mask[tegra->index], 3) { 2368 if (i == tegra->index) 2369 continue; 2370 2371 if (all_planes_overlap_simultaneously) 2372 overlap_bw += plane_peak_bw[i]; 2373 else 2374 overlap_bw = max(overlap_bw, plane_peak_bw[i]); 2375 } 2376 2377 new_peak_bw = plane_peak_bw[tegra->index] + overlap_bw; 2378 old_peak_bw = tegra_state->total_peak_memory_bandwidth; 2379 2380 /* 2381 * If plane's peak bandwidth changed (for example plane isn't 2382 * overlapped anymore) and plane isn't in the atomic state, 2383 * then add plane to the state in order to have the bandwidth 2384 * updated. 2385 */ 2386 if (old_peak_bw != new_peak_bw) { 2387 struct tegra_plane_state *new_tegra_state; 2388 struct drm_plane_state *new_plane_state; 2389 2390 new_plane_state = drm_atomic_get_plane_state(state, plane); 2391 if (IS_ERR(new_plane_state)) 2392 return PTR_ERR(new_plane_state); 2393 2394 new_tegra_state = to_tegra_plane_state(new_plane_state); 2395 new_tegra_state->total_peak_memory_bandwidth = new_peak_bw; 2396 } 2397 } 2398 2399 return 0; 2400 } 2401 2402 static int tegra_crtc_atomic_check(struct drm_crtc *crtc, 2403 struct drm_atomic_state *state) 2404 { 2405 int err; 2406 2407 err = tegra_crtc_calculate_memory_bandwidth(crtc, state); 2408 if (err) 2409 return err; 2410 2411 return 0; 2412 } 2413 2414 void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc, 2415 struct drm_atomic_state *state) 2416 { 2417 /* 2418 * Display bandwidth is allowed to go down only once hardware state 2419 * is known to be armed, i.e. state was committed and VBLANK event 2420 * received. 2421 */ 2422 tegra_crtc_update_memory_bandwidth(crtc, state, false); 2423 } 2424 2425 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { 2426 .atomic_check = tegra_crtc_atomic_check, 2427 .atomic_begin = tegra_crtc_atomic_begin, 2428 .atomic_flush = tegra_crtc_atomic_flush, 2429 .atomic_enable = tegra_crtc_atomic_enable, 2430 .atomic_disable = tegra_crtc_atomic_disable, 2431 }; 2432 2433 static irqreturn_t tegra_dc_irq(int irq, void *data) 2434 { 2435 struct tegra_dc *dc = data; 2436 unsigned long status; 2437 2438 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); 2439 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); 2440 2441 if (status & FRAME_END_INT) { 2442 /* 2443 dev_dbg(dc->dev, "%s(): frame end\n", __func__); 2444 */ 2445 dc->stats.frames_total++; 2446 dc->stats.frames++; 2447 } 2448 2449 if (status & VBLANK_INT) { 2450 /* 2451 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); 2452 */ 2453 drm_crtc_handle_vblank(&dc->base); 2454 dc->stats.vblank_total++; 2455 dc->stats.vblank++; 2456 } 2457 2458 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { 2459 /* 2460 dev_dbg(dc->dev, "%s(): underflow\n", __func__); 2461 */ 2462 dc->stats.underflow_total++; 2463 dc->stats.underflow++; 2464 } 2465 2466 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) { 2467 /* 2468 dev_dbg(dc->dev, "%s(): overflow\n", __func__); 2469 */ 2470 dc->stats.overflow_total++; 2471 dc->stats.overflow++; 2472 } 2473 2474 if (status & HEAD_UF_INT) { 2475 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); 2476 dc->stats.underflow_total++; 2477 dc->stats.underflow++; 2478 } 2479 2480 return IRQ_HANDLED; 2481 } 2482 2483 static bool tegra_dc_has_window_groups(struct tegra_dc *dc) 2484 { 2485 unsigned int i; 2486 2487 if (!dc->soc->wgrps) 2488 return true; 2489 2490 for (i = 0; i < dc->soc->num_wgrps; i++) { 2491 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; 2492 2493 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) 2494 return true; 2495 } 2496 2497 return false; 2498 } 2499 2500 static int tegra_dc_early_init(struct host1x_client *client) 2501 { 2502 struct drm_device *drm = dev_get_drvdata(client->host); 2503 struct tegra_drm *tegra = drm->dev_private; 2504 2505 tegra->num_crtcs++; 2506 2507 return 0; 2508 } 2509 2510 static int tegra_dc_init(struct host1x_client *client) 2511 { 2512 struct drm_device *drm = dev_get_drvdata(client->host); 2513 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED; 2514 struct tegra_dc *dc = host1x_client_to_dc(client); 2515 struct tegra_drm *tegra = drm->dev_private; 2516 struct drm_plane *primary = NULL; 2517 struct drm_plane *cursor = NULL; 2518 int err; 2519 2520 /* 2521 * DC has been reset by now, so VBLANK syncpoint can be released 2522 * for general use. 2523 */ 2524 host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe); 2525 2526 /* 2527 * XXX do not register DCs with no window groups because we cannot 2528 * assign a primary plane to them, which in turn will cause KMS to 2529 * crash. 2530 */ 2531 if (!tegra_dc_has_window_groups(dc)) 2532 return 0; 2533 2534 /* 2535 * Set the display hub as the host1x client parent for the display 2536 * controller. This is needed for the runtime reference counting that 2537 * ensures the display hub is always powered when any of the display 2538 * controllers are. 2539 */ 2540 if (dc->soc->has_nvdisplay) 2541 client->parent = &tegra->hub->client; 2542 2543 dc->syncpt = host1x_syncpt_request(client, flags); 2544 if (!dc->syncpt) 2545 dev_warn(dc->dev, "failed to allocate syncpoint\n"); 2546 2547 err = host1x_client_iommu_attach(client); 2548 if (err < 0 && err != -ENODEV) { 2549 dev_err(client->dev, "failed to attach to domain: %d\n", err); 2550 return err; 2551 } 2552 2553 if (dc->soc->wgrps) 2554 primary = tegra_dc_add_shared_planes(drm, dc); 2555 else 2556 primary = tegra_dc_add_planes(drm, dc); 2557 2558 if (IS_ERR(primary)) { 2559 err = PTR_ERR(primary); 2560 goto cleanup; 2561 } 2562 2563 if (dc->soc->supports_cursor) { 2564 cursor = tegra_dc_cursor_plane_create(drm, dc); 2565 if (IS_ERR(cursor)) { 2566 err = PTR_ERR(cursor); 2567 goto cleanup; 2568 } 2569 } else { 2570 /* dedicate one overlay to mouse cursor */ 2571 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true); 2572 if (IS_ERR(cursor)) { 2573 err = PTR_ERR(cursor); 2574 goto cleanup; 2575 } 2576 } 2577 2578 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, 2579 &tegra_crtc_funcs, NULL); 2580 if (err < 0) 2581 goto cleanup; 2582 2583 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); 2584 2585 /* 2586 * Keep track of the minimum pitch alignment across all display 2587 * controllers. 2588 */ 2589 if (dc->soc->pitch_align > tegra->pitch_align) 2590 tegra->pitch_align = dc->soc->pitch_align; 2591 2592 /* track maximum resolution */ 2593 if (dc->soc->has_nvdisplay) 2594 drm->mode_config.max_width = drm->mode_config.max_height = 16384; 2595 else 2596 drm->mode_config.max_width = drm->mode_config.max_height = 4096; 2597 2598 err = tegra_dc_rgb_init(drm, dc); 2599 if (err < 0 && err != -ENODEV) { 2600 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); 2601 goto cleanup; 2602 } 2603 2604 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, 2605 dev_name(dc->dev), dc); 2606 if (err < 0) { 2607 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, 2608 err); 2609 goto cleanup; 2610 } 2611 2612 /* 2613 * Inherit the DMA parameters (such as maximum segment size) from the 2614 * parent host1x device. 2615 */ 2616 client->dev->dma_parms = client->host->dma_parms; 2617 2618 return 0; 2619 2620 cleanup: 2621 if (!IS_ERR_OR_NULL(cursor)) 2622 drm_plane_cleanup(cursor); 2623 2624 if (!IS_ERR(primary)) 2625 drm_plane_cleanup(primary); 2626 2627 host1x_client_iommu_detach(client); 2628 host1x_syncpt_put(dc->syncpt); 2629 2630 return err; 2631 } 2632 2633 static int tegra_dc_exit(struct host1x_client *client) 2634 { 2635 struct tegra_dc *dc = host1x_client_to_dc(client); 2636 int err; 2637 2638 if (!tegra_dc_has_window_groups(dc)) 2639 return 0; 2640 2641 /* avoid a dangling pointer just in case this disappears */ 2642 client->dev->dma_parms = NULL; 2643 2644 devm_free_irq(dc->dev, dc->irq, dc); 2645 2646 err = tegra_dc_rgb_exit(dc); 2647 if (err) { 2648 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); 2649 return err; 2650 } 2651 2652 host1x_client_iommu_detach(client); 2653 host1x_syncpt_put(dc->syncpt); 2654 2655 return 0; 2656 } 2657 2658 static int tegra_dc_late_exit(struct host1x_client *client) 2659 { 2660 struct drm_device *drm = dev_get_drvdata(client->host); 2661 struct tegra_drm *tegra = drm->dev_private; 2662 2663 tegra->num_crtcs--; 2664 2665 return 0; 2666 } 2667 2668 static int tegra_dc_runtime_suspend(struct host1x_client *client) 2669 { 2670 struct tegra_dc *dc = host1x_client_to_dc(client); 2671 struct device *dev = client->dev; 2672 int err; 2673 2674 err = reset_control_assert(dc->rst); 2675 if (err < 0) { 2676 dev_err(dev, "failed to assert reset: %d\n", err); 2677 return err; 2678 } 2679 2680 if (dc->soc->has_powergate) 2681 tegra_powergate_power_off(dc->powergate); 2682 2683 clk_disable_unprepare(dc->clk); 2684 pm_runtime_put_sync(dev); 2685 2686 return 0; 2687 } 2688 2689 static int tegra_dc_runtime_resume(struct host1x_client *client) 2690 { 2691 struct tegra_dc *dc = host1x_client_to_dc(client); 2692 struct device *dev = client->dev; 2693 int err; 2694 2695 err = pm_runtime_resume_and_get(dev); 2696 if (err < 0) { 2697 dev_err(dev, "failed to get runtime PM: %d\n", err); 2698 return err; 2699 } 2700 2701 if (dc->soc->has_powergate) { 2702 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, 2703 dc->rst); 2704 if (err < 0) { 2705 dev_err(dev, "failed to power partition: %d\n", err); 2706 goto put_rpm; 2707 } 2708 } else { 2709 err = clk_prepare_enable(dc->clk); 2710 if (err < 0) { 2711 dev_err(dev, "failed to enable clock: %d\n", err); 2712 goto put_rpm; 2713 } 2714 2715 err = reset_control_deassert(dc->rst); 2716 if (err < 0) { 2717 dev_err(dev, "failed to deassert reset: %d\n", err); 2718 goto disable_clk; 2719 } 2720 } 2721 2722 return 0; 2723 2724 disable_clk: 2725 clk_disable_unprepare(dc->clk); 2726 put_rpm: 2727 pm_runtime_put_sync(dev); 2728 return err; 2729 } 2730 2731 static const struct host1x_client_ops dc_client_ops = { 2732 .early_init = tegra_dc_early_init, 2733 .init = tegra_dc_init, 2734 .exit = tegra_dc_exit, 2735 .late_exit = tegra_dc_late_exit, 2736 .suspend = tegra_dc_runtime_suspend, 2737 .resume = tegra_dc_runtime_resume, 2738 }; 2739 2740 static const struct tegra_dc_soc_info tegra20_dc_soc_info = { 2741 .supports_background_color = false, 2742 .supports_interlacing = false, 2743 .supports_cursor = false, 2744 .supports_block_linear = false, 2745 .supports_sector_layout = false, 2746 .has_legacy_blending = true, 2747 .pitch_align = 8, 2748 .has_powergate = false, 2749 .coupled_pm = true, 2750 .has_nvdisplay = false, 2751 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 2752 .primary_formats = tegra20_primary_formats, 2753 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 2754 .overlay_formats = tegra20_overlay_formats, 2755 .modifiers = tegra20_modifiers, 2756 .has_win_a_without_filters = true, 2757 .has_win_b_vfilter_mem_client = true, 2758 .has_win_c_without_vert_filter = true, 2759 .plane_tiled_memory_bandwidth_x2 = false, 2760 }; 2761 2762 static const struct tegra_dc_soc_info tegra30_dc_soc_info = { 2763 .supports_background_color = false, 2764 .supports_interlacing = false, 2765 .supports_cursor = false, 2766 .supports_block_linear = false, 2767 .supports_sector_layout = false, 2768 .has_legacy_blending = true, 2769 .pitch_align = 8, 2770 .has_powergate = false, 2771 .coupled_pm = false, 2772 .has_nvdisplay = false, 2773 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 2774 .primary_formats = tegra20_primary_formats, 2775 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 2776 .overlay_formats = tegra20_overlay_formats, 2777 .modifiers = tegra20_modifiers, 2778 .has_win_a_without_filters = false, 2779 .has_win_b_vfilter_mem_client = true, 2780 .has_win_c_without_vert_filter = false, 2781 .plane_tiled_memory_bandwidth_x2 = true, 2782 }; 2783 2784 static const struct tegra_dc_soc_info tegra114_dc_soc_info = { 2785 .supports_background_color = false, 2786 .supports_interlacing = false, 2787 .supports_cursor = false, 2788 .supports_block_linear = false, 2789 .supports_sector_layout = false, 2790 .has_legacy_blending = true, 2791 .pitch_align = 64, 2792 .has_powergate = true, 2793 .coupled_pm = false, 2794 .has_nvdisplay = false, 2795 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 2796 .primary_formats = tegra114_primary_formats, 2797 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 2798 .overlay_formats = tegra114_overlay_formats, 2799 .modifiers = tegra20_modifiers, 2800 .has_win_a_without_filters = false, 2801 .has_win_b_vfilter_mem_client = false, 2802 .has_win_c_without_vert_filter = false, 2803 .plane_tiled_memory_bandwidth_x2 = true, 2804 }; 2805 2806 static const struct tegra_dc_soc_info tegra124_dc_soc_info = { 2807 .supports_background_color = true, 2808 .supports_interlacing = true, 2809 .supports_cursor = true, 2810 .supports_block_linear = true, 2811 .supports_sector_layout = false, 2812 .has_legacy_blending = false, 2813 .pitch_align = 64, 2814 .has_powergate = true, 2815 .coupled_pm = false, 2816 .has_nvdisplay = false, 2817 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats), 2818 .primary_formats = tegra124_primary_formats, 2819 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats), 2820 .overlay_formats = tegra124_overlay_formats, 2821 .modifiers = tegra124_modifiers, 2822 .has_win_a_without_filters = false, 2823 .has_win_b_vfilter_mem_client = false, 2824 .has_win_c_without_vert_filter = false, 2825 .plane_tiled_memory_bandwidth_x2 = false, 2826 }; 2827 2828 static const struct tegra_dc_soc_info tegra210_dc_soc_info = { 2829 .supports_background_color = true, 2830 .supports_interlacing = true, 2831 .supports_cursor = true, 2832 .supports_block_linear = true, 2833 .supports_sector_layout = false, 2834 .has_legacy_blending = false, 2835 .pitch_align = 64, 2836 .has_powergate = true, 2837 .coupled_pm = false, 2838 .has_nvdisplay = false, 2839 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 2840 .primary_formats = tegra114_primary_formats, 2841 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 2842 .overlay_formats = tegra114_overlay_formats, 2843 .modifiers = tegra124_modifiers, 2844 .has_win_a_without_filters = false, 2845 .has_win_b_vfilter_mem_client = false, 2846 .has_win_c_without_vert_filter = false, 2847 .plane_tiled_memory_bandwidth_x2 = false, 2848 }; 2849 2850 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = { 2851 { 2852 .index = 0, 2853 .dc = 0, 2854 .windows = (const unsigned int[]) { 0 }, 2855 .num_windows = 1, 2856 }, { 2857 .index = 1, 2858 .dc = 1, 2859 .windows = (const unsigned int[]) { 1 }, 2860 .num_windows = 1, 2861 }, { 2862 .index = 2, 2863 .dc = 1, 2864 .windows = (const unsigned int[]) { 2 }, 2865 .num_windows = 1, 2866 }, { 2867 .index = 3, 2868 .dc = 2, 2869 .windows = (const unsigned int[]) { 3 }, 2870 .num_windows = 1, 2871 }, { 2872 .index = 4, 2873 .dc = 2, 2874 .windows = (const unsigned int[]) { 4 }, 2875 .num_windows = 1, 2876 }, { 2877 .index = 5, 2878 .dc = 2, 2879 .windows = (const unsigned int[]) { 5 }, 2880 .num_windows = 1, 2881 }, 2882 }; 2883 2884 static const struct tegra_dc_soc_info tegra186_dc_soc_info = { 2885 .supports_background_color = true, 2886 .supports_interlacing = true, 2887 .supports_cursor = true, 2888 .supports_block_linear = true, 2889 .supports_sector_layout = false, 2890 .has_legacy_blending = false, 2891 .pitch_align = 64, 2892 .has_powergate = false, 2893 .coupled_pm = false, 2894 .has_nvdisplay = true, 2895 .wgrps = tegra186_dc_wgrps, 2896 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), 2897 .plane_tiled_memory_bandwidth_x2 = false, 2898 }; 2899 2900 static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = { 2901 { 2902 .index = 0, 2903 .dc = 0, 2904 .windows = (const unsigned int[]) { 0 }, 2905 .num_windows = 1, 2906 }, { 2907 .index = 1, 2908 .dc = 1, 2909 .windows = (const unsigned int[]) { 1 }, 2910 .num_windows = 1, 2911 }, { 2912 .index = 2, 2913 .dc = 1, 2914 .windows = (const unsigned int[]) { 2 }, 2915 .num_windows = 1, 2916 }, { 2917 .index = 3, 2918 .dc = 2, 2919 .windows = (const unsigned int[]) { 3 }, 2920 .num_windows = 1, 2921 }, { 2922 .index = 4, 2923 .dc = 2, 2924 .windows = (const unsigned int[]) { 4 }, 2925 .num_windows = 1, 2926 }, { 2927 .index = 5, 2928 .dc = 2, 2929 .windows = (const unsigned int[]) { 5 }, 2930 .num_windows = 1, 2931 }, 2932 }; 2933 2934 static const struct tegra_dc_soc_info tegra194_dc_soc_info = { 2935 .supports_background_color = true, 2936 .supports_interlacing = true, 2937 .supports_cursor = true, 2938 .supports_block_linear = true, 2939 .supports_sector_layout = true, 2940 .has_legacy_blending = false, 2941 .pitch_align = 64, 2942 .has_powergate = false, 2943 .coupled_pm = false, 2944 .has_nvdisplay = true, 2945 .wgrps = tegra194_dc_wgrps, 2946 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps), 2947 .plane_tiled_memory_bandwidth_x2 = false, 2948 }; 2949 2950 static const struct of_device_id tegra_dc_of_match[] = { 2951 { 2952 .compatible = "nvidia,tegra194-dc", 2953 .data = &tegra194_dc_soc_info, 2954 }, { 2955 .compatible = "nvidia,tegra186-dc", 2956 .data = &tegra186_dc_soc_info, 2957 }, { 2958 .compatible = "nvidia,tegra210-dc", 2959 .data = &tegra210_dc_soc_info, 2960 }, { 2961 .compatible = "nvidia,tegra124-dc", 2962 .data = &tegra124_dc_soc_info, 2963 }, { 2964 .compatible = "nvidia,tegra114-dc", 2965 .data = &tegra114_dc_soc_info, 2966 }, { 2967 .compatible = "nvidia,tegra30-dc", 2968 .data = &tegra30_dc_soc_info, 2969 }, { 2970 .compatible = "nvidia,tegra20-dc", 2971 .data = &tegra20_dc_soc_info, 2972 }, { 2973 /* sentinel */ 2974 } 2975 }; 2976 MODULE_DEVICE_TABLE(of, tegra_dc_of_match); 2977 2978 static int tegra_dc_parse_dt(struct tegra_dc *dc) 2979 { 2980 struct device_node *np; 2981 u32 value = 0; 2982 int err; 2983 2984 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); 2985 if (err < 0) { 2986 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); 2987 2988 /* 2989 * If the nvidia,head property isn't present, try to find the 2990 * correct head number by looking up the position of this 2991 * display controller's node within the device tree. Assuming 2992 * that the nodes are ordered properly in the DTS file and 2993 * that the translation into a flattened device tree blob 2994 * preserves that ordering this will actually yield the right 2995 * head number. 2996 * 2997 * If those assumptions don't hold, this will still work for 2998 * cases where only a single display controller is used. 2999 */ 3000 for_each_matching_node(np, tegra_dc_of_match) { 3001 if (np == dc->dev->of_node) { 3002 of_node_put(np); 3003 break; 3004 } 3005 3006 value++; 3007 } 3008 } 3009 3010 dc->pipe = value; 3011 3012 return 0; 3013 } 3014 3015 static int tegra_dc_match_by_pipe(struct device *dev, const void *data) 3016 { 3017 struct tegra_dc *dc = dev_get_drvdata(dev); 3018 unsigned int pipe = (unsigned long)(void *)data; 3019 3020 return dc->pipe == pipe; 3021 } 3022 3023 static int tegra_dc_couple(struct tegra_dc *dc) 3024 { 3025 /* 3026 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to 3027 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND / 3028 * POWER_CONTROL registers during CRTC enabling. 3029 */ 3030 if (dc->soc->coupled_pm && dc->pipe == 1) { 3031 struct device *companion; 3032 struct tegra_dc *parent; 3033 3034 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0, 3035 tegra_dc_match_by_pipe); 3036 if (!companion) 3037 return -EPROBE_DEFER; 3038 3039 parent = dev_get_drvdata(companion); 3040 dc->client.parent = &parent->client; 3041 3042 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion)); 3043 } 3044 3045 return 0; 3046 } 3047 3048 static int tegra_dc_probe(struct platform_device *pdev) 3049 { 3050 u64 dma_mask = dma_get_mask(pdev->dev.parent); 3051 struct tegra_dc *dc; 3052 int err; 3053 3054 err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask); 3055 if (err < 0) { 3056 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 3057 return err; 3058 } 3059 3060 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); 3061 if (!dc) 3062 return -ENOMEM; 3063 3064 dc->soc = of_device_get_match_data(&pdev->dev); 3065 3066 INIT_LIST_HEAD(&dc->list); 3067 dc->dev = &pdev->dev; 3068 3069 err = tegra_dc_parse_dt(dc); 3070 if (err < 0) 3071 return err; 3072 3073 err = tegra_dc_couple(dc); 3074 if (err < 0) 3075 return err; 3076 3077 dc->clk = devm_clk_get(&pdev->dev, NULL); 3078 if (IS_ERR(dc->clk)) { 3079 dev_err(&pdev->dev, "failed to get clock\n"); 3080 return PTR_ERR(dc->clk); 3081 } 3082 3083 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); 3084 if (IS_ERR(dc->rst)) { 3085 dev_err(&pdev->dev, "failed to get reset\n"); 3086 return PTR_ERR(dc->rst); 3087 } 3088 3089 /* assert reset and disable clock */ 3090 err = clk_prepare_enable(dc->clk); 3091 if (err < 0) 3092 return err; 3093 3094 usleep_range(2000, 4000); 3095 3096 err = reset_control_assert(dc->rst); 3097 if (err < 0) 3098 return err; 3099 3100 usleep_range(2000, 4000); 3101 3102 clk_disable_unprepare(dc->clk); 3103 3104 if (dc->soc->has_powergate) { 3105 if (dc->pipe == 0) 3106 dc->powergate = TEGRA_POWERGATE_DIS; 3107 else 3108 dc->powergate = TEGRA_POWERGATE_DISB; 3109 3110 tegra_powergate_power_off(dc->powergate); 3111 } 3112 3113 dc->regs = devm_platform_ioremap_resource(pdev, 0); 3114 if (IS_ERR(dc->regs)) 3115 return PTR_ERR(dc->regs); 3116 3117 dc->irq = platform_get_irq(pdev, 0); 3118 if (dc->irq < 0) 3119 return -ENXIO; 3120 3121 err = tegra_dc_rgb_probe(dc); 3122 if (err < 0 && err != -ENODEV) { 3123 const char *level = KERN_ERR; 3124 3125 if (err == -EPROBE_DEFER) 3126 level = KERN_DEBUG; 3127 3128 dev_printk(level, dc->dev, "failed to probe RGB output: %d\n", 3129 err); 3130 return err; 3131 } 3132 3133 platform_set_drvdata(pdev, dc); 3134 pm_runtime_enable(&pdev->dev); 3135 3136 INIT_LIST_HEAD(&dc->client.list); 3137 dc->client.ops = &dc_client_ops; 3138 dc->client.dev = &pdev->dev; 3139 3140 err = host1x_client_register(&dc->client); 3141 if (err < 0) { 3142 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 3143 err); 3144 goto disable_pm; 3145 } 3146 3147 return 0; 3148 3149 disable_pm: 3150 pm_runtime_disable(&pdev->dev); 3151 tegra_dc_rgb_remove(dc); 3152 3153 return err; 3154 } 3155 3156 static int tegra_dc_remove(struct platform_device *pdev) 3157 { 3158 struct tegra_dc *dc = platform_get_drvdata(pdev); 3159 int err; 3160 3161 err = host1x_client_unregister(&dc->client); 3162 if (err < 0) { 3163 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 3164 err); 3165 return err; 3166 } 3167 3168 err = tegra_dc_rgb_remove(dc); 3169 if (err < 0) { 3170 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); 3171 return err; 3172 } 3173 3174 pm_runtime_disable(&pdev->dev); 3175 3176 return 0; 3177 } 3178 3179 struct platform_driver tegra_dc_driver = { 3180 .driver = { 3181 .name = "tegra-dc", 3182 .of_match_table = tegra_dc_of_match, 3183 }, 3184 .probe = tegra_dc_probe, 3185 .remove = tegra_dc_remove, 3186 }; 3187