1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Avionic Design GmbH 4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/debugfs.h> 9 #include <linux/delay.h> 10 #include <linux/iommu.h> 11 #include <linux/interconnect.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/pm_domain.h> 15 #include <linux/pm_opp.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 19 #include <soc/tegra/common.h> 20 #include <soc/tegra/pmc.h> 21 22 #include <drm/drm_atomic.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_debugfs.h> 25 #include <drm/drm_fourcc.h> 26 #include <drm/drm_plane_helper.h> 27 #include <drm/drm_vblank.h> 28 29 #include "dc.h" 30 #include "drm.h" 31 #include "gem.h" 32 #include "hub.h" 33 #include "plane.h" 34 35 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, 36 struct drm_crtc_state *state); 37 38 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats) 39 { 40 stats->frames = 0; 41 stats->vblank = 0; 42 stats->underflow = 0; 43 stats->overflow = 0; 44 } 45 46 /* Reads the active copy of a register. */ 47 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) 48 { 49 u32 value; 50 51 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 52 value = tegra_dc_readl(dc, offset); 53 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); 54 55 return value; 56 } 57 58 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane, 59 unsigned int offset) 60 { 61 if (offset >= 0x500 && offset <= 0x638) { 62 offset = 0x000 + (offset - 0x500); 63 return plane->offset + offset; 64 } 65 66 if (offset >= 0x700 && offset <= 0x719) { 67 offset = 0x180 + (offset - 0x700); 68 return plane->offset + offset; 69 } 70 71 if (offset >= 0x800 && offset <= 0x839) { 72 offset = 0x1c0 + (offset - 0x800); 73 return plane->offset + offset; 74 } 75 76 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); 77 78 return plane->offset + offset; 79 } 80 81 static inline u32 tegra_plane_readl(struct tegra_plane *plane, 82 unsigned int offset) 83 { 84 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); 85 } 86 87 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value, 88 unsigned int offset) 89 { 90 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); 91 } 92 93 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) 94 { 95 struct device_node *np = dc->dev->of_node; 96 struct of_phandle_iterator it; 97 int err; 98 99 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0) 100 if (it.node == dev->of_node) 101 return true; 102 103 return false; 104 } 105 106 /* 107 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the 108 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy. 109 * Latching happens mmediately if the display controller is in STOP mode or 110 * on the next frame boundary otherwise. 111 * 112 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The 113 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits 114 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched 115 * into the ACTIVE copy, either immediately if the display controller is in 116 * STOP mode, or at the next frame boundary otherwise. 117 */ 118 void tegra_dc_commit(struct tegra_dc *dc) 119 { 120 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 121 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 122 } 123 124 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, 125 unsigned int bpp) 126 { 127 fixed20_12 outf = dfixed_init(out); 128 fixed20_12 inf = dfixed_init(in); 129 u32 dda_inc; 130 int max; 131 132 if (v) 133 max = 15; 134 else { 135 switch (bpp) { 136 case 2: 137 max = 8; 138 break; 139 140 default: 141 WARN_ON_ONCE(1); 142 fallthrough; 143 case 4: 144 max = 4; 145 break; 146 } 147 } 148 149 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); 150 inf.full -= dfixed_const(1); 151 152 dda_inc = dfixed_div(inf, outf); 153 dda_inc = min_t(u32, dda_inc, dfixed_const(max)); 154 155 return dda_inc; 156 } 157 158 static inline u32 compute_initial_dda(unsigned int in) 159 { 160 fixed20_12 inf = dfixed_init(in); 161 return dfixed_frac(inf); 162 } 163 164 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane) 165 { 166 u32 background[3] = { 167 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 168 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 169 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 170 }; 171 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) | 172 BLEND_COLOR_KEY_NONE; 173 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255); 174 struct tegra_plane_state *state; 175 u32 blending[2]; 176 unsigned int i; 177 178 /* disable blending for non-overlapping case */ 179 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY); 180 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN); 181 182 state = to_tegra_plane_state(plane->base.state); 183 184 if (state->opaque) { 185 /* 186 * Since custom fix-weight blending isn't utilized and weight 187 * of top window is set to max, we can enforce dependent 188 * blending which in this case results in transparent bottom 189 * window if top window is opaque and if top window enables 190 * alpha blending, then bottom window is getting alpha value 191 * of 1 minus the sum of alpha components of the overlapping 192 * plane. 193 */ 194 background[0] |= BLEND_CONTROL_DEPENDENT; 195 background[1] |= BLEND_CONTROL_DEPENDENT; 196 197 /* 198 * The region where three windows overlap is the intersection 199 * of the two regions where two windows overlap. It contributes 200 * to the area if all of the windows on top of it have an alpha 201 * component. 202 */ 203 switch (state->base.normalized_zpos) { 204 case 0: 205 if (state->blending[0].alpha && 206 state->blending[1].alpha) 207 background[2] |= BLEND_CONTROL_DEPENDENT; 208 break; 209 210 case 1: 211 background[2] |= BLEND_CONTROL_DEPENDENT; 212 break; 213 } 214 } else { 215 /* 216 * Enable alpha blending if pixel format has an alpha 217 * component. 218 */ 219 foreground |= BLEND_CONTROL_ALPHA; 220 221 /* 222 * If any of the windows on top of this window is opaque, it 223 * will completely conceal this window within that area. If 224 * top window has an alpha component, it is blended over the 225 * bottom window. 226 */ 227 for (i = 0; i < 2; i++) { 228 if (state->blending[i].alpha && 229 state->blending[i].top) 230 background[i] |= BLEND_CONTROL_DEPENDENT; 231 } 232 233 switch (state->base.normalized_zpos) { 234 case 0: 235 if (state->blending[0].alpha && 236 state->blending[1].alpha) 237 background[2] |= BLEND_CONTROL_DEPENDENT; 238 break; 239 240 case 1: 241 /* 242 * When both middle and topmost windows have an alpha, 243 * these windows a mixed together and then the result 244 * is blended over the bottom window. 245 */ 246 if (state->blending[0].alpha && 247 state->blending[0].top) 248 background[2] |= BLEND_CONTROL_ALPHA; 249 250 if (state->blending[1].alpha && 251 state->blending[1].top) 252 background[2] |= BLEND_CONTROL_ALPHA; 253 break; 254 } 255 } 256 257 switch (state->base.normalized_zpos) { 258 case 0: 259 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X); 260 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y); 261 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY); 262 break; 263 264 case 1: 265 /* 266 * If window B / C is topmost, then X / Y registers are 267 * matching the order of blending[...] state indices, 268 * otherwise a swap is required. 269 */ 270 if (!state->blending[0].top && state->blending[1].top) { 271 blending[0] = foreground; 272 blending[1] = background[1]; 273 } else { 274 blending[0] = background[0]; 275 blending[1] = foreground; 276 } 277 278 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X); 279 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y); 280 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY); 281 break; 282 283 case 2: 284 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X); 285 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y); 286 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY); 287 break; 288 } 289 } 290 291 static void tegra_plane_setup_blending(struct tegra_plane *plane, 292 const struct tegra_dc_window *window) 293 { 294 u32 value; 295 296 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 297 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 298 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 299 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT); 300 301 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 302 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 303 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 304 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT); 305 306 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos); 307 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL); 308 } 309 310 static bool 311 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane, 312 const struct tegra_dc_window *window) 313 { 314 struct tegra_dc *dc = plane->dc; 315 316 if (window->src.w == window->dst.w) 317 return false; 318 319 if (plane->index == 0 && dc->soc->has_win_a_without_filters) 320 return false; 321 322 return true; 323 } 324 325 static bool 326 tegra_plane_use_vertical_filtering(struct tegra_plane *plane, 327 const struct tegra_dc_window *window) 328 { 329 struct tegra_dc *dc = plane->dc; 330 331 if (window->src.h == window->dst.h) 332 return false; 333 334 if (plane->index == 0 && dc->soc->has_win_a_without_filters) 335 return false; 336 337 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter) 338 return false; 339 340 return true; 341 } 342 343 static void tegra_dc_setup_window(struct tegra_plane *plane, 344 const struct tegra_dc_window *window) 345 { 346 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; 347 struct tegra_dc *dc = plane->dc; 348 unsigned int planes; 349 u32 value; 350 bool yuv; 351 352 /* 353 * For YUV planar modes, the number of bytes per pixel takes into 354 * account only the luma component and therefore is 1. 355 */ 356 yuv = tegra_plane_format_is_yuv(window->format, &planes, NULL); 357 if (!yuv) 358 bpp = window->bits_per_pixel / 8; 359 else 360 bpp = (planes > 1) ? 1 : 2; 361 362 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH); 363 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP); 364 365 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); 366 tegra_plane_writel(plane, value, DC_WIN_POSITION); 367 368 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); 369 tegra_plane_writel(plane, value, DC_WIN_SIZE); 370 371 h_offset = window->src.x * bpp; 372 v_offset = window->src.y; 373 h_size = window->src.w * bpp; 374 v_size = window->src.h; 375 376 if (window->reflect_x) 377 h_offset += (window->src.w - 1) * bpp; 378 379 if (window->reflect_y) 380 v_offset += window->src.h - 1; 381 382 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); 383 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE); 384 385 /* 386 * For DDA computations the number of bytes per pixel for YUV planar 387 * modes needs to take into account all Y, U and V components. 388 */ 389 if (yuv && planes > 1) 390 bpp = 2; 391 392 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); 393 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); 394 395 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); 396 tegra_plane_writel(plane, value, DC_WIN_DDA_INC); 397 398 h_dda = compute_initial_dda(window->src.x); 399 v_dda = compute_initial_dda(window->src.y); 400 401 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA); 402 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA); 403 404 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE); 405 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE); 406 407 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR); 408 409 if (yuv && planes > 1) { 410 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U); 411 412 if (planes > 2) 413 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V); 414 415 value = window->stride[1] << 16 | window->stride[0]; 416 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE); 417 } else { 418 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE); 419 } 420 421 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET); 422 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET); 423 424 if (dc->soc->supports_block_linear) { 425 unsigned long height = window->tiling.value; 426 427 switch (window->tiling.mode) { 428 case TEGRA_BO_TILING_MODE_PITCH: 429 value = DC_WINBUF_SURFACE_KIND_PITCH; 430 break; 431 432 case TEGRA_BO_TILING_MODE_TILED: 433 value = DC_WINBUF_SURFACE_KIND_TILED; 434 break; 435 436 case TEGRA_BO_TILING_MODE_BLOCK: 437 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | 438 DC_WINBUF_SURFACE_KIND_BLOCK; 439 break; 440 } 441 442 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND); 443 } else { 444 switch (window->tiling.mode) { 445 case TEGRA_BO_TILING_MODE_PITCH: 446 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | 447 DC_WIN_BUFFER_ADDR_MODE_LINEAR; 448 break; 449 450 case TEGRA_BO_TILING_MODE_TILED: 451 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | 452 DC_WIN_BUFFER_ADDR_MODE_TILE; 453 break; 454 455 case TEGRA_BO_TILING_MODE_BLOCK: 456 /* 457 * No need to handle this here because ->atomic_check 458 * will already have filtered it out. 459 */ 460 break; 461 } 462 463 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE); 464 } 465 466 value = WIN_ENABLE; 467 468 if (yuv) { 469 /* setup default colorspace conversion coefficients */ 470 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF); 471 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB); 472 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR); 473 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR); 474 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG); 475 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG); 476 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB); 477 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB); 478 479 value |= CSC_ENABLE; 480 } else if (window->bits_per_pixel < 24) { 481 value |= COLOR_EXPAND; 482 } 483 484 if (window->reflect_x) 485 value |= H_DIRECTION; 486 487 if (window->reflect_y) 488 value |= V_DIRECTION; 489 490 if (tegra_plane_use_horizontal_filtering(plane, window)) { 491 /* 492 * Enable horizontal 6-tap filter and set filtering 493 * coefficients to the default values defined in TRM. 494 */ 495 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0)); 496 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1)); 497 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2)); 498 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3)); 499 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4)); 500 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5)); 501 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6)); 502 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7)); 503 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8)); 504 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9)); 505 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10)); 506 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11)); 507 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12)); 508 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13)); 509 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14)); 510 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15)); 511 512 value |= H_FILTER; 513 } 514 515 if (tegra_plane_use_vertical_filtering(plane, window)) { 516 unsigned int i, k; 517 518 /* 519 * Enable vertical 2-tap filter and set filtering 520 * coefficients to the default values defined in TRM. 521 */ 522 for (i = 0, k = 128; i < 16; i++, k -= 8) 523 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i)); 524 525 value |= V_FILTER; 526 } 527 528 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS); 529 530 if (dc->soc->has_legacy_blending) 531 tegra_plane_setup_blending_legacy(plane); 532 else 533 tegra_plane_setup_blending(plane, window); 534 } 535 536 static const u32 tegra20_primary_formats[] = { 537 DRM_FORMAT_ARGB4444, 538 DRM_FORMAT_ARGB1555, 539 DRM_FORMAT_RGB565, 540 DRM_FORMAT_RGBA5551, 541 DRM_FORMAT_ABGR8888, 542 DRM_FORMAT_ARGB8888, 543 /* non-native formats */ 544 DRM_FORMAT_XRGB1555, 545 DRM_FORMAT_RGBX5551, 546 DRM_FORMAT_XBGR8888, 547 DRM_FORMAT_XRGB8888, 548 }; 549 550 static const u64 tegra20_modifiers[] = { 551 DRM_FORMAT_MOD_LINEAR, 552 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED, 553 DRM_FORMAT_MOD_INVALID 554 }; 555 556 static const u32 tegra114_primary_formats[] = { 557 DRM_FORMAT_ARGB4444, 558 DRM_FORMAT_ARGB1555, 559 DRM_FORMAT_RGB565, 560 DRM_FORMAT_RGBA5551, 561 DRM_FORMAT_ABGR8888, 562 DRM_FORMAT_ARGB8888, 563 /* new on Tegra114 */ 564 DRM_FORMAT_ABGR4444, 565 DRM_FORMAT_ABGR1555, 566 DRM_FORMAT_BGRA5551, 567 DRM_FORMAT_XRGB1555, 568 DRM_FORMAT_RGBX5551, 569 DRM_FORMAT_XBGR1555, 570 DRM_FORMAT_BGRX5551, 571 DRM_FORMAT_BGR565, 572 DRM_FORMAT_BGRA8888, 573 DRM_FORMAT_RGBA8888, 574 DRM_FORMAT_XRGB8888, 575 DRM_FORMAT_XBGR8888, 576 }; 577 578 static const u32 tegra124_primary_formats[] = { 579 DRM_FORMAT_ARGB4444, 580 DRM_FORMAT_ARGB1555, 581 DRM_FORMAT_RGB565, 582 DRM_FORMAT_RGBA5551, 583 DRM_FORMAT_ABGR8888, 584 DRM_FORMAT_ARGB8888, 585 /* new on Tegra114 */ 586 DRM_FORMAT_ABGR4444, 587 DRM_FORMAT_ABGR1555, 588 DRM_FORMAT_BGRA5551, 589 DRM_FORMAT_XRGB1555, 590 DRM_FORMAT_RGBX5551, 591 DRM_FORMAT_XBGR1555, 592 DRM_FORMAT_BGRX5551, 593 DRM_FORMAT_BGR565, 594 DRM_FORMAT_BGRA8888, 595 DRM_FORMAT_RGBA8888, 596 DRM_FORMAT_XRGB8888, 597 DRM_FORMAT_XBGR8888, 598 /* new on Tegra124 */ 599 DRM_FORMAT_RGBX8888, 600 DRM_FORMAT_BGRX8888, 601 }; 602 603 static const u64 tegra124_modifiers[] = { 604 DRM_FORMAT_MOD_LINEAR, 605 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0), 606 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1), 607 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2), 608 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3), 609 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4), 610 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5), 611 DRM_FORMAT_MOD_INVALID 612 }; 613 614 static int tegra_plane_atomic_check(struct drm_plane *plane, 615 struct drm_atomic_state *state) 616 { 617 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 618 plane); 619 struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state); 620 unsigned int supported_rotation = DRM_MODE_ROTATE_0 | 621 DRM_MODE_REFLECT_X | 622 DRM_MODE_REFLECT_Y; 623 unsigned int rotation = new_plane_state->rotation; 624 struct tegra_bo_tiling *tiling = &plane_state->tiling; 625 struct tegra_plane *tegra = to_tegra_plane(plane); 626 struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc); 627 int err; 628 629 plane_state->peak_memory_bandwidth = 0; 630 plane_state->avg_memory_bandwidth = 0; 631 632 /* no need for further checks if the plane is being disabled */ 633 if (!new_plane_state->crtc) { 634 plane_state->total_peak_memory_bandwidth = 0; 635 return 0; 636 } 637 638 err = tegra_plane_format(new_plane_state->fb->format->format, 639 &plane_state->format, 640 &plane_state->swap); 641 if (err < 0) 642 return err; 643 644 /* 645 * Tegra20 and Tegra30 are special cases here because they support 646 * only variants of specific formats with an alpha component, but not 647 * the corresponding opaque formats. However, the opaque formats can 648 * be emulated by disabling alpha blending for the plane. 649 */ 650 if (dc->soc->has_legacy_blending) { 651 err = tegra_plane_setup_legacy_state(tegra, plane_state); 652 if (err < 0) 653 return err; 654 } 655 656 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); 657 if (err < 0) 658 return err; 659 660 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && 661 !dc->soc->supports_block_linear) { 662 DRM_ERROR("hardware doesn't support block linear mode\n"); 663 return -EINVAL; 664 } 665 666 /* 667 * Older userspace used custom BO flag in order to specify the Y 668 * reflection, while modern userspace uses the generic DRM rotation 669 * property in order to achieve the same result. The legacy BO flag 670 * duplicates the DRM rotation property when both are set. 671 */ 672 if (tegra_fb_is_bottom_up(new_plane_state->fb)) 673 rotation |= DRM_MODE_REFLECT_Y; 674 675 rotation = drm_rotation_simplify(rotation, supported_rotation); 676 677 if (rotation & DRM_MODE_REFLECT_X) 678 plane_state->reflect_x = true; 679 else 680 plane_state->reflect_x = false; 681 682 if (rotation & DRM_MODE_REFLECT_Y) 683 plane_state->reflect_y = true; 684 else 685 plane_state->reflect_y = false; 686 687 /* 688 * Tegra doesn't support different strides for U and V planes so we 689 * error out if the user tries to display a framebuffer with such a 690 * configuration. 691 */ 692 if (new_plane_state->fb->format->num_planes > 2) { 693 if (new_plane_state->fb->pitches[2] != new_plane_state->fb->pitches[1]) { 694 DRM_ERROR("unsupported UV-plane configuration\n"); 695 return -EINVAL; 696 } 697 } 698 699 err = tegra_plane_state_add(tegra, new_plane_state); 700 if (err < 0) 701 return err; 702 703 return 0; 704 } 705 706 static void tegra_plane_atomic_disable(struct drm_plane *plane, 707 struct drm_atomic_state *state) 708 { 709 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 710 plane); 711 struct tegra_plane *p = to_tegra_plane(plane); 712 u32 value; 713 714 /* rien ne va plus */ 715 if (!old_state || !old_state->crtc) 716 return; 717 718 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS); 719 value &= ~WIN_ENABLE; 720 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS); 721 } 722 723 static void tegra_plane_atomic_update(struct drm_plane *plane, 724 struct drm_atomic_state *state) 725 { 726 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 727 plane); 728 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state); 729 struct drm_framebuffer *fb = new_state->fb; 730 struct tegra_plane *p = to_tegra_plane(plane); 731 struct tegra_dc_window window; 732 unsigned int i; 733 734 /* rien ne va plus */ 735 if (!new_state->crtc || !new_state->fb) 736 return; 737 738 if (!new_state->visible) 739 return tegra_plane_atomic_disable(plane, state); 740 741 memset(&window, 0, sizeof(window)); 742 window.src.x = new_state->src.x1 >> 16; 743 window.src.y = new_state->src.y1 >> 16; 744 window.src.w = drm_rect_width(&new_state->src) >> 16; 745 window.src.h = drm_rect_height(&new_state->src) >> 16; 746 window.dst.x = new_state->dst.x1; 747 window.dst.y = new_state->dst.y1; 748 window.dst.w = drm_rect_width(&new_state->dst); 749 window.dst.h = drm_rect_height(&new_state->dst); 750 window.bits_per_pixel = fb->format->cpp[0] * 8; 751 window.reflect_x = tegra_plane_state->reflect_x; 752 window.reflect_y = tegra_plane_state->reflect_y; 753 754 /* copy from state */ 755 window.zpos = new_state->normalized_zpos; 756 window.tiling = tegra_plane_state->tiling; 757 window.format = tegra_plane_state->format; 758 window.swap = tegra_plane_state->swap; 759 760 for (i = 0; i < fb->format->num_planes; i++) { 761 window.base[i] = tegra_plane_state->iova[i] + fb->offsets[i]; 762 763 /* 764 * Tegra uses a shared stride for UV planes. Framebuffers are 765 * already checked for this in the tegra_plane_atomic_check() 766 * function, so it's safe to ignore the V-plane pitch here. 767 */ 768 if (i < 2) 769 window.stride[i] = fb->pitches[i]; 770 } 771 772 tegra_dc_setup_window(p, &window); 773 } 774 775 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = { 776 .prepare_fb = tegra_plane_prepare_fb, 777 .cleanup_fb = tegra_plane_cleanup_fb, 778 .atomic_check = tegra_plane_atomic_check, 779 .atomic_disable = tegra_plane_atomic_disable, 780 .atomic_update = tegra_plane_atomic_update, 781 }; 782 783 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm) 784 { 785 /* 786 * Ideally this would use drm_crtc_mask(), but that would require the 787 * CRTC to already be in the mode_config's list of CRTCs. However, it 788 * will only be added to that list in the drm_crtc_init_with_planes() 789 * (in tegra_dc_init()), which in turn requires registration of these 790 * planes. So we have ourselves a nice little chicken and egg problem 791 * here. 792 * 793 * We work around this by manually creating the mask from the number 794 * of CRTCs that have been registered, and should therefore always be 795 * the same as drm_crtc_index() after registration. 796 */ 797 return 1 << drm->mode_config.num_crtc; 798 } 799 800 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm, 801 struct tegra_dc *dc) 802 { 803 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 804 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY; 805 struct tegra_plane *plane; 806 unsigned int num_formats; 807 const u64 *modifiers; 808 const u32 *formats; 809 int err; 810 811 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 812 if (!plane) 813 return ERR_PTR(-ENOMEM); 814 815 /* Always use window A as primary window */ 816 plane->offset = 0xa00; 817 plane->index = 0; 818 plane->dc = dc; 819 820 num_formats = dc->soc->num_primary_formats; 821 formats = dc->soc->primary_formats; 822 modifiers = dc->soc->modifiers; 823 824 err = tegra_plane_interconnect_init(plane); 825 if (err) { 826 kfree(plane); 827 return ERR_PTR(err); 828 } 829 830 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 831 &tegra_plane_funcs, formats, 832 num_formats, modifiers, type, NULL); 833 if (err < 0) { 834 kfree(plane); 835 return ERR_PTR(err); 836 } 837 838 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 839 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); 840 841 err = drm_plane_create_rotation_property(&plane->base, 842 DRM_MODE_ROTATE_0, 843 DRM_MODE_ROTATE_0 | 844 DRM_MODE_ROTATE_180 | 845 DRM_MODE_REFLECT_X | 846 DRM_MODE_REFLECT_Y); 847 if (err < 0) 848 dev_err(dc->dev, "failed to create rotation property: %d\n", 849 err); 850 851 return &plane->base; 852 } 853 854 static const u32 tegra_legacy_cursor_plane_formats[] = { 855 DRM_FORMAT_RGBA8888, 856 }; 857 858 static const u32 tegra_cursor_plane_formats[] = { 859 DRM_FORMAT_ARGB8888, 860 }; 861 862 static int tegra_cursor_atomic_check(struct drm_plane *plane, 863 struct drm_atomic_state *state) 864 { 865 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 866 plane); 867 struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state); 868 struct tegra_plane *tegra = to_tegra_plane(plane); 869 int err; 870 871 plane_state->peak_memory_bandwidth = 0; 872 plane_state->avg_memory_bandwidth = 0; 873 874 /* no need for further checks if the plane is being disabled */ 875 if (!new_plane_state->crtc) { 876 plane_state->total_peak_memory_bandwidth = 0; 877 return 0; 878 } 879 880 /* scaling not supported for cursor */ 881 if ((new_plane_state->src_w >> 16 != new_plane_state->crtc_w) || 882 (new_plane_state->src_h >> 16 != new_plane_state->crtc_h)) 883 return -EINVAL; 884 885 /* only square cursors supported */ 886 if (new_plane_state->src_w != new_plane_state->src_h) 887 return -EINVAL; 888 889 if (new_plane_state->crtc_w != 32 && new_plane_state->crtc_w != 64 && 890 new_plane_state->crtc_w != 128 && new_plane_state->crtc_w != 256) 891 return -EINVAL; 892 893 err = tegra_plane_state_add(tegra, new_plane_state); 894 if (err < 0) 895 return err; 896 897 return 0; 898 } 899 900 static void __tegra_cursor_atomic_update(struct drm_plane *plane, 901 struct drm_plane_state *new_state) 902 { 903 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state); 904 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); 905 struct tegra_drm *tegra = plane->dev->dev_private; 906 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 907 u64 dma_mask = *dc->dev->dma_mask; 908 #endif 909 unsigned int x, y; 910 u32 value = 0; 911 912 /* rien ne va plus */ 913 if (!new_state->crtc || !new_state->fb) 914 return; 915 916 /* 917 * Legacy display supports hardware clipping of the cursor, but 918 * nvdisplay relies on software to clip the cursor to the screen. 919 */ 920 if (!dc->soc->has_nvdisplay) 921 value |= CURSOR_CLIP_DISPLAY; 922 923 switch (new_state->crtc_w) { 924 case 32: 925 value |= CURSOR_SIZE_32x32; 926 break; 927 928 case 64: 929 value |= CURSOR_SIZE_64x64; 930 break; 931 932 case 128: 933 value |= CURSOR_SIZE_128x128; 934 break; 935 936 case 256: 937 value |= CURSOR_SIZE_256x256; 938 break; 939 940 default: 941 WARN(1, "cursor size %ux%u not supported\n", 942 new_state->crtc_w, new_state->crtc_h); 943 return; 944 } 945 946 value |= (tegra_plane_state->iova[0] >> 10) & 0x3fffff; 947 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); 948 949 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 950 value = (tegra_plane_state->iova[0] >> 32) & (dma_mask >> 32); 951 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); 952 #endif 953 954 /* enable cursor and set blend mode */ 955 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 956 value |= CURSOR_ENABLE; 957 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 958 959 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); 960 value &= ~CURSOR_DST_BLEND_MASK; 961 value &= ~CURSOR_SRC_BLEND_MASK; 962 963 if (dc->soc->has_nvdisplay) 964 value &= ~CURSOR_COMPOSITION_MODE_XOR; 965 else 966 value |= CURSOR_MODE_NORMAL; 967 968 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; 969 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; 970 value |= CURSOR_ALPHA; 971 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); 972 973 /* nvdisplay relies on software for clipping */ 974 if (dc->soc->has_nvdisplay) { 975 struct drm_rect src; 976 977 x = new_state->dst.x1; 978 y = new_state->dst.y1; 979 980 drm_rect_fp_to_int(&src, &new_state->src); 981 982 value = (src.y1 & tegra->vmask) << 16 | (src.x1 & tegra->hmask); 983 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR); 984 985 value = (drm_rect_height(&src) & tegra->vmask) << 16 | 986 (drm_rect_width(&src) & tegra->hmask); 987 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR); 988 } else { 989 x = new_state->crtc_x; 990 y = new_state->crtc_y; 991 } 992 993 /* position the cursor */ 994 value = ((y & tegra->vmask) << 16) | (x & tegra->hmask); 995 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); 996 } 997 998 static void tegra_cursor_atomic_update(struct drm_plane *plane, 999 struct drm_atomic_state *state) 1000 { 1001 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); 1002 1003 __tegra_cursor_atomic_update(plane, new_state); 1004 } 1005 1006 static void tegra_cursor_atomic_disable(struct drm_plane *plane, 1007 struct drm_atomic_state *state) 1008 { 1009 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 1010 plane); 1011 struct tegra_dc *dc; 1012 u32 value; 1013 1014 /* rien ne va plus */ 1015 if (!old_state || !old_state->crtc) 1016 return; 1017 1018 dc = to_tegra_dc(old_state->crtc); 1019 1020 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1021 value &= ~CURSOR_ENABLE; 1022 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1023 } 1024 1025 static int tegra_cursor_atomic_async_check(struct drm_plane *plane, struct drm_atomic_state *state) 1026 { 1027 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); 1028 struct drm_crtc_state *crtc_state; 1029 int min_scale, max_scale; 1030 int err; 1031 1032 crtc_state = drm_atomic_get_existing_crtc_state(state, new_state->crtc); 1033 if (WARN_ON(!crtc_state)) 1034 return -EINVAL; 1035 1036 if (!crtc_state->active) 1037 return -EINVAL; 1038 1039 if (plane->state->crtc != new_state->crtc || 1040 plane->state->src_w != new_state->src_w || 1041 plane->state->src_h != new_state->src_h || 1042 plane->state->crtc_w != new_state->crtc_w || 1043 plane->state->crtc_h != new_state->crtc_h || 1044 plane->state->fb != new_state->fb || 1045 plane->state->fb == NULL) 1046 return -EINVAL; 1047 1048 min_scale = (1 << 16) / 8; 1049 max_scale = (8 << 16) / 1; 1050 1051 err = drm_atomic_helper_check_plane_state(new_state, crtc_state, min_scale, max_scale, 1052 true, true); 1053 if (err < 0) 1054 return err; 1055 1056 if (new_state->visible != plane->state->visible) 1057 return -EINVAL; 1058 1059 return 0; 1060 } 1061 1062 static void tegra_cursor_atomic_async_update(struct drm_plane *plane, 1063 struct drm_atomic_state *state) 1064 { 1065 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); 1066 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); 1067 1068 plane->state->src_x = new_state->src_x; 1069 plane->state->src_y = new_state->src_y; 1070 plane->state->crtc_x = new_state->crtc_x; 1071 plane->state->crtc_y = new_state->crtc_y; 1072 1073 if (new_state->visible) { 1074 struct tegra_plane *p = to_tegra_plane(plane); 1075 u32 value; 1076 1077 __tegra_cursor_atomic_update(plane, new_state); 1078 1079 value = (WIN_A_ACT_REQ << p->index) << 8 | GENERAL_UPDATE; 1080 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 1081 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 1082 1083 value = (WIN_A_ACT_REQ << p->index) | GENERAL_ACT_REQ; 1084 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 1085 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 1086 } 1087 } 1088 1089 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = { 1090 .prepare_fb = tegra_plane_prepare_fb, 1091 .cleanup_fb = tegra_plane_cleanup_fb, 1092 .atomic_check = tegra_cursor_atomic_check, 1093 .atomic_update = tegra_cursor_atomic_update, 1094 .atomic_disable = tegra_cursor_atomic_disable, 1095 .atomic_async_check = tegra_cursor_atomic_async_check, 1096 .atomic_async_update = tegra_cursor_atomic_async_update, 1097 }; 1098 1099 static const uint64_t linear_modifiers[] = { 1100 DRM_FORMAT_MOD_LINEAR, 1101 DRM_FORMAT_MOD_INVALID 1102 }; 1103 1104 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, 1105 struct tegra_dc *dc) 1106 { 1107 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 1108 struct tegra_plane *plane; 1109 unsigned int num_formats; 1110 const u32 *formats; 1111 int err; 1112 1113 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 1114 if (!plane) 1115 return ERR_PTR(-ENOMEM); 1116 1117 /* 1118 * This index is kind of fake. The cursor isn't a regular plane, but 1119 * its update and activation request bits in DC_CMD_STATE_CONTROL do 1120 * use the same programming. Setting this fake index here allows the 1121 * code in tegra_add_plane_state() to do the right thing without the 1122 * need to special-casing the cursor plane. 1123 */ 1124 plane->index = 6; 1125 plane->dc = dc; 1126 1127 if (!dc->soc->has_nvdisplay) { 1128 num_formats = ARRAY_SIZE(tegra_legacy_cursor_plane_formats); 1129 formats = tegra_legacy_cursor_plane_formats; 1130 1131 err = tegra_plane_interconnect_init(plane); 1132 if (err) { 1133 kfree(plane); 1134 return ERR_PTR(err); 1135 } 1136 } else { 1137 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); 1138 formats = tegra_cursor_plane_formats; 1139 } 1140 1141 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 1142 &tegra_plane_funcs, formats, 1143 num_formats, linear_modifiers, 1144 DRM_PLANE_TYPE_CURSOR, NULL); 1145 if (err < 0) { 1146 kfree(plane); 1147 return ERR_PTR(err); 1148 } 1149 1150 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); 1151 drm_plane_create_zpos_immutable_property(&plane->base, 255); 1152 1153 return &plane->base; 1154 } 1155 1156 static const u32 tegra20_overlay_formats[] = { 1157 DRM_FORMAT_ARGB4444, 1158 DRM_FORMAT_ARGB1555, 1159 DRM_FORMAT_RGB565, 1160 DRM_FORMAT_RGBA5551, 1161 DRM_FORMAT_ABGR8888, 1162 DRM_FORMAT_ARGB8888, 1163 /* non-native formats */ 1164 DRM_FORMAT_XRGB1555, 1165 DRM_FORMAT_RGBX5551, 1166 DRM_FORMAT_XBGR8888, 1167 DRM_FORMAT_XRGB8888, 1168 /* planar formats */ 1169 DRM_FORMAT_UYVY, 1170 DRM_FORMAT_YUYV, 1171 DRM_FORMAT_YUV420, 1172 DRM_FORMAT_YUV422, 1173 }; 1174 1175 static const u32 tegra114_overlay_formats[] = { 1176 DRM_FORMAT_ARGB4444, 1177 DRM_FORMAT_ARGB1555, 1178 DRM_FORMAT_RGB565, 1179 DRM_FORMAT_RGBA5551, 1180 DRM_FORMAT_ABGR8888, 1181 DRM_FORMAT_ARGB8888, 1182 /* new on Tegra114 */ 1183 DRM_FORMAT_ABGR4444, 1184 DRM_FORMAT_ABGR1555, 1185 DRM_FORMAT_BGRA5551, 1186 DRM_FORMAT_XRGB1555, 1187 DRM_FORMAT_RGBX5551, 1188 DRM_FORMAT_XBGR1555, 1189 DRM_FORMAT_BGRX5551, 1190 DRM_FORMAT_BGR565, 1191 DRM_FORMAT_BGRA8888, 1192 DRM_FORMAT_RGBA8888, 1193 DRM_FORMAT_XRGB8888, 1194 DRM_FORMAT_XBGR8888, 1195 /* planar formats */ 1196 DRM_FORMAT_UYVY, 1197 DRM_FORMAT_YUYV, 1198 DRM_FORMAT_YUV420, 1199 DRM_FORMAT_YUV422, 1200 /* semi-planar formats */ 1201 DRM_FORMAT_NV12, 1202 DRM_FORMAT_NV21, 1203 DRM_FORMAT_NV16, 1204 DRM_FORMAT_NV61, 1205 DRM_FORMAT_NV24, 1206 DRM_FORMAT_NV42, 1207 }; 1208 1209 static const u32 tegra124_overlay_formats[] = { 1210 DRM_FORMAT_ARGB4444, 1211 DRM_FORMAT_ARGB1555, 1212 DRM_FORMAT_RGB565, 1213 DRM_FORMAT_RGBA5551, 1214 DRM_FORMAT_ABGR8888, 1215 DRM_FORMAT_ARGB8888, 1216 /* new on Tegra114 */ 1217 DRM_FORMAT_ABGR4444, 1218 DRM_FORMAT_ABGR1555, 1219 DRM_FORMAT_BGRA5551, 1220 DRM_FORMAT_XRGB1555, 1221 DRM_FORMAT_RGBX5551, 1222 DRM_FORMAT_XBGR1555, 1223 DRM_FORMAT_BGRX5551, 1224 DRM_FORMAT_BGR565, 1225 DRM_FORMAT_BGRA8888, 1226 DRM_FORMAT_RGBA8888, 1227 DRM_FORMAT_XRGB8888, 1228 DRM_FORMAT_XBGR8888, 1229 /* new on Tegra124 */ 1230 DRM_FORMAT_RGBX8888, 1231 DRM_FORMAT_BGRX8888, 1232 /* planar formats */ 1233 DRM_FORMAT_UYVY, 1234 DRM_FORMAT_YUYV, 1235 DRM_FORMAT_YUV420, 1236 DRM_FORMAT_YUV422, 1237 /* semi-planar formats */ 1238 DRM_FORMAT_NV12, 1239 DRM_FORMAT_NV21, 1240 DRM_FORMAT_NV16, 1241 DRM_FORMAT_NV61, 1242 DRM_FORMAT_NV24, 1243 DRM_FORMAT_NV42, 1244 }; 1245 1246 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, 1247 struct tegra_dc *dc, 1248 unsigned int index, 1249 bool cursor) 1250 { 1251 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 1252 struct tegra_plane *plane; 1253 unsigned int num_formats; 1254 enum drm_plane_type type; 1255 const u32 *formats; 1256 int err; 1257 1258 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 1259 if (!plane) 1260 return ERR_PTR(-ENOMEM); 1261 1262 plane->offset = 0xa00 + 0x200 * index; 1263 plane->index = index; 1264 plane->dc = dc; 1265 1266 num_formats = dc->soc->num_overlay_formats; 1267 formats = dc->soc->overlay_formats; 1268 1269 err = tegra_plane_interconnect_init(plane); 1270 if (err) { 1271 kfree(plane); 1272 return ERR_PTR(err); 1273 } 1274 1275 if (!cursor) 1276 type = DRM_PLANE_TYPE_OVERLAY; 1277 else 1278 type = DRM_PLANE_TYPE_CURSOR; 1279 1280 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 1281 &tegra_plane_funcs, formats, 1282 num_formats, linear_modifiers, 1283 type, NULL); 1284 if (err < 0) { 1285 kfree(plane); 1286 return ERR_PTR(err); 1287 } 1288 1289 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 1290 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); 1291 1292 err = drm_plane_create_rotation_property(&plane->base, 1293 DRM_MODE_ROTATE_0, 1294 DRM_MODE_ROTATE_0 | 1295 DRM_MODE_ROTATE_180 | 1296 DRM_MODE_REFLECT_X | 1297 DRM_MODE_REFLECT_Y); 1298 if (err < 0) 1299 dev_err(dc->dev, "failed to create rotation property: %d\n", 1300 err); 1301 1302 return &plane->base; 1303 } 1304 1305 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm, 1306 struct tegra_dc *dc) 1307 { 1308 struct drm_plane *plane, *primary = NULL; 1309 unsigned int i, j; 1310 1311 for (i = 0; i < dc->soc->num_wgrps; i++) { 1312 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; 1313 1314 if (wgrp->dc == dc->pipe) { 1315 for (j = 0; j < wgrp->num_windows; j++) { 1316 unsigned int index = wgrp->windows[j]; 1317 1318 plane = tegra_shared_plane_create(drm, dc, 1319 wgrp->index, 1320 index); 1321 if (IS_ERR(plane)) 1322 return plane; 1323 1324 /* 1325 * Choose the first shared plane owned by this 1326 * head as the primary plane. 1327 */ 1328 if (!primary) { 1329 plane->type = DRM_PLANE_TYPE_PRIMARY; 1330 primary = plane; 1331 } 1332 } 1333 } 1334 } 1335 1336 return primary; 1337 } 1338 1339 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm, 1340 struct tegra_dc *dc) 1341 { 1342 struct drm_plane *planes[2], *primary; 1343 unsigned int planes_num; 1344 unsigned int i; 1345 int err; 1346 1347 primary = tegra_primary_plane_create(drm, dc); 1348 if (IS_ERR(primary)) 1349 return primary; 1350 1351 if (dc->soc->supports_cursor) 1352 planes_num = 2; 1353 else 1354 planes_num = 1; 1355 1356 for (i = 0; i < planes_num; i++) { 1357 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i, 1358 false); 1359 if (IS_ERR(planes[i])) { 1360 err = PTR_ERR(planes[i]); 1361 1362 while (i--) 1363 planes[i]->funcs->destroy(planes[i]); 1364 1365 primary->funcs->destroy(primary); 1366 return ERR_PTR(err); 1367 } 1368 } 1369 1370 return primary; 1371 } 1372 1373 static void tegra_dc_destroy(struct drm_crtc *crtc) 1374 { 1375 drm_crtc_cleanup(crtc); 1376 } 1377 1378 static void tegra_crtc_reset(struct drm_crtc *crtc) 1379 { 1380 struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 1381 1382 if (crtc->state) 1383 tegra_crtc_atomic_destroy_state(crtc, crtc->state); 1384 1385 __drm_atomic_helper_crtc_reset(crtc, &state->base); 1386 } 1387 1388 static struct drm_crtc_state * 1389 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 1390 { 1391 struct tegra_dc_state *state = to_dc_state(crtc->state); 1392 struct tegra_dc_state *copy; 1393 1394 copy = kmalloc(sizeof(*copy), GFP_KERNEL); 1395 if (!copy) 1396 return NULL; 1397 1398 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base); 1399 copy->clk = state->clk; 1400 copy->pclk = state->pclk; 1401 copy->div = state->div; 1402 copy->planes = state->planes; 1403 1404 return ©->base; 1405 } 1406 1407 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, 1408 struct drm_crtc_state *state) 1409 { 1410 __drm_atomic_helper_crtc_destroy_state(state); 1411 kfree(state); 1412 } 1413 1414 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 1415 1416 static const struct debugfs_reg32 tegra_dc_regs[] = { 1417 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT), 1418 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL), 1419 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR), 1420 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT), 1421 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL), 1422 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR), 1423 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT), 1424 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL), 1425 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR), 1426 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT), 1427 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL), 1428 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR), 1429 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC), 1430 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0), 1431 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND), 1432 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE), 1433 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL), 1434 DEBUGFS_REG32(DC_CMD_INT_STATUS), 1435 DEBUGFS_REG32(DC_CMD_INT_MASK), 1436 DEBUGFS_REG32(DC_CMD_INT_ENABLE), 1437 DEBUGFS_REG32(DC_CMD_INT_TYPE), 1438 DEBUGFS_REG32(DC_CMD_INT_POLARITY), 1439 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1), 1440 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2), 1441 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3), 1442 DEBUGFS_REG32(DC_CMD_STATE_ACCESS), 1443 DEBUGFS_REG32(DC_CMD_STATE_CONTROL), 1444 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER), 1445 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL), 1446 DEBUGFS_REG32(DC_COM_CRC_CONTROL), 1447 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM), 1448 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)), 1449 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)), 1450 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)), 1451 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)), 1452 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)), 1453 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)), 1454 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)), 1455 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)), 1456 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)), 1457 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)), 1458 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)), 1459 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)), 1460 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)), 1461 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)), 1462 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)), 1463 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)), 1464 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)), 1465 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)), 1466 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)), 1467 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)), 1468 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)), 1469 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)), 1470 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)), 1471 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)), 1472 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)), 1473 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL), 1474 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL), 1475 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE), 1476 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL), 1477 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE), 1478 DEBUGFS_REG32(DC_COM_SPI_CONTROL), 1479 DEBUGFS_REG32(DC_COM_SPI_START_BYTE), 1480 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB), 1481 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD), 1482 DEBUGFS_REG32(DC_COM_HSPI_CS_DC), 1483 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A), 1484 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B), 1485 DEBUGFS_REG32(DC_COM_GPIO_CTRL), 1486 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER), 1487 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED), 1488 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0), 1489 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1), 1490 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS), 1491 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY), 1492 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER), 1493 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS), 1494 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC), 1495 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH), 1496 DEBUGFS_REG32(DC_DISP_BACK_PORCH), 1497 DEBUGFS_REG32(DC_DISP_ACTIVE), 1498 DEBUGFS_REG32(DC_DISP_FRONT_PORCH), 1499 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL), 1500 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A), 1501 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B), 1502 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C), 1503 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D), 1504 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL), 1505 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A), 1506 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B), 1507 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C), 1508 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D), 1509 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL), 1510 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A), 1511 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B), 1512 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C), 1513 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D), 1514 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL), 1515 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A), 1516 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B), 1517 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C), 1518 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL), 1519 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A), 1520 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B), 1521 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C), 1522 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL), 1523 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A), 1524 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL), 1525 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A), 1526 DEBUGFS_REG32(DC_DISP_M0_CONTROL), 1527 DEBUGFS_REG32(DC_DISP_M1_CONTROL), 1528 DEBUGFS_REG32(DC_DISP_DI_CONTROL), 1529 DEBUGFS_REG32(DC_DISP_PP_CONTROL), 1530 DEBUGFS_REG32(DC_DISP_PP_SELECT_A), 1531 DEBUGFS_REG32(DC_DISP_PP_SELECT_B), 1532 DEBUGFS_REG32(DC_DISP_PP_SELECT_C), 1533 DEBUGFS_REG32(DC_DISP_PP_SELECT_D), 1534 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL), 1535 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL), 1536 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL), 1537 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS), 1538 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS), 1539 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS), 1540 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS), 1541 DEBUGFS_REG32(DC_DISP_BORDER_COLOR), 1542 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER), 1543 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER), 1544 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER), 1545 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER), 1546 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND), 1547 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND), 1548 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR), 1549 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS), 1550 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION), 1551 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS), 1552 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL), 1553 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A), 1554 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B), 1555 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C), 1556 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D), 1557 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL), 1558 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST), 1559 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST), 1560 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST), 1561 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST), 1562 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL), 1563 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL), 1564 DEBUGFS_REG32(DC_DISP_SD_CONTROL), 1565 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF), 1566 DEBUGFS_REG32(DC_DISP_SD_LUT(0)), 1567 DEBUGFS_REG32(DC_DISP_SD_LUT(1)), 1568 DEBUGFS_REG32(DC_DISP_SD_LUT(2)), 1569 DEBUGFS_REG32(DC_DISP_SD_LUT(3)), 1570 DEBUGFS_REG32(DC_DISP_SD_LUT(4)), 1571 DEBUGFS_REG32(DC_DISP_SD_LUT(5)), 1572 DEBUGFS_REG32(DC_DISP_SD_LUT(6)), 1573 DEBUGFS_REG32(DC_DISP_SD_LUT(7)), 1574 DEBUGFS_REG32(DC_DISP_SD_LUT(8)), 1575 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL), 1576 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT), 1577 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)), 1578 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)), 1579 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)), 1580 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)), 1581 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)), 1582 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)), 1583 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)), 1584 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)), 1585 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)), 1586 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)), 1587 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)), 1588 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)), 1589 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL), 1590 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES), 1591 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES), 1592 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI), 1593 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL), 1594 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS), 1595 DEBUGFS_REG32(DC_WIN_BYTE_SWAP), 1596 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL), 1597 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH), 1598 DEBUGFS_REG32(DC_WIN_POSITION), 1599 DEBUGFS_REG32(DC_WIN_SIZE), 1600 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE), 1601 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA), 1602 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA), 1603 DEBUGFS_REG32(DC_WIN_DDA_INC), 1604 DEBUGFS_REG32(DC_WIN_LINE_STRIDE), 1605 DEBUGFS_REG32(DC_WIN_BUF_STRIDE), 1606 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE), 1607 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE), 1608 DEBUGFS_REG32(DC_WIN_DV_CONTROL), 1609 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY), 1610 DEBUGFS_REG32(DC_WIN_BLEND_1WIN), 1611 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X), 1612 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y), 1613 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY), 1614 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL), 1615 DEBUGFS_REG32(DC_WINBUF_START_ADDR), 1616 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS), 1617 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U), 1618 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS), 1619 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V), 1620 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS), 1621 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET), 1622 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS), 1623 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET), 1624 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS), 1625 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS), 1626 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS), 1627 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS), 1628 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS), 1629 }; 1630 1631 static int tegra_dc_show_regs(struct seq_file *s, void *data) 1632 { 1633 struct drm_info_node *node = s->private; 1634 struct tegra_dc *dc = node->info_ent->data; 1635 unsigned int i; 1636 int err = 0; 1637 1638 drm_modeset_lock(&dc->base.mutex, NULL); 1639 1640 if (!dc->base.state->active) { 1641 err = -EBUSY; 1642 goto unlock; 1643 } 1644 1645 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) { 1646 unsigned int offset = tegra_dc_regs[i].offset; 1647 1648 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name, 1649 offset, tegra_dc_readl(dc, offset)); 1650 } 1651 1652 unlock: 1653 drm_modeset_unlock(&dc->base.mutex); 1654 return err; 1655 } 1656 1657 static int tegra_dc_show_crc(struct seq_file *s, void *data) 1658 { 1659 struct drm_info_node *node = s->private; 1660 struct tegra_dc *dc = node->info_ent->data; 1661 int err = 0; 1662 u32 value; 1663 1664 drm_modeset_lock(&dc->base.mutex, NULL); 1665 1666 if (!dc->base.state->active) { 1667 err = -EBUSY; 1668 goto unlock; 1669 } 1670 1671 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE; 1672 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); 1673 tegra_dc_commit(dc); 1674 1675 drm_crtc_wait_one_vblank(&dc->base); 1676 drm_crtc_wait_one_vblank(&dc->base); 1677 1678 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); 1679 seq_printf(s, "%08x\n", value); 1680 1681 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); 1682 1683 unlock: 1684 drm_modeset_unlock(&dc->base.mutex); 1685 return err; 1686 } 1687 1688 static int tegra_dc_show_stats(struct seq_file *s, void *data) 1689 { 1690 struct drm_info_node *node = s->private; 1691 struct tegra_dc *dc = node->info_ent->data; 1692 1693 seq_printf(s, "frames: %lu\n", dc->stats.frames); 1694 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); 1695 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); 1696 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); 1697 1698 seq_printf(s, "frames total: %lu\n", dc->stats.frames_total); 1699 seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total); 1700 seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total); 1701 seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total); 1702 1703 return 0; 1704 } 1705 1706 static struct drm_info_list debugfs_files[] = { 1707 { "regs", tegra_dc_show_regs, 0, NULL }, 1708 { "crc", tegra_dc_show_crc, 0, NULL }, 1709 { "stats", tegra_dc_show_stats, 0, NULL }, 1710 }; 1711 1712 static int tegra_dc_late_register(struct drm_crtc *crtc) 1713 { 1714 unsigned int i, count = ARRAY_SIZE(debugfs_files); 1715 struct drm_minor *minor = crtc->dev->primary; 1716 struct dentry *root; 1717 struct tegra_dc *dc = to_tegra_dc(crtc); 1718 1719 #ifdef CONFIG_DEBUG_FS 1720 root = crtc->debugfs_entry; 1721 #else 1722 root = NULL; 1723 #endif 1724 1725 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1726 GFP_KERNEL); 1727 if (!dc->debugfs_files) 1728 return -ENOMEM; 1729 1730 for (i = 0; i < count; i++) 1731 dc->debugfs_files[i].data = dc; 1732 1733 drm_debugfs_create_files(dc->debugfs_files, count, root, minor); 1734 1735 return 0; 1736 } 1737 1738 static void tegra_dc_early_unregister(struct drm_crtc *crtc) 1739 { 1740 unsigned int count = ARRAY_SIZE(debugfs_files); 1741 struct drm_minor *minor = crtc->dev->primary; 1742 struct tegra_dc *dc = to_tegra_dc(crtc); 1743 1744 drm_debugfs_remove_files(dc->debugfs_files, count, minor); 1745 kfree(dc->debugfs_files); 1746 dc->debugfs_files = NULL; 1747 } 1748 1749 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc) 1750 { 1751 struct tegra_dc *dc = to_tegra_dc(crtc); 1752 1753 /* XXX vblank syncpoints don't work with nvdisplay yet */ 1754 if (dc->syncpt && !dc->soc->has_nvdisplay) 1755 return host1x_syncpt_read(dc->syncpt); 1756 1757 /* fallback to software emulated VBLANK counter */ 1758 return (u32)drm_crtc_vblank_count(&dc->base); 1759 } 1760 1761 static int tegra_dc_enable_vblank(struct drm_crtc *crtc) 1762 { 1763 struct tegra_dc *dc = to_tegra_dc(crtc); 1764 u32 value; 1765 1766 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 1767 value |= VBLANK_INT; 1768 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1769 1770 return 0; 1771 } 1772 1773 static void tegra_dc_disable_vblank(struct drm_crtc *crtc) 1774 { 1775 struct tegra_dc *dc = to_tegra_dc(crtc); 1776 u32 value; 1777 1778 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 1779 value &= ~VBLANK_INT; 1780 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1781 } 1782 1783 static const struct drm_crtc_funcs tegra_crtc_funcs = { 1784 .page_flip = drm_atomic_helper_page_flip, 1785 .set_config = drm_atomic_helper_set_config, 1786 .destroy = tegra_dc_destroy, 1787 .reset = tegra_crtc_reset, 1788 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state, 1789 .atomic_destroy_state = tegra_crtc_atomic_destroy_state, 1790 .late_register = tegra_dc_late_register, 1791 .early_unregister = tegra_dc_early_unregister, 1792 .get_vblank_counter = tegra_dc_get_vblank_counter, 1793 .enable_vblank = tegra_dc_enable_vblank, 1794 .disable_vblank = tegra_dc_disable_vblank, 1795 }; 1796 1797 static int tegra_dc_set_timings(struct tegra_dc *dc, 1798 struct drm_display_mode *mode) 1799 { 1800 unsigned int h_ref_to_sync = 1; 1801 unsigned int v_ref_to_sync = 1; 1802 unsigned long value; 1803 1804 if (!dc->soc->has_nvdisplay) { 1805 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); 1806 1807 value = (v_ref_to_sync << 16) | h_ref_to_sync; 1808 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); 1809 } 1810 1811 value = ((mode->vsync_end - mode->vsync_start) << 16) | 1812 ((mode->hsync_end - mode->hsync_start) << 0); 1813 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); 1814 1815 value = ((mode->vtotal - mode->vsync_end) << 16) | 1816 ((mode->htotal - mode->hsync_end) << 0); 1817 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); 1818 1819 value = ((mode->vsync_start - mode->vdisplay) << 16) | 1820 ((mode->hsync_start - mode->hdisplay) << 0); 1821 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); 1822 1823 value = (mode->vdisplay << 16) | mode->hdisplay; 1824 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); 1825 1826 return 0; 1827 } 1828 1829 /** 1830 * tegra_dc_state_setup_clock - check clock settings and store them in atomic 1831 * state 1832 * @dc: display controller 1833 * @crtc_state: CRTC atomic state 1834 * @clk: parent clock for display controller 1835 * @pclk: pixel clock 1836 * @div: shift clock divider 1837 * 1838 * Returns: 1839 * 0 on success or a negative error-code on failure. 1840 */ 1841 int tegra_dc_state_setup_clock(struct tegra_dc *dc, 1842 struct drm_crtc_state *crtc_state, 1843 struct clk *clk, unsigned long pclk, 1844 unsigned int div) 1845 { 1846 struct tegra_dc_state *state = to_dc_state(crtc_state); 1847 1848 if (!clk_has_parent(dc->clk, clk)) 1849 return -EINVAL; 1850 1851 state->clk = clk; 1852 state->pclk = pclk; 1853 state->div = div; 1854 1855 return 0; 1856 } 1857 1858 static void tegra_dc_update_voltage_state(struct tegra_dc *dc, 1859 struct tegra_dc_state *state) 1860 { 1861 unsigned long rate, pstate; 1862 struct dev_pm_opp *opp; 1863 int err; 1864 1865 if (!dc->has_opp_table) 1866 return; 1867 1868 /* calculate actual pixel clock rate which depends on internal divider */ 1869 rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2); 1870 1871 /* find suitable OPP for the rate */ 1872 opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate); 1873 1874 /* 1875 * Very high resolution modes may results in a clock rate that is 1876 * above the characterized maximum. In this case it's okay to fall 1877 * back to the characterized maximum. 1878 */ 1879 if (opp == ERR_PTR(-ERANGE)) 1880 opp = dev_pm_opp_find_freq_floor(dc->dev, &rate); 1881 1882 if (IS_ERR(opp)) { 1883 dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n", 1884 rate, opp); 1885 return; 1886 } 1887 1888 pstate = dev_pm_opp_get_required_pstate(opp, 0); 1889 dev_pm_opp_put(opp); 1890 1891 /* 1892 * The minimum core voltage depends on the pixel clock rate (which 1893 * depends on internal clock divider of the CRTC) and not on the 1894 * rate of the display controller clock. This is why we're not using 1895 * dev_pm_opp_set_rate() API and instead controlling the power domain 1896 * directly. 1897 */ 1898 err = dev_pm_genpd_set_performance_state(dc->dev, pstate); 1899 if (err) 1900 dev_err(dc->dev, "failed to set power domain state to %lu: %d\n", 1901 pstate, err); 1902 } 1903 1904 static void tegra_dc_set_clock_rate(struct tegra_dc *dc, 1905 struct tegra_dc_state *state) 1906 { 1907 int err; 1908 1909 err = clk_set_parent(dc->clk, state->clk); 1910 if (err < 0) 1911 dev_err(dc->dev, "failed to set parent clock: %d\n", err); 1912 1913 /* 1914 * Outputs may not want to change the parent clock rate. This is only 1915 * relevant to Tegra20 where only a single display PLL is available. 1916 * Since that PLL would typically be used for HDMI, an internal LVDS 1917 * panel would need to be driven by some other clock such as PLL_P 1918 * which is shared with other peripherals. Changing the clock rate 1919 * should therefore be avoided. 1920 */ 1921 if (state->pclk > 0) { 1922 err = clk_set_rate(state->clk, state->pclk); 1923 if (err < 0) 1924 dev_err(dc->dev, 1925 "failed to set clock rate to %lu Hz\n", 1926 state->pclk); 1927 1928 err = clk_set_rate(dc->clk, state->pclk); 1929 if (err < 0) 1930 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", 1931 dc->clk, state->pclk, err); 1932 } 1933 1934 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), 1935 state->div); 1936 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); 1937 1938 tegra_dc_update_voltage_state(dc, state); 1939 } 1940 1941 static void tegra_dc_stop(struct tegra_dc *dc) 1942 { 1943 u32 value; 1944 1945 /* stop the display controller */ 1946 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 1947 value &= ~DISP_CTRL_MODE_MASK; 1948 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 1949 1950 tegra_dc_commit(dc); 1951 } 1952 1953 static bool tegra_dc_idle(struct tegra_dc *dc) 1954 { 1955 u32 value; 1956 1957 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); 1958 1959 return (value & DISP_CTRL_MODE_MASK) == 0; 1960 } 1961 1962 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) 1963 { 1964 timeout = jiffies + msecs_to_jiffies(timeout); 1965 1966 while (time_before(jiffies, timeout)) { 1967 if (tegra_dc_idle(dc)) 1968 return 0; 1969 1970 usleep_range(1000, 2000); 1971 } 1972 1973 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); 1974 return -ETIMEDOUT; 1975 } 1976 1977 static void 1978 tegra_crtc_update_memory_bandwidth(struct drm_crtc *crtc, 1979 struct drm_atomic_state *state, 1980 bool prepare_bandwidth_transition) 1981 { 1982 const struct tegra_plane_state *old_tegra_state, *new_tegra_state; 1983 u32 i, new_avg_bw, old_avg_bw, new_peak_bw, old_peak_bw; 1984 const struct drm_plane_state *old_plane_state; 1985 const struct drm_crtc_state *old_crtc_state; 1986 struct tegra_dc_window window, old_window; 1987 struct tegra_dc *dc = to_tegra_dc(crtc); 1988 struct tegra_plane *tegra; 1989 struct drm_plane *plane; 1990 1991 if (dc->soc->has_nvdisplay) 1992 return; 1993 1994 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); 1995 1996 if (!crtc->state->active) { 1997 if (!old_crtc_state->active) 1998 return; 1999 2000 /* 2001 * When CRTC is disabled on DPMS, the state of attached planes 2002 * is kept unchanged. Hence we need to enforce removal of the 2003 * bandwidths from the ICC paths. 2004 */ 2005 drm_atomic_crtc_for_each_plane(plane, crtc) { 2006 tegra = to_tegra_plane(plane); 2007 2008 icc_set_bw(tegra->icc_mem, 0, 0); 2009 icc_set_bw(tegra->icc_mem_vfilter, 0, 0); 2010 } 2011 2012 return; 2013 } 2014 2015 for_each_old_plane_in_state(old_crtc_state->state, plane, 2016 old_plane_state, i) { 2017 old_tegra_state = to_const_tegra_plane_state(old_plane_state); 2018 new_tegra_state = to_const_tegra_plane_state(plane->state); 2019 tegra = to_tegra_plane(plane); 2020 2021 /* 2022 * We're iterating over the global atomic state and it contains 2023 * planes from another CRTC, hence we need to filter out the 2024 * planes unrelated to this CRTC. 2025 */ 2026 if (tegra->dc != dc) 2027 continue; 2028 2029 new_avg_bw = new_tegra_state->avg_memory_bandwidth; 2030 old_avg_bw = old_tegra_state->avg_memory_bandwidth; 2031 2032 new_peak_bw = new_tegra_state->total_peak_memory_bandwidth; 2033 old_peak_bw = old_tegra_state->total_peak_memory_bandwidth; 2034 2035 /* 2036 * See the comment related to !crtc->state->active above, 2037 * which explains why bandwidths need to be updated when 2038 * CRTC is turning ON. 2039 */ 2040 if (new_avg_bw == old_avg_bw && new_peak_bw == old_peak_bw && 2041 old_crtc_state->active) 2042 continue; 2043 2044 window.src.h = drm_rect_height(&plane->state->src) >> 16; 2045 window.dst.h = drm_rect_height(&plane->state->dst); 2046 2047 old_window.src.h = drm_rect_height(&old_plane_state->src) >> 16; 2048 old_window.dst.h = drm_rect_height(&old_plane_state->dst); 2049 2050 /* 2051 * During the preparation phase (atomic_begin), the memory 2052 * freq should go high before the DC changes are committed 2053 * if bandwidth requirement goes up, otherwise memory freq 2054 * should to stay high if BW requirement goes down. The 2055 * opposite applies to the completion phase (post_commit). 2056 */ 2057 if (prepare_bandwidth_transition) { 2058 new_avg_bw = max(old_avg_bw, new_avg_bw); 2059 new_peak_bw = max(old_peak_bw, new_peak_bw); 2060 2061 if (tegra_plane_use_vertical_filtering(tegra, &old_window)) 2062 window = old_window; 2063 } 2064 2065 icc_set_bw(tegra->icc_mem, new_avg_bw, new_peak_bw); 2066 2067 if (tegra_plane_use_vertical_filtering(tegra, &window)) 2068 icc_set_bw(tegra->icc_mem_vfilter, new_avg_bw, new_peak_bw); 2069 else 2070 icc_set_bw(tegra->icc_mem_vfilter, 0, 0); 2071 } 2072 } 2073 2074 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, 2075 struct drm_atomic_state *state) 2076 { 2077 struct tegra_dc *dc = to_tegra_dc(crtc); 2078 u32 value; 2079 int err; 2080 2081 if (!tegra_dc_idle(dc)) { 2082 tegra_dc_stop(dc); 2083 2084 /* 2085 * Ignore the return value, there isn't anything useful to do 2086 * in case this fails. 2087 */ 2088 tegra_dc_wait_idle(dc, 100); 2089 } 2090 2091 /* 2092 * This should really be part of the RGB encoder driver, but clearing 2093 * these bits has the side-effect of stopping the display controller. 2094 * When that happens no VBLANK interrupts will be raised. At the same 2095 * time the encoder is disabled before the display controller, so the 2096 * above code is always going to timeout waiting for the controller 2097 * to go idle. 2098 * 2099 * Given the close coupling between the RGB encoder and the display 2100 * controller doing it here is still kind of okay. None of the other 2101 * encoder drivers require these bits to be cleared. 2102 * 2103 * XXX: Perhaps given that the display controller is switched off at 2104 * this point anyway maybe clearing these bits isn't even useful for 2105 * the RGB encoder? 2106 */ 2107 if (dc->rgb) { 2108 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 2109 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 2110 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); 2111 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 2112 } 2113 2114 tegra_dc_stats_reset(&dc->stats); 2115 drm_crtc_vblank_off(crtc); 2116 2117 spin_lock_irq(&crtc->dev->event_lock); 2118 2119 if (crtc->state->event) { 2120 drm_crtc_send_vblank_event(crtc, crtc->state->event); 2121 crtc->state->event = NULL; 2122 } 2123 2124 spin_unlock_irq(&crtc->dev->event_lock); 2125 2126 err = host1x_client_suspend(&dc->client); 2127 if (err < 0) 2128 dev_err(dc->dev, "failed to suspend: %d\n", err); 2129 2130 if (dc->has_opp_table) { 2131 err = dev_pm_genpd_set_performance_state(dc->dev, 0); 2132 if (err) 2133 dev_err(dc->dev, 2134 "failed to clear power domain state: %d\n", err); 2135 } 2136 } 2137 2138 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, 2139 struct drm_atomic_state *state) 2140 { 2141 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 2142 struct tegra_dc_state *crtc_state = to_dc_state(crtc->state); 2143 struct tegra_dc *dc = to_tegra_dc(crtc); 2144 u32 value; 2145 int err; 2146 2147 /* apply PLL changes */ 2148 tegra_dc_set_clock_rate(dc, crtc_state); 2149 2150 err = host1x_client_resume(&dc->client); 2151 if (err < 0) { 2152 dev_err(dc->dev, "failed to resume: %d\n", err); 2153 return; 2154 } 2155 2156 /* initialize display controller */ 2157 if (dc->syncpt) { 2158 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; 2159 2160 if (dc->soc->has_nvdisplay) 2161 enable = 1 << 31; 2162 else 2163 enable = 1 << 8; 2164 2165 value = SYNCPT_CNTRL_NO_STALL; 2166 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); 2167 2168 value = enable | syncpt; 2169 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); 2170 } 2171 2172 if (dc->soc->has_nvdisplay) { 2173 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT | 2174 DSC_OBUF_UF_INT; 2175 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 2176 2177 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT | 2178 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT | 2179 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT | 2180 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT | 2181 VBLANK_INT | FRAME_END_INT; 2182 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 2183 2184 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT | 2185 FRAME_END_INT; 2186 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 2187 2188 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT; 2189 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 2190 2191 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 2192 } else { 2193 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 2194 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 2195 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 2196 2197 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 2198 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 2199 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 2200 2201 /* initialize timer */ 2202 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | 2203 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); 2204 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); 2205 2206 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | 2207 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); 2208 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); 2209 2210 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 2211 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 2212 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 2213 2214 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 2215 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 2216 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 2217 } 2218 2219 if (dc->soc->supports_background_color) 2220 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR); 2221 else 2222 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); 2223 2224 /* apply pixel clock changes */ 2225 if (!dc->soc->has_nvdisplay) { 2226 value = SHIFT_CLK_DIVIDER(crtc_state->div) | PIXEL_CLK_DIVIDER_PCD1; 2227 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); 2228 } 2229 2230 /* program display mode */ 2231 tegra_dc_set_timings(dc, mode); 2232 2233 /* interlacing isn't supported yet, so disable it */ 2234 if (dc->soc->supports_interlacing) { 2235 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); 2236 value &= ~INTERLACE_ENABLE; 2237 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); 2238 } 2239 2240 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 2241 value &= ~DISP_CTRL_MODE_MASK; 2242 value |= DISP_CTRL_MODE_C_DISPLAY; 2243 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 2244 2245 if (!dc->soc->has_nvdisplay) { 2246 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 2247 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 2248 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; 2249 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 2250 } 2251 2252 /* enable underflow reporting and display red for missing pixels */ 2253 if (dc->soc->has_nvdisplay) { 2254 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE; 2255 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW); 2256 } 2257 2258 if (dc->rgb) { 2259 /* XXX: parameterize? */ 2260 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE; 2261 tegra_dc_writel(dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS); 2262 } 2263 2264 tegra_dc_commit(dc); 2265 2266 drm_crtc_vblank_on(crtc); 2267 } 2268 2269 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, 2270 struct drm_atomic_state *state) 2271 { 2272 unsigned long flags; 2273 2274 tegra_crtc_update_memory_bandwidth(crtc, state, true); 2275 2276 if (crtc->state->event) { 2277 spin_lock_irqsave(&crtc->dev->event_lock, flags); 2278 2279 if (drm_crtc_vblank_get(crtc) != 0) 2280 drm_crtc_send_vblank_event(crtc, crtc->state->event); 2281 else 2282 drm_crtc_arm_vblank_event(crtc, crtc->state->event); 2283 2284 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 2285 2286 crtc->state->event = NULL; 2287 } 2288 } 2289 2290 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, 2291 struct drm_atomic_state *state) 2292 { 2293 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 2294 crtc); 2295 struct tegra_dc_state *dc_state = to_dc_state(crtc_state); 2296 struct tegra_dc *dc = to_tegra_dc(crtc); 2297 u32 value; 2298 2299 value = dc_state->planes << 8 | GENERAL_UPDATE; 2300 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 2301 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 2302 2303 value = dc_state->planes | GENERAL_ACT_REQ; 2304 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 2305 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 2306 } 2307 2308 static bool tegra_plane_is_cursor(const struct drm_plane_state *state) 2309 { 2310 const struct tegra_dc_soc_info *soc = to_tegra_dc(state->crtc)->soc; 2311 const struct drm_format_info *fmt = state->fb->format; 2312 unsigned int src_w = drm_rect_width(&state->src) >> 16; 2313 unsigned int dst_w = drm_rect_width(&state->dst); 2314 2315 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) 2316 return false; 2317 2318 if (soc->supports_cursor) 2319 return true; 2320 2321 if (src_w != dst_w || fmt->num_planes != 1 || src_w * fmt->cpp[0] > 256) 2322 return false; 2323 2324 return true; 2325 } 2326 2327 static unsigned long 2328 tegra_plane_overlap_mask(struct drm_crtc_state *state, 2329 const struct drm_plane_state *plane_state) 2330 { 2331 const struct drm_plane_state *other_state; 2332 const struct tegra_plane *tegra; 2333 unsigned long overlap_mask = 0; 2334 struct drm_plane *plane; 2335 struct drm_rect rect; 2336 2337 if (!plane_state->visible || !plane_state->fb) 2338 return 0; 2339 2340 /* 2341 * Data-prefetch FIFO will easily help to overcome temporal memory 2342 * pressure if other plane overlaps with the cursor plane. 2343 */ 2344 if (tegra_plane_is_cursor(plane_state)) 2345 return 0; 2346 2347 drm_atomic_crtc_state_for_each_plane_state(plane, other_state, state) { 2348 rect = plane_state->dst; 2349 2350 tegra = to_tegra_plane(other_state->plane); 2351 2352 if (!other_state->visible || !other_state->fb) 2353 continue; 2354 2355 /* 2356 * Ignore cursor plane overlaps because it's not practical to 2357 * assume that it contributes to the bandwidth in overlapping 2358 * area if window width is small. 2359 */ 2360 if (tegra_plane_is_cursor(other_state)) 2361 continue; 2362 2363 if (drm_rect_intersect(&rect, &other_state->dst)) 2364 overlap_mask |= BIT(tegra->index); 2365 } 2366 2367 return overlap_mask; 2368 } 2369 2370 static int tegra_crtc_calculate_memory_bandwidth(struct drm_crtc *crtc, 2371 struct drm_atomic_state *state) 2372 { 2373 ulong overlap_mask[TEGRA_DC_LEGACY_PLANES_NUM] = {}, mask; 2374 u32 plane_peak_bw[TEGRA_DC_LEGACY_PLANES_NUM] = {}; 2375 bool all_planes_overlap_simultaneously = true; 2376 const struct tegra_plane_state *tegra_state; 2377 const struct drm_plane_state *plane_state; 2378 struct tegra_dc *dc = to_tegra_dc(crtc); 2379 const struct drm_crtc_state *old_state; 2380 struct drm_crtc_state *new_state; 2381 struct tegra_plane *tegra; 2382 struct drm_plane *plane; 2383 2384 /* 2385 * The nv-display uses shared planes. The algorithm below assumes 2386 * maximum 3 planes per-CRTC, this assumption isn't applicable to 2387 * the nv-display. Note that T124 support has additional windows, 2388 * but currently they aren't supported by the driver. 2389 */ 2390 if (dc->soc->has_nvdisplay) 2391 return 0; 2392 2393 new_state = drm_atomic_get_new_crtc_state(state, crtc); 2394 old_state = drm_atomic_get_old_crtc_state(state, crtc); 2395 2396 /* 2397 * For overlapping planes pixel's data is fetched for each plane at 2398 * the same time, hence bandwidths are accumulated in this case. 2399 * This needs to be taken into account for calculating total bandwidth 2400 * consumed by all planes. 2401 * 2402 * Here we get the overlapping state of each plane, which is a 2403 * bitmask of plane indices telling with what planes there is an 2404 * overlap. Note that bitmask[plane] includes BIT(plane) in order 2405 * to make further code nicer and simpler. 2406 */ 2407 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) { 2408 tegra_state = to_const_tegra_plane_state(plane_state); 2409 tegra = to_tegra_plane(plane); 2410 2411 if (WARN_ON_ONCE(tegra->index >= TEGRA_DC_LEGACY_PLANES_NUM)) 2412 return -EINVAL; 2413 2414 plane_peak_bw[tegra->index] = tegra_state->peak_memory_bandwidth; 2415 mask = tegra_plane_overlap_mask(new_state, plane_state); 2416 overlap_mask[tegra->index] = mask; 2417 2418 if (hweight_long(mask) != 3) 2419 all_planes_overlap_simultaneously = false; 2420 } 2421 2422 /* 2423 * Then we calculate maximum bandwidth of each plane state. 2424 * The bandwidth includes the plane BW + BW of the "simultaneously" 2425 * overlapping planes, where "simultaneously" means areas where DC 2426 * fetches from the planes simultaneously during of scan-out process. 2427 * 2428 * For example, if plane A overlaps with planes B and C, but B and C 2429 * don't overlap, then the peak bandwidth will be either in area where 2430 * A-and-B or A-and-C planes overlap. 2431 * 2432 * The plane_peak_bw[] contains peak memory bandwidth values of 2433 * each plane, this information is needed by interconnect provider 2434 * in order to set up latency allowance based on the peak BW, see 2435 * tegra_crtc_update_memory_bandwidth(). 2436 */ 2437 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) { 2438 u32 i, old_peak_bw, new_peak_bw, overlap_bw = 0; 2439 2440 /* 2441 * Note that plane's atomic check doesn't touch the 2442 * total_peak_memory_bandwidth of enabled plane, hence the 2443 * current state contains the old bandwidth state from the 2444 * previous CRTC commit. 2445 */ 2446 tegra_state = to_const_tegra_plane_state(plane_state); 2447 tegra = to_tegra_plane(plane); 2448 2449 for_each_set_bit(i, &overlap_mask[tegra->index], 3) { 2450 if (i == tegra->index) 2451 continue; 2452 2453 if (all_planes_overlap_simultaneously) 2454 overlap_bw += plane_peak_bw[i]; 2455 else 2456 overlap_bw = max(overlap_bw, plane_peak_bw[i]); 2457 } 2458 2459 new_peak_bw = plane_peak_bw[tegra->index] + overlap_bw; 2460 old_peak_bw = tegra_state->total_peak_memory_bandwidth; 2461 2462 /* 2463 * If plane's peak bandwidth changed (for example plane isn't 2464 * overlapped anymore) and plane isn't in the atomic state, 2465 * then add plane to the state in order to have the bandwidth 2466 * updated. 2467 */ 2468 if (old_peak_bw != new_peak_bw) { 2469 struct tegra_plane_state *new_tegra_state; 2470 struct drm_plane_state *new_plane_state; 2471 2472 new_plane_state = drm_atomic_get_plane_state(state, plane); 2473 if (IS_ERR(new_plane_state)) 2474 return PTR_ERR(new_plane_state); 2475 2476 new_tegra_state = to_tegra_plane_state(new_plane_state); 2477 new_tegra_state->total_peak_memory_bandwidth = new_peak_bw; 2478 } 2479 } 2480 2481 return 0; 2482 } 2483 2484 static int tegra_crtc_atomic_check(struct drm_crtc *crtc, 2485 struct drm_atomic_state *state) 2486 { 2487 int err; 2488 2489 err = tegra_crtc_calculate_memory_bandwidth(crtc, state); 2490 if (err) 2491 return err; 2492 2493 return 0; 2494 } 2495 2496 void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc, 2497 struct drm_atomic_state *state) 2498 { 2499 /* 2500 * Display bandwidth is allowed to go down only once hardware state 2501 * is known to be armed, i.e. state was committed and VBLANK event 2502 * received. 2503 */ 2504 tegra_crtc_update_memory_bandwidth(crtc, state, false); 2505 } 2506 2507 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { 2508 .atomic_check = tegra_crtc_atomic_check, 2509 .atomic_begin = tegra_crtc_atomic_begin, 2510 .atomic_flush = tegra_crtc_atomic_flush, 2511 .atomic_enable = tegra_crtc_atomic_enable, 2512 .atomic_disable = tegra_crtc_atomic_disable, 2513 }; 2514 2515 static irqreturn_t tegra_dc_irq(int irq, void *data) 2516 { 2517 struct tegra_dc *dc = data; 2518 unsigned long status; 2519 2520 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); 2521 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); 2522 2523 if (status & FRAME_END_INT) { 2524 /* 2525 dev_dbg(dc->dev, "%s(): frame end\n", __func__); 2526 */ 2527 dc->stats.frames_total++; 2528 dc->stats.frames++; 2529 } 2530 2531 if (status & VBLANK_INT) { 2532 /* 2533 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); 2534 */ 2535 drm_crtc_handle_vblank(&dc->base); 2536 dc->stats.vblank_total++; 2537 dc->stats.vblank++; 2538 } 2539 2540 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { 2541 /* 2542 dev_dbg(dc->dev, "%s(): underflow\n", __func__); 2543 */ 2544 dc->stats.underflow_total++; 2545 dc->stats.underflow++; 2546 } 2547 2548 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) { 2549 /* 2550 dev_dbg(dc->dev, "%s(): overflow\n", __func__); 2551 */ 2552 dc->stats.overflow_total++; 2553 dc->stats.overflow++; 2554 } 2555 2556 if (status & HEAD_UF_INT) { 2557 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); 2558 dc->stats.underflow_total++; 2559 dc->stats.underflow++; 2560 } 2561 2562 return IRQ_HANDLED; 2563 } 2564 2565 static bool tegra_dc_has_window_groups(struct tegra_dc *dc) 2566 { 2567 unsigned int i; 2568 2569 if (!dc->soc->wgrps) 2570 return true; 2571 2572 for (i = 0; i < dc->soc->num_wgrps; i++) { 2573 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; 2574 2575 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) 2576 return true; 2577 } 2578 2579 return false; 2580 } 2581 2582 static int tegra_dc_early_init(struct host1x_client *client) 2583 { 2584 struct drm_device *drm = dev_get_drvdata(client->host); 2585 struct tegra_drm *tegra = drm->dev_private; 2586 2587 tegra->num_crtcs++; 2588 2589 return 0; 2590 } 2591 2592 static int tegra_dc_init(struct host1x_client *client) 2593 { 2594 struct drm_device *drm = dev_get_drvdata(client->host); 2595 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED; 2596 struct tegra_dc *dc = host1x_client_to_dc(client); 2597 struct tegra_drm *tegra = drm->dev_private; 2598 struct drm_plane *primary = NULL; 2599 struct drm_plane *cursor = NULL; 2600 int err; 2601 2602 /* 2603 * DC has been reset by now, so VBLANK syncpoint can be released 2604 * for general use. 2605 */ 2606 host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe); 2607 2608 /* 2609 * XXX do not register DCs with no window groups because we cannot 2610 * assign a primary plane to them, which in turn will cause KMS to 2611 * crash. 2612 */ 2613 if (!tegra_dc_has_window_groups(dc)) 2614 return 0; 2615 2616 /* 2617 * Set the display hub as the host1x client parent for the display 2618 * controller. This is needed for the runtime reference counting that 2619 * ensures the display hub is always powered when any of the display 2620 * controllers are. 2621 */ 2622 if (dc->soc->has_nvdisplay) 2623 client->parent = &tegra->hub->client; 2624 2625 dc->syncpt = host1x_syncpt_request(client, flags); 2626 if (!dc->syncpt) 2627 dev_warn(dc->dev, "failed to allocate syncpoint\n"); 2628 2629 err = host1x_client_iommu_attach(client); 2630 if (err < 0 && err != -ENODEV) { 2631 dev_err(client->dev, "failed to attach to domain: %d\n", err); 2632 return err; 2633 } 2634 2635 if (dc->soc->wgrps) 2636 primary = tegra_dc_add_shared_planes(drm, dc); 2637 else 2638 primary = tegra_dc_add_planes(drm, dc); 2639 2640 if (IS_ERR(primary)) { 2641 err = PTR_ERR(primary); 2642 goto cleanup; 2643 } 2644 2645 if (dc->soc->supports_cursor) { 2646 cursor = tegra_dc_cursor_plane_create(drm, dc); 2647 if (IS_ERR(cursor)) { 2648 err = PTR_ERR(cursor); 2649 goto cleanup; 2650 } 2651 } else { 2652 /* dedicate one overlay to mouse cursor */ 2653 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true); 2654 if (IS_ERR(cursor)) { 2655 err = PTR_ERR(cursor); 2656 goto cleanup; 2657 } 2658 } 2659 2660 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, 2661 &tegra_crtc_funcs, NULL); 2662 if (err < 0) 2663 goto cleanup; 2664 2665 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); 2666 2667 /* 2668 * Keep track of the minimum pitch alignment across all display 2669 * controllers. 2670 */ 2671 if (dc->soc->pitch_align > tegra->pitch_align) 2672 tegra->pitch_align = dc->soc->pitch_align; 2673 2674 /* track maximum resolution */ 2675 if (dc->soc->has_nvdisplay) 2676 drm->mode_config.max_width = drm->mode_config.max_height = 16384; 2677 else 2678 drm->mode_config.max_width = drm->mode_config.max_height = 4096; 2679 2680 err = tegra_dc_rgb_init(drm, dc); 2681 if (err < 0 && err != -ENODEV) { 2682 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); 2683 goto cleanup; 2684 } 2685 2686 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, 2687 dev_name(dc->dev), dc); 2688 if (err < 0) { 2689 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, 2690 err); 2691 goto cleanup; 2692 } 2693 2694 /* 2695 * Inherit the DMA parameters (such as maximum segment size) from the 2696 * parent host1x device. 2697 */ 2698 client->dev->dma_parms = client->host->dma_parms; 2699 2700 return 0; 2701 2702 cleanup: 2703 if (!IS_ERR_OR_NULL(cursor)) 2704 drm_plane_cleanup(cursor); 2705 2706 if (!IS_ERR(primary)) 2707 drm_plane_cleanup(primary); 2708 2709 host1x_client_iommu_detach(client); 2710 host1x_syncpt_put(dc->syncpt); 2711 2712 return err; 2713 } 2714 2715 static int tegra_dc_exit(struct host1x_client *client) 2716 { 2717 struct tegra_dc *dc = host1x_client_to_dc(client); 2718 int err; 2719 2720 if (!tegra_dc_has_window_groups(dc)) 2721 return 0; 2722 2723 /* avoid a dangling pointer just in case this disappears */ 2724 client->dev->dma_parms = NULL; 2725 2726 devm_free_irq(dc->dev, dc->irq, dc); 2727 2728 err = tegra_dc_rgb_exit(dc); 2729 if (err) { 2730 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); 2731 return err; 2732 } 2733 2734 host1x_client_iommu_detach(client); 2735 host1x_syncpt_put(dc->syncpt); 2736 2737 return 0; 2738 } 2739 2740 static int tegra_dc_late_exit(struct host1x_client *client) 2741 { 2742 struct drm_device *drm = dev_get_drvdata(client->host); 2743 struct tegra_drm *tegra = drm->dev_private; 2744 2745 tegra->num_crtcs--; 2746 2747 return 0; 2748 } 2749 2750 static int tegra_dc_runtime_suspend(struct host1x_client *client) 2751 { 2752 struct tegra_dc *dc = host1x_client_to_dc(client); 2753 struct device *dev = client->dev; 2754 int err; 2755 2756 err = reset_control_assert(dc->rst); 2757 if (err < 0) { 2758 dev_err(dev, "failed to assert reset: %d\n", err); 2759 return err; 2760 } 2761 2762 if (dc->soc->has_powergate) 2763 tegra_powergate_power_off(dc->powergate); 2764 2765 clk_disable_unprepare(dc->clk); 2766 pm_runtime_put_sync(dev); 2767 2768 return 0; 2769 } 2770 2771 static int tegra_dc_runtime_resume(struct host1x_client *client) 2772 { 2773 struct tegra_dc *dc = host1x_client_to_dc(client); 2774 struct device *dev = client->dev; 2775 int err; 2776 2777 err = pm_runtime_resume_and_get(dev); 2778 if (err < 0) { 2779 dev_err(dev, "failed to get runtime PM: %d\n", err); 2780 return err; 2781 } 2782 2783 if (dc->soc->has_powergate) { 2784 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, 2785 dc->rst); 2786 if (err < 0) { 2787 dev_err(dev, "failed to power partition: %d\n", err); 2788 goto put_rpm; 2789 } 2790 } else { 2791 err = clk_prepare_enable(dc->clk); 2792 if (err < 0) { 2793 dev_err(dev, "failed to enable clock: %d\n", err); 2794 goto put_rpm; 2795 } 2796 2797 err = reset_control_deassert(dc->rst); 2798 if (err < 0) { 2799 dev_err(dev, "failed to deassert reset: %d\n", err); 2800 goto disable_clk; 2801 } 2802 } 2803 2804 return 0; 2805 2806 disable_clk: 2807 clk_disable_unprepare(dc->clk); 2808 put_rpm: 2809 pm_runtime_put_sync(dev); 2810 return err; 2811 } 2812 2813 static const struct host1x_client_ops dc_client_ops = { 2814 .early_init = tegra_dc_early_init, 2815 .init = tegra_dc_init, 2816 .exit = tegra_dc_exit, 2817 .late_exit = tegra_dc_late_exit, 2818 .suspend = tegra_dc_runtime_suspend, 2819 .resume = tegra_dc_runtime_resume, 2820 }; 2821 2822 static const struct tegra_dc_soc_info tegra20_dc_soc_info = { 2823 .supports_background_color = false, 2824 .supports_interlacing = false, 2825 .supports_cursor = false, 2826 .supports_block_linear = false, 2827 .supports_sector_layout = false, 2828 .has_legacy_blending = true, 2829 .pitch_align = 8, 2830 .has_powergate = false, 2831 .coupled_pm = true, 2832 .has_nvdisplay = false, 2833 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 2834 .primary_formats = tegra20_primary_formats, 2835 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 2836 .overlay_formats = tegra20_overlay_formats, 2837 .modifiers = tegra20_modifiers, 2838 .has_win_a_without_filters = true, 2839 .has_win_b_vfilter_mem_client = true, 2840 .has_win_c_without_vert_filter = true, 2841 .plane_tiled_memory_bandwidth_x2 = false, 2842 .has_pll_d2_out0 = false, 2843 }; 2844 2845 static const struct tegra_dc_soc_info tegra30_dc_soc_info = { 2846 .supports_background_color = false, 2847 .supports_interlacing = false, 2848 .supports_cursor = false, 2849 .supports_block_linear = false, 2850 .supports_sector_layout = false, 2851 .has_legacy_blending = true, 2852 .pitch_align = 8, 2853 .has_powergate = false, 2854 .coupled_pm = false, 2855 .has_nvdisplay = false, 2856 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 2857 .primary_formats = tegra20_primary_formats, 2858 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 2859 .overlay_formats = tegra20_overlay_formats, 2860 .modifiers = tegra20_modifiers, 2861 .has_win_a_without_filters = false, 2862 .has_win_b_vfilter_mem_client = true, 2863 .has_win_c_without_vert_filter = false, 2864 .plane_tiled_memory_bandwidth_x2 = true, 2865 .has_pll_d2_out0 = true, 2866 }; 2867 2868 static const struct tegra_dc_soc_info tegra114_dc_soc_info = { 2869 .supports_background_color = false, 2870 .supports_interlacing = false, 2871 .supports_cursor = false, 2872 .supports_block_linear = false, 2873 .supports_sector_layout = false, 2874 .has_legacy_blending = true, 2875 .pitch_align = 64, 2876 .has_powergate = true, 2877 .coupled_pm = false, 2878 .has_nvdisplay = false, 2879 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 2880 .primary_formats = tegra114_primary_formats, 2881 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 2882 .overlay_formats = tegra114_overlay_formats, 2883 .modifiers = tegra20_modifiers, 2884 .has_win_a_without_filters = false, 2885 .has_win_b_vfilter_mem_client = false, 2886 .has_win_c_without_vert_filter = false, 2887 .plane_tiled_memory_bandwidth_x2 = true, 2888 .has_pll_d2_out0 = true, 2889 }; 2890 2891 static const struct tegra_dc_soc_info tegra124_dc_soc_info = { 2892 .supports_background_color = true, 2893 .supports_interlacing = true, 2894 .supports_cursor = true, 2895 .supports_block_linear = true, 2896 .supports_sector_layout = false, 2897 .has_legacy_blending = false, 2898 .pitch_align = 64, 2899 .has_powergate = true, 2900 .coupled_pm = false, 2901 .has_nvdisplay = false, 2902 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats), 2903 .primary_formats = tegra124_primary_formats, 2904 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats), 2905 .overlay_formats = tegra124_overlay_formats, 2906 .modifiers = tegra124_modifiers, 2907 .has_win_a_without_filters = false, 2908 .has_win_b_vfilter_mem_client = false, 2909 .has_win_c_without_vert_filter = false, 2910 .plane_tiled_memory_bandwidth_x2 = false, 2911 .has_pll_d2_out0 = true, 2912 }; 2913 2914 static const struct tegra_dc_soc_info tegra210_dc_soc_info = { 2915 .supports_background_color = true, 2916 .supports_interlacing = true, 2917 .supports_cursor = true, 2918 .supports_block_linear = true, 2919 .supports_sector_layout = false, 2920 .has_legacy_blending = false, 2921 .pitch_align = 64, 2922 .has_powergate = true, 2923 .coupled_pm = false, 2924 .has_nvdisplay = false, 2925 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 2926 .primary_formats = tegra114_primary_formats, 2927 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 2928 .overlay_formats = tegra114_overlay_formats, 2929 .modifiers = tegra124_modifiers, 2930 .has_win_a_without_filters = false, 2931 .has_win_b_vfilter_mem_client = false, 2932 .has_win_c_without_vert_filter = false, 2933 .plane_tiled_memory_bandwidth_x2 = false, 2934 .has_pll_d2_out0 = true, 2935 }; 2936 2937 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = { 2938 { 2939 .index = 0, 2940 .dc = 0, 2941 .windows = (const unsigned int[]) { 0 }, 2942 .num_windows = 1, 2943 }, { 2944 .index = 1, 2945 .dc = 1, 2946 .windows = (const unsigned int[]) { 1 }, 2947 .num_windows = 1, 2948 }, { 2949 .index = 2, 2950 .dc = 1, 2951 .windows = (const unsigned int[]) { 2 }, 2952 .num_windows = 1, 2953 }, { 2954 .index = 3, 2955 .dc = 2, 2956 .windows = (const unsigned int[]) { 3 }, 2957 .num_windows = 1, 2958 }, { 2959 .index = 4, 2960 .dc = 2, 2961 .windows = (const unsigned int[]) { 4 }, 2962 .num_windows = 1, 2963 }, { 2964 .index = 5, 2965 .dc = 2, 2966 .windows = (const unsigned int[]) { 5 }, 2967 .num_windows = 1, 2968 }, 2969 }; 2970 2971 static const struct tegra_dc_soc_info tegra186_dc_soc_info = { 2972 .supports_background_color = true, 2973 .supports_interlacing = true, 2974 .supports_cursor = true, 2975 .supports_block_linear = true, 2976 .supports_sector_layout = false, 2977 .has_legacy_blending = false, 2978 .pitch_align = 64, 2979 .has_powergate = false, 2980 .coupled_pm = false, 2981 .has_nvdisplay = true, 2982 .wgrps = tegra186_dc_wgrps, 2983 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), 2984 .plane_tiled_memory_bandwidth_x2 = false, 2985 .has_pll_d2_out0 = false, 2986 }; 2987 2988 static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = { 2989 { 2990 .index = 0, 2991 .dc = 0, 2992 .windows = (const unsigned int[]) { 0 }, 2993 .num_windows = 1, 2994 }, { 2995 .index = 1, 2996 .dc = 1, 2997 .windows = (const unsigned int[]) { 1 }, 2998 .num_windows = 1, 2999 }, { 3000 .index = 2, 3001 .dc = 1, 3002 .windows = (const unsigned int[]) { 2 }, 3003 .num_windows = 1, 3004 }, { 3005 .index = 3, 3006 .dc = 2, 3007 .windows = (const unsigned int[]) { 3 }, 3008 .num_windows = 1, 3009 }, { 3010 .index = 4, 3011 .dc = 2, 3012 .windows = (const unsigned int[]) { 4 }, 3013 .num_windows = 1, 3014 }, { 3015 .index = 5, 3016 .dc = 2, 3017 .windows = (const unsigned int[]) { 5 }, 3018 .num_windows = 1, 3019 }, 3020 }; 3021 3022 static const struct tegra_dc_soc_info tegra194_dc_soc_info = { 3023 .supports_background_color = true, 3024 .supports_interlacing = true, 3025 .supports_cursor = true, 3026 .supports_block_linear = true, 3027 .supports_sector_layout = true, 3028 .has_legacy_blending = false, 3029 .pitch_align = 64, 3030 .has_powergate = false, 3031 .coupled_pm = false, 3032 .has_nvdisplay = true, 3033 .wgrps = tegra194_dc_wgrps, 3034 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps), 3035 .plane_tiled_memory_bandwidth_x2 = false, 3036 .has_pll_d2_out0 = false, 3037 }; 3038 3039 static const struct of_device_id tegra_dc_of_match[] = { 3040 { 3041 .compatible = "nvidia,tegra194-dc", 3042 .data = &tegra194_dc_soc_info, 3043 }, { 3044 .compatible = "nvidia,tegra186-dc", 3045 .data = &tegra186_dc_soc_info, 3046 }, { 3047 .compatible = "nvidia,tegra210-dc", 3048 .data = &tegra210_dc_soc_info, 3049 }, { 3050 .compatible = "nvidia,tegra124-dc", 3051 .data = &tegra124_dc_soc_info, 3052 }, { 3053 .compatible = "nvidia,tegra114-dc", 3054 .data = &tegra114_dc_soc_info, 3055 }, { 3056 .compatible = "nvidia,tegra30-dc", 3057 .data = &tegra30_dc_soc_info, 3058 }, { 3059 .compatible = "nvidia,tegra20-dc", 3060 .data = &tegra20_dc_soc_info, 3061 }, { 3062 /* sentinel */ 3063 } 3064 }; 3065 MODULE_DEVICE_TABLE(of, tegra_dc_of_match); 3066 3067 static int tegra_dc_parse_dt(struct tegra_dc *dc) 3068 { 3069 struct device_node *np; 3070 u32 value = 0; 3071 int err; 3072 3073 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); 3074 if (err < 0) { 3075 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); 3076 3077 /* 3078 * If the nvidia,head property isn't present, try to find the 3079 * correct head number by looking up the position of this 3080 * display controller's node within the device tree. Assuming 3081 * that the nodes are ordered properly in the DTS file and 3082 * that the translation into a flattened device tree blob 3083 * preserves that ordering this will actually yield the right 3084 * head number. 3085 * 3086 * If those assumptions don't hold, this will still work for 3087 * cases where only a single display controller is used. 3088 */ 3089 for_each_matching_node(np, tegra_dc_of_match) { 3090 if (np == dc->dev->of_node) { 3091 of_node_put(np); 3092 break; 3093 } 3094 3095 value++; 3096 } 3097 } 3098 3099 dc->pipe = value; 3100 3101 return 0; 3102 } 3103 3104 static int tegra_dc_match_by_pipe(struct device *dev, const void *data) 3105 { 3106 struct tegra_dc *dc = dev_get_drvdata(dev); 3107 unsigned int pipe = (unsigned long)(void *)data; 3108 3109 return dc->pipe == pipe; 3110 } 3111 3112 static int tegra_dc_couple(struct tegra_dc *dc) 3113 { 3114 /* 3115 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to 3116 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND / 3117 * POWER_CONTROL registers during CRTC enabling. 3118 */ 3119 if (dc->soc->coupled_pm && dc->pipe == 1) { 3120 struct device *companion; 3121 struct tegra_dc *parent; 3122 3123 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0, 3124 tegra_dc_match_by_pipe); 3125 if (!companion) 3126 return -EPROBE_DEFER; 3127 3128 parent = dev_get_drvdata(companion); 3129 dc->client.parent = &parent->client; 3130 3131 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion)); 3132 } 3133 3134 return 0; 3135 } 3136 3137 static int tegra_dc_init_opp_table(struct tegra_dc *dc) 3138 { 3139 struct tegra_core_opp_params opp_params = {}; 3140 int err; 3141 3142 err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params); 3143 if (err && err != -ENODEV) 3144 return err; 3145 3146 if (err) 3147 dc->has_opp_table = false; 3148 else 3149 dc->has_opp_table = true; 3150 3151 return 0; 3152 } 3153 3154 static int tegra_dc_probe(struct platform_device *pdev) 3155 { 3156 u64 dma_mask = dma_get_mask(pdev->dev.parent); 3157 struct tegra_dc *dc; 3158 int err; 3159 3160 err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask); 3161 if (err < 0) { 3162 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 3163 return err; 3164 } 3165 3166 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); 3167 if (!dc) 3168 return -ENOMEM; 3169 3170 dc->soc = of_device_get_match_data(&pdev->dev); 3171 3172 INIT_LIST_HEAD(&dc->list); 3173 dc->dev = &pdev->dev; 3174 3175 err = tegra_dc_parse_dt(dc); 3176 if (err < 0) 3177 return err; 3178 3179 err = tegra_dc_couple(dc); 3180 if (err < 0) 3181 return err; 3182 3183 dc->clk = devm_clk_get(&pdev->dev, NULL); 3184 if (IS_ERR(dc->clk)) { 3185 dev_err(&pdev->dev, "failed to get clock\n"); 3186 return PTR_ERR(dc->clk); 3187 } 3188 3189 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); 3190 if (IS_ERR(dc->rst)) { 3191 dev_err(&pdev->dev, "failed to get reset\n"); 3192 return PTR_ERR(dc->rst); 3193 } 3194 3195 /* assert reset and disable clock */ 3196 err = clk_prepare_enable(dc->clk); 3197 if (err < 0) 3198 return err; 3199 3200 usleep_range(2000, 4000); 3201 3202 err = reset_control_assert(dc->rst); 3203 if (err < 0) 3204 return err; 3205 3206 usleep_range(2000, 4000); 3207 3208 clk_disable_unprepare(dc->clk); 3209 3210 if (dc->soc->has_powergate) { 3211 if (dc->pipe == 0) 3212 dc->powergate = TEGRA_POWERGATE_DIS; 3213 else 3214 dc->powergate = TEGRA_POWERGATE_DISB; 3215 3216 tegra_powergate_power_off(dc->powergate); 3217 } 3218 3219 err = tegra_dc_init_opp_table(dc); 3220 if (err < 0) 3221 return err; 3222 3223 dc->regs = devm_platform_ioremap_resource(pdev, 0); 3224 if (IS_ERR(dc->regs)) 3225 return PTR_ERR(dc->regs); 3226 3227 dc->irq = platform_get_irq(pdev, 0); 3228 if (dc->irq < 0) 3229 return -ENXIO; 3230 3231 err = tegra_dc_rgb_probe(dc); 3232 if (err < 0 && err != -ENODEV) 3233 return dev_err_probe(&pdev->dev, err, 3234 "failed to probe RGB output\n"); 3235 3236 platform_set_drvdata(pdev, dc); 3237 pm_runtime_enable(&pdev->dev); 3238 3239 INIT_LIST_HEAD(&dc->client.list); 3240 dc->client.ops = &dc_client_ops; 3241 dc->client.dev = &pdev->dev; 3242 3243 err = host1x_client_register(&dc->client); 3244 if (err < 0) { 3245 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 3246 err); 3247 goto disable_pm; 3248 } 3249 3250 return 0; 3251 3252 disable_pm: 3253 pm_runtime_disable(&pdev->dev); 3254 tegra_dc_rgb_remove(dc); 3255 3256 return err; 3257 } 3258 3259 static int tegra_dc_remove(struct platform_device *pdev) 3260 { 3261 struct tegra_dc *dc = platform_get_drvdata(pdev); 3262 int err; 3263 3264 err = host1x_client_unregister(&dc->client); 3265 if (err < 0) { 3266 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 3267 err); 3268 return err; 3269 } 3270 3271 err = tegra_dc_rgb_remove(dc); 3272 if (err < 0) { 3273 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); 3274 return err; 3275 } 3276 3277 pm_runtime_disable(&pdev->dev); 3278 3279 return 0; 3280 } 3281 3282 struct platform_driver tegra_dc_driver = { 3283 .driver = { 3284 .name = "tegra-dc", 3285 .of_match_table = tegra_dc_of_match, 3286 }, 3287 .probe = tegra_dc_probe, 3288 .remove = tegra_dc_remove, 3289 }; 3290