xref: /openbmc/linux/drivers/gpu/drm/sun4i/sun4i_tcon.h (revision 67f4aeb2b41a0629abde3794d463547f60b0cbdd)
12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
29026e0d1SMaxime Ripard /*
39026e0d1SMaxime Ripard  * Copyright (C) 2015 Free Electrons
49026e0d1SMaxime Ripard  * Copyright (C) 2015 NextThing Co
59026e0d1SMaxime Ripard  *
69026e0d1SMaxime Ripard  * Boris Brezillon <boris.brezillon@free-electrons.com>
79026e0d1SMaxime Ripard  * Maxime Ripard <maxime.ripard@free-electrons.com>
89026e0d1SMaxime Ripard  */
99026e0d1SMaxime Ripard 
109026e0d1SMaxime Ripard #ifndef __SUN4I_TCON_H__
119026e0d1SMaxime Ripard #define __SUN4I_TCON_H__
129026e0d1SMaxime Ripard 
139026e0d1SMaxime Ripard #include <drm/drm_crtc.h>
149026e0d1SMaxime Ripard 
159026e0d1SMaxime Ripard #include <linux/kernel.h>
1680a58240SChen-Yu Tsai #include <linux/list.h>
179026e0d1SMaxime Ripard #include <linux/reset.h>
189026e0d1SMaxime Ripard 
199026e0d1SMaxime Ripard #define SUN4I_TCON_GCTL_REG			0x0
209026e0d1SMaxime Ripard #define SUN4I_TCON_GCTL_TCON_ENABLE			BIT(31)
219026e0d1SMaxime Ripard #define SUN4I_TCON_GCTL_IOMAP_MASK			BIT(0)
229026e0d1SMaxime Ripard #define SUN4I_TCON_GCTL_IOMAP_TCON1			(1 << 0)
239026e0d1SMaxime Ripard #define SUN4I_TCON_GCTL_IOMAP_TCON0			(0 << 0)
249026e0d1SMaxime Ripard 
259026e0d1SMaxime Ripard #define SUN4I_TCON_GINT0_REG			0x4
269026e0d1SMaxime Ripard #define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe)		BIT(31 - (pipe))
27a493ceaeSMaxime Ripard #define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE	BIT(27)
28a493ceaeSMaxime Ripard #define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_ENABLE	BIT(26)
299026e0d1SMaxime Ripard #define SUN4I_TCON_GINT0_VBLANK_INT(pipe)		BIT(15 - (pipe))
30a493ceaeSMaxime Ripard #define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT		BIT(11)
31a493ceaeSMaxime Ripard #define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_INT		BIT(10)
329026e0d1SMaxime Ripard 
339026e0d1SMaxime Ripard #define SUN4I_TCON_GINT1_REG			0x8
34a08fc7c8SMaxime Ripard 
359026e0d1SMaxime Ripard #define SUN4I_TCON_FRM_CTL_REG			0x10
365869d90bSChen-Yu Tsai #define SUN4I_TCON0_FRM_CTL_EN				BIT(31)
375869d90bSChen-Yu Tsai #define SUN4I_TCON0_FRM_CTL_MODE_R			BIT(6)
385869d90bSChen-Yu Tsai #define SUN4I_TCON0_FRM_CTL_MODE_G			BIT(5)
395869d90bSChen-Yu Tsai #define SUN4I_TCON0_FRM_CTL_MODE_B			BIT(4)
40a08fc7c8SMaxime Ripard 
415869d90bSChen-Yu Tsai #define SUN4I_TCON0_FRM_SEED_PR_REG		0x14
425869d90bSChen-Yu Tsai #define SUN4I_TCON0_FRM_SEED_PG_REG		0x18
435869d90bSChen-Yu Tsai #define SUN4I_TCON0_FRM_SEED_PB_REG		0x1c
445869d90bSChen-Yu Tsai #define SUN4I_TCON0_FRM_SEED_LR_REG		0x20
455869d90bSChen-Yu Tsai #define SUN4I_TCON0_FRM_SEED_LG_REG		0x24
465869d90bSChen-Yu Tsai #define SUN4I_TCON0_FRM_SEED_LB_REG		0x28
475869d90bSChen-Yu Tsai #define SUN4I_TCON0_FRM_TBL0_REG		0x2c
485869d90bSChen-Yu Tsai #define SUN4I_TCON0_FRM_TBL1_REG		0x30
495869d90bSChen-Yu Tsai #define SUN4I_TCON0_FRM_TBL2_REG		0x34
505869d90bSChen-Yu Tsai #define SUN4I_TCON0_FRM_TBL3_REG		0x38
519026e0d1SMaxime Ripard 
529026e0d1SMaxime Ripard #define SUN4I_TCON0_CTL_REG			0x40
539026e0d1SMaxime Ripard #define SUN4I_TCON0_CTL_TCON_ENABLE			BIT(31)
54a08fc7c8SMaxime Ripard #define SUN4I_TCON0_CTL_IF_MASK				GENMASK(25, 24)
55a08fc7c8SMaxime Ripard #define SUN4I_TCON0_CTL_IF_8080				(1 << 24)
569026e0d1SMaxime Ripard #define SUN4I_TCON0_CTL_CLK_DELAY_MASK			GENMASK(8, 4)
579026e0d1SMaxime Ripard #define SUN4I_TCON0_CTL_CLK_DELAY(delay)		((delay << 4) & SUN4I_TCON0_CTL_CLK_DELAY_MASK)
5827e18de7SChen-Yu Tsai #define SUN4I_TCON0_CTL_SRC_SEL_MASK			GENMASK(2, 0)
599026e0d1SMaxime Ripard 
609026e0d1SMaxime Ripard #define SUN4I_TCON0_DCLK_REG			0x44
619026e0d1SMaxime Ripard #define SUN4I_TCON0_DCLK_GATE_BIT			(31)
629026e0d1SMaxime Ripard #define SUN4I_TCON0_DCLK_DIV_SHIFT			(0)
639026e0d1SMaxime Ripard #define SUN4I_TCON0_DCLK_DIV_WIDTH			(7)
649026e0d1SMaxime Ripard 
659026e0d1SMaxime Ripard #define SUN4I_TCON0_BASIC0_REG			0x48
669026e0d1SMaxime Ripard #define SUN4I_TCON0_BASIC0_X(width)			((((width) - 1) & 0xfff) << 16)
679026e0d1SMaxime Ripard #define SUN4I_TCON0_BASIC0_Y(height)			(((height) - 1) & 0xfff)
689026e0d1SMaxime Ripard 
699026e0d1SMaxime Ripard #define SUN4I_TCON0_BASIC1_REG			0x4c
709026e0d1SMaxime Ripard #define SUN4I_TCON0_BASIC1_H_TOTAL(total)		((((total) - 1) & 0x1fff) << 16)
719026e0d1SMaxime Ripard #define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp)		(((bp) - 1) & 0xfff)
729026e0d1SMaxime Ripard 
739026e0d1SMaxime Ripard #define SUN4I_TCON0_BASIC2_REG			0x50
74a88cbbd4SMaxime Ripard #define SUN4I_TCON0_BASIC2_V_TOTAL(total)		(((total) & 0x1fff) << 16)
759026e0d1SMaxime Ripard #define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp)		(((bp) - 1) & 0xfff)
769026e0d1SMaxime Ripard 
779026e0d1SMaxime Ripard #define SUN4I_TCON0_BASIC3_REG			0x54
789026e0d1SMaxime Ripard #define SUN4I_TCON0_BASIC3_H_SYNC(width)		((((width) - 1) & 0x7ff) << 16)
799026e0d1SMaxime Ripard #define SUN4I_TCON0_BASIC3_V_SYNC(height)		(((height) - 1) & 0x7ff)
809026e0d1SMaxime Ripard 
819026e0d1SMaxime Ripard #define SUN4I_TCON0_HV_IF_REG			0x58
82a08fc7c8SMaxime Ripard 
839026e0d1SMaxime Ripard #define SUN4I_TCON0_CPU_IF_REG			0x60
84a08fc7c8SMaxime Ripard #define SUN4I_TCON0_CPU_IF_MODE_MASK			GENMASK(31, 28)
85a08fc7c8SMaxime Ripard #define SUN4I_TCON0_CPU_IF_MODE_DSI			(1 << 28)
86a08fc7c8SMaxime Ripard #define SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH		BIT(16)
87a08fc7c8SMaxime Ripard #define SUN4I_TCON0_CPU_IF_TRI_FIFO_EN			BIT(2)
88a08fc7c8SMaxime Ripard #define SUN4I_TCON0_CPU_IF_TRI_EN			BIT(0)
89a08fc7c8SMaxime Ripard 
909026e0d1SMaxime Ripard #define SUN4I_TCON0_CPU_WR_REG			0x64
919026e0d1SMaxime Ripard #define SUN4I_TCON0_CPU_RD0_REG			0x68
929026e0d1SMaxime Ripard #define SUN4I_TCON0_CPU_RDA_REG			0x6c
939026e0d1SMaxime Ripard #define SUN4I_TCON0_TTL0_REG			0x70
949026e0d1SMaxime Ripard #define SUN4I_TCON0_TTL1_REG			0x74
959026e0d1SMaxime Ripard #define SUN4I_TCON0_TTL2_REG			0x78
969026e0d1SMaxime Ripard #define SUN4I_TCON0_TTL3_REG			0x7c
979026e0d1SMaxime Ripard #define SUN4I_TCON0_TTL4_REG			0x80
98a0c1214eSMaxime Ripard 
999026e0d1SMaxime Ripard #define SUN4I_TCON0_LVDS_IF_REG			0x84
100a0c1214eSMaxime Ripard #define SUN4I_TCON0_LVDS_IF_EN				BIT(31)
101a0c1214eSMaxime Ripard #define SUN4I_TCON0_LVDS_IF_BITWIDTH_MASK		BIT(26)
102a0c1214eSMaxime Ripard #define SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS		(1 << 26)
103a0c1214eSMaxime Ripard #define SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS		(0 << 26)
104a0c1214eSMaxime Ripard #define SUN4I_TCON0_LVDS_IF_CLK_SEL_MASK		BIT(20)
105a0c1214eSMaxime Ripard #define SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0		(1 << 20)
106a0c1214eSMaxime Ripard #define SUN4I_TCON0_LVDS_IF_CLK_POL_MASK		BIT(4)
107a0c1214eSMaxime Ripard #define SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL		(1 << 4)
108a0c1214eSMaxime Ripard #define SUN4I_TCON0_LVDS_IF_CLK_POL_INV			(0 << 4)
109a0c1214eSMaxime Ripard #define SUN4I_TCON0_LVDS_IF_DATA_POL_MASK		GENMASK(3, 0)
110a0c1214eSMaxime Ripard #define SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL		(0xf)
111a0c1214eSMaxime Ripard #define SUN4I_TCON0_LVDS_IF_DATA_POL_INV		(0)
112a0c1214eSMaxime Ripard 
1139026e0d1SMaxime Ripard #define SUN4I_TCON0_IO_POL_REG			0x88
1149026e0d1SMaxime Ripard #define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase)		((phase & 3) << 28)
11565bf2d54SPaul Kocialkowski #define SUN4I_TCON0_IO_POL_DE_NEGATIVE			BIT(27)
116*67f4aeb2SGiulio Benetti #define SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE		BIT(26)
1179026e0d1SMaxime Ripard #define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE		BIT(25)
1189026e0d1SMaxime Ripard #define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE		BIT(24)
1199026e0d1SMaxime Ripard 
1209026e0d1SMaxime Ripard #define SUN4I_TCON0_IO_TRI_REG			0x8c
1219026e0d1SMaxime Ripard #define SUN4I_TCON0_IO_TRI_HSYNC_DISABLE		BIT(25)
1229026e0d1SMaxime Ripard #define SUN4I_TCON0_IO_TRI_VSYNC_DISABLE		BIT(24)
1239026e0d1SMaxime Ripard #define SUN4I_TCON0_IO_TRI_DATA_PINS_DISABLE(pins)	GENMASK(pins, 0)
1249026e0d1SMaxime Ripard 
1259026e0d1SMaxime Ripard #define SUN4I_TCON1_CTL_REG			0x90
1269026e0d1SMaxime Ripard #define SUN4I_TCON1_CTL_TCON_ENABLE			BIT(31)
1279026e0d1SMaxime Ripard #define SUN4I_TCON1_CTL_INTERLACE_ENABLE		BIT(20)
1289026e0d1SMaxime Ripard #define SUN4I_TCON1_CTL_CLK_DELAY_MASK			GENMASK(8, 4)
1299026e0d1SMaxime Ripard #define SUN4I_TCON1_CTL_CLK_DELAY(delay)		((delay << 4) & SUN4I_TCON1_CTL_CLK_DELAY_MASK)
13027e18de7SChen-Yu Tsai #define SUN4I_TCON1_CTL_SRC_SEL_MASK			GENMASK(1, 0)
1319026e0d1SMaxime Ripard 
1329026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC0_REG			0x94
1339026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC0_X(width)			((((width) - 1) & 0xfff) << 16)
1349026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC0_Y(height)			(((height) - 1) & 0xfff)
1359026e0d1SMaxime Ripard 
1369026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC1_REG			0x98
1379026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC1_X(width)			((((width) - 1) & 0xfff) << 16)
1389026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC1_Y(height)			(((height) - 1) & 0xfff)
1399026e0d1SMaxime Ripard 
1409026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC2_REG			0x9c
1419026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC2_X(width)			((((width) - 1) & 0xfff) << 16)
1429026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC2_Y(height)			(((height) - 1) & 0xfff)
1439026e0d1SMaxime Ripard 
1449026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC3_REG			0xa0
1459026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC3_H_TOTAL(total)		((((total) - 1) & 0x1fff) << 16)
1469026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC3_H_BACKPORCH(bp)		(((bp) - 1) & 0xfff)
1479026e0d1SMaxime Ripard 
1489026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC4_REG			0xa4
1499026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC4_V_TOTAL(total)		(((total) & 0x1fff) << 16)
1509026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC4_V_BACKPORCH(bp)		(((bp) - 1) & 0xfff)
1519026e0d1SMaxime Ripard 
1529026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC5_REG			0xa8
1539026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC5_H_SYNC(width)		((((width) - 1) & 0x3ff) << 16)
1549026e0d1SMaxime Ripard #define SUN4I_TCON1_BASIC5_V_SYNC(height)		(((height) - 1) & 0x3ff)
1559026e0d1SMaxime Ripard 
1569026e0d1SMaxime Ripard #define SUN4I_TCON1_IO_POL_REG			0xf0
1579026e0d1SMaxime Ripard #define SUN4I_TCON1_IO_TRI_REG			0xf4
158a08fc7c8SMaxime Ripard 
159a08fc7c8SMaxime Ripard #define SUN4I_TCON_ECC_FIFO_REG			0xf8
160a08fc7c8SMaxime Ripard #define SUN4I_TCON_ECC_FIFO_EN				BIT(3)
161a08fc7c8SMaxime Ripard 
1629026e0d1SMaxime Ripard #define SUN4I_TCON_CEU_CTL_REG			0x100
1639026e0d1SMaxime Ripard #define SUN4I_TCON_CEU_MUL_RR_REG		0x110
1649026e0d1SMaxime Ripard #define SUN4I_TCON_CEU_MUL_RG_REG		0x114
1659026e0d1SMaxime Ripard #define SUN4I_TCON_CEU_MUL_RB_REG		0x118
1669026e0d1SMaxime Ripard #define SUN4I_TCON_CEU_ADD_RC_REG		0x11c
1679026e0d1SMaxime Ripard #define SUN4I_TCON_CEU_MUL_GR_REG		0x120
1689026e0d1SMaxime Ripard #define SUN4I_TCON_CEU_MUL_GG_REG		0x124
1699026e0d1SMaxime Ripard #define SUN4I_TCON_CEU_MUL_GB_REG		0x128
1709026e0d1SMaxime Ripard #define SUN4I_TCON_CEU_ADD_GC_REG		0x12c
1719026e0d1SMaxime Ripard #define SUN4I_TCON_CEU_MUL_BR_REG		0x130
1729026e0d1SMaxime Ripard #define SUN4I_TCON_CEU_MUL_BG_REG		0x134
1739026e0d1SMaxime Ripard #define SUN4I_TCON_CEU_MUL_BB_REG		0x138
1749026e0d1SMaxime Ripard #define SUN4I_TCON_CEU_ADD_BC_REG		0x13c
1759026e0d1SMaxime Ripard #define SUN4I_TCON_CEU_RANGE_R_REG		0x140
1769026e0d1SMaxime Ripard #define SUN4I_TCON_CEU_RANGE_G_REG		0x144
1779026e0d1SMaxime Ripard #define SUN4I_TCON_CEU_RANGE_B_REG		0x148
178a08fc7c8SMaxime Ripard 
179a08fc7c8SMaxime Ripard #define SUN4I_TCON0_CPU_TRI0_REG		0x160
180a08fc7c8SMaxime Ripard #define SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(space)		((((space) - 1) & 0xfff) << 16)
181a08fc7c8SMaxime Ripard #define SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(size)		(((size) - 1) & 0xfff)
182a08fc7c8SMaxime Ripard 
183a08fc7c8SMaxime Ripard #define SUN4I_TCON0_CPU_TRI1_REG		0x164
184a08fc7c8SMaxime Ripard #define SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(num)		(((num) - 1) & 0xffff)
185a08fc7c8SMaxime Ripard 
186a08fc7c8SMaxime Ripard #define SUN4I_TCON0_CPU_TRI2_REG		0x168
187a08fc7c8SMaxime Ripard #define SUN4I_TCON0_CPU_TRI2_START_DELAY(delay)		(((delay) & 0xffff) << 16)
188a08fc7c8SMaxime Ripard #define SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(set)	((set) & 0xfff)
189a08fc7c8SMaxime Ripard 
190a08fc7c8SMaxime Ripard #define SUN4I_TCON_SAFE_PERIOD_REG		0x1f0
191a08fc7c8SMaxime Ripard #define SUN4I_TCON_SAFE_PERIOD_NUM(num)			(((num) & 0xfff) << 16)
192a08fc7c8SMaxime Ripard #define SUN4I_TCON_SAFE_PERIOD_MODE(mode)		((mode) & 0x3)
193a08fc7c8SMaxime Ripard 
1949026e0d1SMaxime Ripard #define SUN4I_TCON_MUX_CTRL_REG			0x200
195a0c1214eSMaxime Ripard 
196a0c1214eSMaxime Ripard #define SUN4I_TCON0_LVDS_ANA0_REG		0x220
197d718e53aSAndrey Lebedev #define SUN4I_TCON0_LVDS_ANA0_DCHS			BIT(16)
198d718e53aSAndrey Lebedev #define SUN4I_TCON0_LVDS_ANA0_PD			(BIT(20) | BIT(21))
199d718e53aSAndrey Lebedev #define SUN4I_TCON0_LVDS_ANA0_EN_MB			BIT(22)
200d718e53aSAndrey Lebedev #define SUN4I_TCON0_LVDS_ANA0_REG_C			(BIT(24) | BIT(25))
201d718e53aSAndrey Lebedev #define SUN4I_TCON0_LVDS_ANA0_REG_V			(BIT(26) | BIT(27))
202d718e53aSAndrey Lebedev #define SUN4I_TCON0_LVDS_ANA0_CK_EN			(BIT(29) | BIT(28))
203d718e53aSAndrey Lebedev 
204a0c1214eSMaxime Ripard #define SUN6I_TCON0_LVDS_ANA0_EN_MB			BIT(31)
205a0c1214eSMaxime Ripard #define SUN6I_TCON0_LVDS_ANA0_EN_LDO			BIT(30)
206a0c1214eSMaxime Ripard #define SUN6I_TCON0_LVDS_ANA0_EN_DRVC			BIT(24)
207a0c1214eSMaxime Ripard #define SUN6I_TCON0_LVDS_ANA0_EN_DRVD(x)		(((x) & 0xf) << 20)
208a0c1214eSMaxime Ripard #define SUN6I_TCON0_LVDS_ANA0_C(x)			(((x) & 3) << 17)
209a0c1214eSMaxime Ripard #define SUN6I_TCON0_LVDS_ANA0_V(x)			(((x) & 3) << 8)
210a0c1214eSMaxime Ripard #define SUN6I_TCON0_LVDS_ANA0_PD(x)			(((x) & 3) << 4)
211a0c1214eSMaxime Ripard 
212d718e53aSAndrey Lebedev #define SUN4I_TCON0_LVDS_ANA1_REG		0x224
213d718e53aSAndrey Lebedev #define SUN4I_TCON0_LVDS_ANA1_INIT			(0x1f << 26 | 0x1f << 10)
214d718e53aSAndrey Lebedev #define SUN4I_TCON0_LVDS_ANA1_UPDATE			(0x1f << 16 | 0x1f << 00)
215d718e53aSAndrey Lebedev 
2169026e0d1SMaxime Ripard #define SUN4I_TCON1_FILL_CTL_REG		0x300
2179026e0d1SMaxime Ripard #define SUN4I_TCON1_FILL_BEG0_REG		0x304
2189026e0d1SMaxime Ripard #define SUN4I_TCON1_FILL_END0_REG		0x308
2199026e0d1SMaxime Ripard #define SUN4I_TCON1_FILL_DATA0_REG		0x30c
2209026e0d1SMaxime Ripard #define SUN4I_TCON1_FILL_BEG1_REG		0x310
2219026e0d1SMaxime Ripard #define SUN4I_TCON1_FILL_END1_REG		0x314
2229026e0d1SMaxime Ripard #define SUN4I_TCON1_FILL_DATA1_REG		0x318
2239026e0d1SMaxime Ripard #define SUN4I_TCON1_FILL_BEG2_REG		0x31c
2249026e0d1SMaxime Ripard #define SUN4I_TCON1_FILL_END2_REG		0x320
2259026e0d1SMaxime Ripard #define SUN4I_TCON1_FILL_DATA2_REG		0x324
2269026e0d1SMaxime Ripard #define SUN4I_TCON1_GAMMA_TABLE_REG		0x400
2279026e0d1SMaxime Ripard 
2289026e0d1SMaxime Ripard #define SUN4I_TCON_MAX_CHANNELS		2
2299026e0d1SMaxime Ripard 
230ad537fb2SChen-Yu Tsai struct sun4i_tcon;
231ad537fb2SChen-Yu Tsai 
23291ea2f29SChen-Yu Tsai struct sun4i_tcon_quirks {
23334d698f6SJernej Skrabec 	bool	has_channel_0;	/* a83t does not have channel 0 on second TCON */
23491ea2f29SChen-Yu Tsai 	bool	has_channel_1;	/* a33 does not have channel 1 */
235a0c1214eSMaxime Ripard 	bool	has_lvds_alt;	/* Does the LVDS clock have a parent other than the TCON clock? */
23627e18de7SChen-Yu Tsai 	bool	needs_de_be_mux; /* sun6i needs mux to select backend */
2376664e9dcSChen-Yu Tsai 	bool    needs_edp_reset; /* a80 edp reset needed for tcon0 access */
238e742a17cSMaxime Ripard 	bool	supports_lvds;   /* Does the TCON support an LVDS output? */
2394396393fSChen-Yu Tsai 	u8	dclk_min_div;	/* minimum divider for TCON0 DCLK */
240ad537fb2SChen-Yu Tsai 
241ad537fb2SChen-Yu Tsai 	/* callback to handle tcon muxing options */
242abcb8766SMaxime Ripard 	int	(*set_mux)(struct sun4i_tcon *, const struct drm_encoder *);
2435627c9d8SAndrey Lebedev 	/* handler for LVDS setup routine */
2445627c9d8SAndrey Lebedev 	void	(*setup_lvds_phy)(struct sun4i_tcon *tcon,
2455627c9d8SAndrey Lebedev 				  const struct drm_encoder *encoder);
24691ea2f29SChen-Yu Tsai };
24791ea2f29SChen-Yu Tsai 
2489026e0d1SMaxime Ripard struct sun4i_tcon {
249ae558110SMaxime Ripard 	struct device			*dev;
2509026e0d1SMaxime Ripard 	struct drm_device		*drm;
2519026e0d1SMaxime Ripard 	struct regmap			*regs;
2529026e0d1SMaxime Ripard 
2539026e0d1SMaxime Ripard 	/* Main bus clock */
2549026e0d1SMaxime Ripard 	struct clk			*clk;
2559026e0d1SMaxime Ripard 
2569026e0d1SMaxime Ripard 	/* Clocks for the TCON channels */
2579026e0d1SMaxime Ripard 	struct clk			*sclk0;
2589026e0d1SMaxime Ripard 	struct clk			*sclk1;
2599026e0d1SMaxime Ripard 
260a0c1214eSMaxime Ripard 	/* Possible mux for the LVDS clock */
261a0c1214eSMaxime Ripard 	struct clk			*lvds_pll;
262a0c1214eSMaxime Ripard 
2639026e0d1SMaxime Ripard 	/* Pixel clock */
2649026e0d1SMaxime Ripard 	struct clk			*dclk;
265ec08d596SMaxime Ripard 	u8				dclk_max_div;
266ec08d596SMaxime Ripard 	u8				dclk_min_div;
2679026e0d1SMaxime Ripard 
2689026e0d1SMaxime Ripard 	/* Reset control */
2699026e0d1SMaxime Ripard 	struct reset_control		*lcd_rst;
270a0c1214eSMaxime Ripard 	struct reset_control		*lvds_rst;
2719026e0d1SMaxime Ripard 
27291ea2f29SChen-Yu Tsai 	/* Platform adjustments */
27391ea2f29SChen-Yu Tsai 	const struct sun4i_tcon_quirks	*quirks;
27446cce6daSChen-Yu Tsai 
27546cce6daSChen-Yu Tsai 	/* Associated crtc */
27646cce6daSChen-Yu Tsai 	struct sun4i_crtc		*crtc;
27780a58240SChen-Yu Tsai 
278d281c862SChen-Yu Tsai 	int				id;
279d281c862SChen-Yu Tsai 
28080a58240SChen-Yu Tsai 	/* TCON list management */
28180a58240SChen-Yu Tsai 	struct list_head		list;
2829026e0d1SMaxime Ripard };
2839026e0d1SMaxime Ripard 
284894f5a9fSMaxime Ripard struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node);
285a8444c7eSMaxime Ripard struct drm_panel *sun4i_tcon_find_panel(struct device_node *node);
286a8444c7eSMaxime Ripard 
2879026e0d1SMaxime Ripard void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable);
2885b8f0910SMaxime Ripard void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
2895b8f0910SMaxime Ripard 			 const struct drm_encoder *encoder,
2905b8f0910SMaxime Ripard 			 const struct drm_display_mode *mode);
29145e88f99SMaxime Ripard void sun4i_tcon_set_status(struct sun4i_tcon *crtc,
29245e88f99SMaxime Ripard 			   const struct drm_encoder *encoder, bool enable);
2939026e0d1SMaxime Ripard 
294ff71c2cfSChen-Yu Tsai extern const struct of_device_id sun4i_tcon_of_table[];
295ff71c2cfSChen-Yu Tsai 
2969026e0d1SMaxime Ripard #endif /* __SUN4I_TCON_H__ */
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