xref: /openbmc/linux/drivers/gpu/drm/sun4i/sun4i_tcon.c (revision be3fe0f9ed1ca8e4b2cf3419dfb34be716296487)
19026e0d1SMaxime Ripard /*
29026e0d1SMaxime Ripard  * Copyright (C) 2015 Free Electrons
39026e0d1SMaxime Ripard  * Copyright (C) 2015 NextThing Co
49026e0d1SMaxime Ripard  *
59026e0d1SMaxime Ripard  * Maxime Ripard <maxime.ripard@free-electrons.com>
69026e0d1SMaxime Ripard  *
79026e0d1SMaxime Ripard  * This program is free software; you can redistribute it and/or
89026e0d1SMaxime Ripard  * modify it under the terms of the GNU General Public License as
99026e0d1SMaxime Ripard  * published by the Free Software Foundation; either version 2 of
109026e0d1SMaxime Ripard  * the License, or (at your option) any later version.
119026e0d1SMaxime Ripard  */
129026e0d1SMaxime Ripard 
139026e0d1SMaxime Ripard #include <drm/drmP.h>
149026e0d1SMaxime Ripard #include <drm/drm_atomic_helper.h>
159026e0d1SMaxime Ripard #include <drm/drm_crtc.h>
169026e0d1SMaxime Ripard #include <drm/drm_crtc_helper.h>
179026e0d1SMaxime Ripard #include <drm/drm_modes.h>
18ebc94461SRob Herring #include <drm/drm_of.h>
199026e0d1SMaxime Ripard 
209026e0d1SMaxime Ripard #include <linux/component.h>
219026e0d1SMaxime Ripard #include <linux/ioport.h>
229026e0d1SMaxime Ripard #include <linux/of_address.h>
2391ea2f29SChen-Yu Tsai #include <linux/of_device.h>
249026e0d1SMaxime Ripard #include <linux/of_irq.h>
259026e0d1SMaxime Ripard #include <linux/regmap.h>
269026e0d1SMaxime Ripard #include <linux/reset.h>
279026e0d1SMaxime Ripard 
289026e0d1SMaxime Ripard #include "sun4i_crtc.h"
299026e0d1SMaxime Ripard #include "sun4i_dotclock.h"
309026e0d1SMaxime Ripard #include "sun4i_drv.h"
3129e57fabSMaxime Ripard #include "sun4i_rgb.h"
329026e0d1SMaxime Ripard #include "sun4i_tcon.h"
3387969338SIcenowy Zheng #include "sunxi_engine.h"
349026e0d1SMaxime Ripard 
359026e0d1SMaxime Ripard void sun4i_tcon_disable(struct sun4i_tcon *tcon)
369026e0d1SMaxime Ripard {
379026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("Disabling TCON\n");
389026e0d1SMaxime Ripard 
399026e0d1SMaxime Ripard 	/* Disable the TCON */
409026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
419026e0d1SMaxime Ripard 			   SUN4I_TCON_GCTL_TCON_ENABLE, 0);
429026e0d1SMaxime Ripard }
439026e0d1SMaxime Ripard EXPORT_SYMBOL(sun4i_tcon_disable);
449026e0d1SMaxime Ripard 
459026e0d1SMaxime Ripard void sun4i_tcon_enable(struct sun4i_tcon *tcon)
469026e0d1SMaxime Ripard {
479026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("Enabling TCON\n");
489026e0d1SMaxime Ripard 
499026e0d1SMaxime Ripard 	/* Enable the TCON */
509026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
519026e0d1SMaxime Ripard 			   SUN4I_TCON_GCTL_TCON_ENABLE,
529026e0d1SMaxime Ripard 			   SUN4I_TCON_GCTL_TCON_ENABLE);
539026e0d1SMaxime Ripard }
549026e0d1SMaxime Ripard EXPORT_SYMBOL(sun4i_tcon_enable);
559026e0d1SMaxime Ripard 
569026e0d1SMaxime Ripard void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int channel)
579026e0d1SMaxime Ripard {
581a075426SMaxime Ripard 	DRM_DEBUG_DRIVER("Disabling TCON channel %d\n", channel);
591a075426SMaxime Ripard 
609026e0d1SMaxime Ripard 	/* Disable the TCON's channel */
619026e0d1SMaxime Ripard 	if (channel == 0) {
629026e0d1SMaxime Ripard 		regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
639026e0d1SMaxime Ripard 				   SUN4I_TCON0_CTL_TCON_ENABLE, 0);
649026e0d1SMaxime Ripard 		clk_disable_unprepare(tcon->dclk);
658e924047SMaxime Ripard 		return;
668e924047SMaxime Ripard 	}
678e924047SMaxime Ripard 
6891ea2f29SChen-Yu Tsai 	WARN_ON(!tcon->quirks->has_channel_1);
699026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
709026e0d1SMaxime Ripard 			   SUN4I_TCON1_CTL_TCON_ENABLE, 0);
719026e0d1SMaxime Ripard 	clk_disable_unprepare(tcon->sclk1);
729026e0d1SMaxime Ripard }
739026e0d1SMaxime Ripard EXPORT_SYMBOL(sun4i_tcon_channel_disable);
749026e0d1SMaxime Ripard 
759026e0d1SMaxime Ripard void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel)
769026e0d1SMaxime Ripard {
771a075426SMaxime Ripard 	DRM_DEBUG_DRIVER("Enabling TCON channel %d\n", channel);
781a075426SMaxime Ripard 
799026e0d1SMaxime Ripard 	/* Enable the TCON's channel */
809026e0d1SMaxime Ripard 	if (channel == 0) {
819026e0d1SMaxime Ripard 		regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
829026e0d1SMaxime Ripard 				   SUN4I_TCON0_CTL_TCON_ENABLE,
839026e0d1SMaxime Ripard 				   SUN4I_TCON0_CTL_TCON_ENABLE);
849026e0d1SMaxime Ripard 		clk_prepare_enable(tcon->dclk);
858e924047SMaxime Ripard 		return;
868e924047SMaxime Ripard 	}
878e924047SMaxime Ripard 
8891ea2f29SChen-Yu Tsai 	WARN_ON(!tcon->quirks->has_channel_1);
899026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
909026e0d1SMaxime Ripard 			   SUN4I_TCON1_CTL_TCON_ENABLE,
919026e0d1SMaxime Ripard 			   SUN4I_TCON1_CTL_TCON_ENABLE);
929026e0d1SMaxime Ripard 	clk_prepare_enable(tcon->sclk1);
939026e0d1SMaxime Ripard }
949026e0d1SMaxime Ripard EXPORT_SYMBOL(sun4i_tcon_channel_enable);
959026e0d1SMaxime Ripard 
969026e0d1SMaxime Ripard void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
979026e0d1SMaxime Ripard {
989026e0d1SMaxime Ripard 	u32 mask, val = 0;
999026e0d1SMaxime Ripard 
1009026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");
1019026e0d1SMaxime Ripard 
1029026e0d1SMaxime Ripard 	mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
1039026e0d1SMaxime Ripard 	       SUN4I_TCON_GINT0_VBLANK_ENABLE(1);
1049026e0d1SMaxime Ripard 
1059026e0d1SMaxime Ripard 	if (enable)
1069026e0d1SMaxime Ripard 		val = mask;
1079026e0d1SMaxime Ripard 
1089026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);
1099026e0d1SMaxime Ripard }
1109026e0d1SMaxime Ripard EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
1119026e0d1SMaxime Ripard 
112f8c73f4fSMaxime Ripard void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
113f8c73f4fSMaxime Ripard 			struct drm_encoder *encoder)
114f8c73f4fSMaxime Ripard {
115b7cb9b91SMaxime Ripard 	u32 val;
116b7cb9b91SMaxime Ripard 
117f8c73f4fSMaxime Ripard 	if (!tcon->quirks->has_unknown_mux)
118f8c73f4fSMaxime Ripard 		return;
119f8c73f4fSMaxime Ripard 
120f8c73f4fSMaxime Ripard 	if (channel != 1)
121f8c73f4fSMaxime Ripard 		return;
122f8c73f4fSMaxime Ripard 
123b7cb9b91SMaxime Ripard 	if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
124b7cb9b91SMaxime Ripard 		val = 1;
125b7cb9b91SMaxime Ripard 	else
126b7cb9b91SMaxime Ripard 		val = 0;
127b7cb9b91SMaxime Ripard 
128f8c73f4fSMaxime Ripard 	/*
129f8c73f4fSMaxime Ripard 	 * FIXME: Undocumented bits
130f8c73f4fSMaxime Ripard 	 */
131b7cb9b91SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
132f8c73f4fSMaxime Ripard }
133f8c73f4fSMaxime Ripard EXPORT_SYMBOL(sun4i_tcon_set_mux);
134f8c73f4fSMaxime Ripard 
1359026e0d1SMaxime Ripard static int sun4i_tcon_get_clk_delay(struct drm_display_mode *mode,
1369026e0d1SMaxime Ripard 				    int channel)
1379026e0d1SMaxime Ripard {
1389026e0d1SMaxime Ripard 	int delay = mode->vtotal - mode->vdisplay;
1399026e0d1SMaxime Ripard 
1409026e0d1SMaxime Ripard 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1419026e0d1SMaxime Ripard 		delay /= 2;
1429026e0d1SMaxime Ripard 
1439026e0d1SMaxime Ripard 	if (channel == 1)
1449026e0d1SMaxime Ripard 		delay -= 2;
1459026e0d1SMaxime Ripard 
1469026e0d1SMaxime Ripard 	delay = min(delay, 30);
1479026e0d1SMaxime Ripard 
1489026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay);
1499026e0d1SMaxime Ripard 
1509026e0d1SMaxime Ripard 	return delay;
1519026e0d1SMaxime Ripard }
1529026e0d1SMaxime Ripard 
1539026e0d1SMaxime Ripard void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
1549026e0d1SMaxime Ripard 			  struct drm_display_mode *mode)
1559026e0d1SMaxime Ripard {
1569026e0d1SMaxime Ripard 	unsigned int bp, hsync, vsync;
1579026e0d1SMaxime Ripard 	u8 clk_delay;
1589026e0d1SMaxime Ripard 	u32 val = 0;
1599026e0d1SMaxime Ripard 
16086cf6788SChen-Yu Tsai 	/* Configure the dot clock */
16186cf6788SChen-Yu Tsai 	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
16286cf6788SChen-Yu Tsai 
1639026e0d1SMaxime Ripard 	/* Adjust clock delay */
1649026e0d1SMaxime Ripard 	clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
1659026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
1669026e0d1SMaxime Ripard 			   SUN4I_TCON0_CTL_CLK_DELAY_MASK,
1679026e0d1SMaxime Ripard 			   SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
1689026e0d1SMaxime Ripard 
1699026e0d1SMaxime Ripard 	/* Set the resolution */
1709026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
1719026e0d1SMaxime Ripard 		     SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
1729026e0d1SMaxime Ripard 		     SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
1739026e0d1SMaxime Ripard 
1749026e0d1SMaxime Ripard 	/*
1759026e0d1SMaxime Ripard 	 * This is called a backporch in the register documentation,
17623a1cb11SChen-Yu Tsai 	 * but it really is the back porch + hsync
1779026e0d1SMaxime Ripard 	 */
1789026e0d1SMaxime Ripard 	bp = mode->crtc_htotal - mode->crtc_hsync_start;
1799026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
1809026e0d1SMaxime Ripard 			 mode->crtc_htotal, bp);
1819026e0d1SMaxime Ripard 
1829026e0d1SMaxime Ripard 	/* Set horizontal display timings */
1839026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
1849026e0d1SMaxime Ripard 		     SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) |
1859026e0d1SMaxime Ripard 		     SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
1869026e0d1SMaxime Ripard 
1879026e0d1SMaxime Ripard 	/*
1889026e0d1SMaxime Ripard 	 * This is called a backporch in the register documentation,
18923a1cb11SChen-Yu Tsai 	 * but it really is the back porch + hsync
1909026e0d1SMaxime Ripard 	 */
1919026e0d1SMaxime Ripard 	bp = mode->crtc_vtotal - mode->crtc_vsync_start;
1929026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
1939026e0d1SMaxime Ripard 			 mode->crtc_vtotal, bp);
1949026e0d1SMaxime Ripard 
1959026e0d1SMaxime Ripard 	/* Set vertical display timings */
1969026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
197a88cbbd4SMaxime Ripard 		     SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
1989026e0d1SMaxime Ripard 		     SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
1999026e0d1SMaxime Ripard 
2009026e0d1SMaxime Ripard 	/* Set Hsync and Vsync length */
2019026e0d1SMaxime Ripard 	hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
2029026e0d1SMaxime Ripard 	vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
2039026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
2049026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
2059026e0d1SMaxime Ripard 		     SUN4I_TCON0_BASIC3_V_SYNC(vsync) |
2069026e0d1SMaxime Ripard 		     SUN4I_TCON0_BASIC3_H_SYNC(hsync));
2079026e0d1SMaxime Ripard 
2089026e0d1SMaxime Ripard 	/* Setup the polarity of the various signals */
2099026e0d1SMaxime Ripard 	if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
2109026e0d1SMaxime Ripard 		val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
2119026e0d1SMaxime Ripard 
2129026e0d1SMaxime Ripard 	if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
2139026e0d1SMaxime Ripard 		val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
2149026e0d1SMaxime Ripard 
2159026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
2169026e0d1SMaxime Ripard 			   SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,
2179026e0d1SMaxime Ripard 			   val);
2189026e0d1SMaxime Ripard 
2199026e0d1SMaxime Ripard 	/* Map output pins to channel 0 */
2209026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
2219026e0d1SMaxime Ripard 			   SUN4I_TCON_GCTL_IOMAP_MASK,
2229026e0d1SMaxime Ripard 			   SUN4I_TCON_GCTL_IOMAP_TCON0);
2239026e0d1SMaxime Ripard 
2249026e0d1SMaxime Ripard 	/* Enable the output on the pins */
2259026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
2269026e0d1SMaxime Ripard }
2279026e0d1SMaxime Ripard EXPORT_SYMBOL(sun4i_tcon0_mode_set);
2289026e0d1SMaxime Ripard 
2299026e0d1SMaxime Ripard void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
2309026e0d1SMaxime Ripard 			  struct drm_display_mode *mode)
2319026e0d1SMaxime Ripard {
232b8317a3dSMaxime Ripard 	unsigned int bp, hsync, vsync, vtotal;
2339026e0d1SMaxime Ripard 	u8 clk_delay;
2349026e0d1SMaxime Ripard 	u32 val;
2359026e0d1SMaxime Ripard 
23691ea2f29SChen-Yu Tsai 	WARN_ON(!tcon->quirks->has_channel_1);
2378e924047SMaxime Ripard 
23886cf6788SChen-Yu Tsai 	/* Configure the dot clock */
23986cf6788SChen-Yu Tsai 	clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
24086cf6788SChen-Yu Tsai 
2419026e0d1SMaxime Ripard 	/* Adjust clock delay */
2429026e0d1SMaxime Ripard 	clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
2439026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
2449026e0d1SMaxime Ripard 			   SUN4I_TCON1_CTL_CLK_DELAY_MASK,
2459026e0d1SMaxime Ripard 			   SUN4I_TCON1_CTL_CLK_DELAY(clk_delay));
2469026e0d1SMaxime Ripard 
2479026e0d1SMaxime Ripard 	/* Set interlaced mode */
2489026e0d1SMaxime Ripard 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2499026e0d1SMaxime Ripard 		val = SUN4I_TCON1_CTL_INTERLACE_ENABLE;
2509026e0d1SMaxime Ripard 	else
2519026e0d1SMaxime Ripard 		val = 0;
2529026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
2539026e0d1SMaxime Ripard 			   SUN4I_TCON1_CTL_INTERLACE_ENABLE,
2549026e0d1SMaxime Ripard 			   val);
2559026e0d1SMaxime Ripard 
2569026e0d1SMaxime Ripard 	/* Set the input resolution */
2579026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
2589026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) |
2599026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay));
2609026e0d1SMaxime Ripard 
2619026e0d1SMaxime Ripard 	/* Set the upscaling resolution */
2629026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
2639026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) |
2649026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay));
2659026e0d1SMaxime Ripard 
2669026e0d1SMaxime Ripard 	/* Set the output resolution */
2679026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
2689026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) |
2699026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
2709026e0d1SMaxime Ripard 
2719026e0d1SMaxime Ripard 	/* Set horizontal display timings */
2723cb2f46bSMaxime Ripard 	bp = mode->crtc_htotal - mode->crtc_hsync_start;
2739026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
2749026e0d1SMaxime Ripard 			 mode->htotal, bp);
2759026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
2769026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
2779026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
2789026e0d1SMaxime Ripard 
2793cb2f46bSMaxime Ripard 	bp = mode->crtc_vtotal - mode->crtc_vsync_start;
2809026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
281b8317a3dSMaxime Ripard 			 mode->crtc_vtotal, bp);
282b8317a3dSMaxime Ripard 
283b8317a3dSMaxime Ripard 	/*
284b8317a3dSMaxime Ripard 	 * The vertical resolution needs to be doubled in all
285b8317a3dSMaxime Ripard 	 * cases. We could use crtc_vtotal and always multiply by two,
286b8317a3dSMaxime Ripard 	 * but that leads to a rounding error in interlace when vtotal
287b8317a3dSMaxime Ripard 	 * is odd.
288b8317a3dSMaxime Ripard 	 *
289b8317a3dSMaxime Ripard 	 * This happens with TV's PAL for example, where vtotal will
290b8317a3dSMaxime Ripard 	 * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be
291b8317a3dSMaxime Ripard 	 * 624, which apparently confuses the hardware.
292b8317a3dSMaxime Ripard 	 *
293b8317a3dSMaxime Ripard 	 * To work around this, we will always use vtotal, and
294b8317a3dSMaxime Ripard 	 * multiply by two only if we're not in interlace.
295b8317a3dSMaxime Ripard 	 */
296b8317a3dSMaxime Ripard 	vtotal = mode->vtotal;
297b8317a3dSMaxime Ripard 	if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
298b8317a3dSMaxime Ripard 		vtotal = vtotal * 2;
299b8317a3dSMaxime Ripard 
300b8317a3dSMaxime Ripard 	/* Set vertical display timings */
3019026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
302b8317a3dSMaxime Ripard 		     SUN4I_TCON1_BASIC4_V_TOTAL(vtotal) |
3039026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
3049026e0d1SMaxime Ripard 
3059026e0d1SMaxime Ripard 	/* Set Hsync and Vsync length */
3069026e0d1SMaxime Ripard 	hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
3079026e0d1SMaxime Ripard 	vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
3089026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
3099026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,
3109026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
3119026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC5_H_SYNC(hsync));
3129026e0d1SMaxime Ripard 
3139026e0d1SMaxime Ripard 	/* Map output pins to channel 1 */
3149026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
3159026e0d1SMaxime Ripard 			   SUN4I_TCON_GCTL_IOMAP_MASK,
3169026e0d1SMaxime Ripard 			   SUN4I_TCON_GCTL_IOMAP_TCON1);
3179026e0d1SMaxime Ripard }
3189026e0d1SMaxime Ripard EXPORT_SYMBOL(sun4i_tcon1_mode_set);
3199026e0d1SMaxime Ripard 
3209026e0d1SMaxime Ripard static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
3219026e0d1SMaxime Ripard 					struct sun4i_crtc *scrtc)
3229026e0d1SMaxime Ripard {
3239026e0d1SMaxime Ripard 	unsigned long flags;
3249026e0d1SMaxime Ripard 
3259026e0d1SMaxime Ripard 	spin_lock_irqsave(&dev->event_lock, flags);
3269026e0d1SMaxime Ripard 	if (scrtc->event) {
3279026e0d1SMaxime Ripard 		drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event);
3289026e0d1SMaxime Ripard 		drm_crtc_vblank_put(&scrtc->crtc);
3299026e0d1SMaxime Ripard 		scrtc->event = NULL;
3309026e0d1SMaxime Ripard 	}
3319026e0d1SMaxime Ripard 	spin_unlock_irqrestore(&dev->event_lock, flags);
3329026e0d1SMaxime Ripard }
3339026e0d1SMaxime Ripard 
3349026e0d1SMaxime Ripard static irqreturn_t sun4i_tcon_handler(int irq, void *private)
3359026e0d1SMaxime Ripard {
3369026e0d1SMaxime Ripard 	struct sun4i_tcon *tcon = private;
3379026e0d1SMaxime Ripard 	struct drm_device *drm = tcon->drm;
33846cce6daSChen-Yu Tsai 	struct sun4i_crtc *scrtc = tcon->crtc;
3399026e0d1SMaxime Ripard 	unsigned int status;
3409026e0d1SMaxime Ripard 
3419026e0d1SMaxime Ripard 	regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
3429026e0d1SMaxime Ripard 
3439026e0d1SMaxime Ripard 	if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
3449026e0d1SMaxime Ripard 			SUN4I_TCON_GINT0_VBLANK_INT(1))))
3459026e0d1SMaxime Ripard 		return IRQ_NONE;
3469026e0d1SMaxime Ripard 
3479026e0d1SMaxime Ripard 	drm_crtc_handle_vblank(&scrtc->crtc);
3489026e0d1SMaxime Ripard 	sun4i_tcon_finish_page_flip(drm, scrtc);
3499026e0d1SMaxime Ripard 
3509026e0d1SMaxime Ripard 	/* Acknowledge the interrupt */
3519026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
3529026e0d1SMaxime Ripard 			   SUN4I_TCON_GINT0_VBLANK_INT(0) |
3539026e0d1SMaxime Ripard 			   SUN4I_TCON_GINT0_VBLANK_INT(1),
3549026e0d1SMaxime Ripard 			   0);
3559026e0d1SMaxime Ripard 
3569026e0d1SMaxime Ripard 	return IRQ_HANDLED;
3579026e0d1SMaxime Ripard }
3589026e0d1SMaxime Ripard 
3599026e0d1SMaxime Ripard static int sun4i_tcon_init_clocks(struct device *dev,
3609026e0d1SMaxime Ripard 				  struct sun4i_tcon *tcon)
3619026e0d1SMaxime Ripard {
3629026e0d1SMaxime Ripard 	tcon->clk = devm_clk_get(dev, "ahb");
3639026e0d1SMaxime Ripard 	if (IS_ERR(tcon->clk)) {
3649026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't get the TCON bus clock\n");
3659026e0d1SMaxime Ripard 		return PTR_ERR(tcon->clk);
3669026e0d1SMaxime Ripard 	}
3679026e0d1SMaxime Ripard 	clk_prepare_enable(tcon->clk);
3689026e0d1SMaxime Ripard 
3699026e0d1SMaxime Ripard 	tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
3709026e0d1SMaxime Ripard 	if (IS_ERR(tcon->sclk0)) {
3719026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
3729026e0d1SMaxime Ripard 		return PTR_ERR(tcon->sclk0);
3739026e0d1SMaxime Ripard 	}
3749026e0d1SMaxime Ripard 
37591ea2f29SChen-Yu Tsai 	if (tcon->quirks->has_channel_1) {
3769026e0d1SMaxime Ripard 		tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
3779026e0d1SMaxime Ripard 		if (IS_ERR(tcon->sclk1)) {
3789026e0d1SMaxime Ripard 			dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
3799026e0d1SMaxime Ripard 			return PTR_ERR(tcon->sclk1);
3809026e0d1SMaxime Ripard 		}
3818e924047SMaxime Ripard 	}
3829026e0d1SMaxime Ripard 
3834c7f16d1SChen-Yu Tsai 	return 0;
3849026e0d1SMaxime Ripard }
3859026e0d1SMaxime Ripard 
3869026e0d1SMaxime Ripard static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
3879026e0d1SMaxime Ripard {
3889026e0d1SMaxime Ripard 	clk_disable_unprepare(tcon->clk);
3899026e0d1SMaxime Ripard }
3909026e0d1SMaxime Ripard 
3919026e0d1SMaxime Ripard static int sun4i_tcon_init_irq(struct device *dev,
3929026e0d1SMaxime Ripard 			       struct sun4i_tcon *tcon)
3939026e0d1SMaxime Ripard {
3949026e0d1SMaxime Ripard 	struct platform_device *pdev = to_platform_device(dev);
3959026e0d1SMaxime Ripard 	int irq, ret;
3969026e0d1SMaxime Ripard 
3979026e0d1SMaxime Ripard 	irq = platform_get_irq(pdev, 0);
3989026e0d1SMaxime Ripard 	if (irq < 0) {
3999026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't retrieve the TCON interrupt\n");
4009026e0d1SMaxime Ripard 		return irq;
4019026e0d1SMaxime Ripard 	}
4029026e0d1SMaxime Ripard 
4039026e0d1SMaxime Ripard 	ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0,
4049026e0d1SMaxime Ripard 			       dev_name(dev), tcon);
4059026e0d1SMaxime Ripard 	if (ret) {
4069026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't request the IRQ\n");
4079026e0d1SMaxime Ripard 		return ret;
4089026e0d1SMaxime Ripard 	}
4099026e0d1SMaxime Ripard 
4109026e0d1SMaxime Ripard 	return 0;
4119026e0d1SMaxime Ripard }
4129026e0d1SMaxime Ripard 
4139026e0d1SMaxime Ripard static struct regmap_config sun4i_tcon_regmap_config = {
4149026e0d1SMaxime Ripard 	.reg_bits	= 32,
4159026e0d1SMaxime Ripard 	.val_bits	= 32,
4169026e0d1SMaxime Ripard 	.reg_stride	= 4,
4179026e0d1SMaxime Ripard 	.max_register	= 0x800,
4189026e0d1SMaxime Ripard };
4199026e0d1SMaxime Ripard 
4209026e0d1SMaxime Ripard static int sun4i_tcon_init_regmap(struct device *dev,
4219026e0d1SMaxime Ripard 				  struct sun4i_tcon *tcon)
4229026e0d1SMaxime Ripard {
4239026e0d1SMaxime Ripard 	struct platform_device *pdev = to_platform_device(dev);
4249026e0d1SMaxime Ripard 	struct resource *res;
4259026e0d1SMaxime Ripard 	void __iomem *regs;
4269026e0d1SMaxime Ripard 
4279026e0d1SMaxime Ripard 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4289026e0d1SMaxime Ripard 	regs = devm_ioremap_resource(dev, res);
429af346f55SWei Yongjun 	if (IS_ERR(regs))
4309026e0d1SMaxime Ripard 		return PTR_ERR(regs);
4319026e0d1SMaxime Ripard 
4329026e0d1SMaxime Ripard 	tcon->regs = devm_regmap_init_mmio(dev, regs,
4339026e0d1SMaxime Ripard 					   &sun4i_tcon_regmap_config);
4349026e0d1SMaxime Ripard 	if (IS_ERR(tcon->regs)) {
4359026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't create the TCON regmap\n");
4369026e0d1SMaxime Ripard 		return PTR_ERR(tcon->regs);
4379026e0d1SMaxime Ripard 	}
4389026e0d1SMaxime Ripard 
4399026e0d1SMaxime Ripard 	/* Make sure the TCON is disabled and all IRQs are off */
4409026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
4419026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
4429026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
4439026e0d1SMaxime Ripard 
4449026e0d1SMaxime Ripard 	/* Disable IO lines and set them to tristate */
4459026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
4469026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
4479026e0d1SMaxime Ripard 
4489026e0d1SMaxime Ripard 	return 0;
4499026e0d1SMaxime Ripard }
4509026e0d1SMaxime Ripard 
451b317fa3bSChen-Yu Tsai /*
452b317fa3bSChen-Yu Tsai  * On SoCs with the old display pipeline design (Display Engine 1.0),
453b317fa3bSChen-Yu Tsai  * the TCON is always tied to just one backend. Hence we can traverse
454b317fa3bSChen-Yu Tsai  * the of_graph upwards to find the backend our tcon is connected to,
455b317fa3bSChen-Yu Tsai  * and take its ID as our own.
456b317fa3bSChen-Yu Tsai  *
457b317fa3bSChen-Yu Tsai  * We can either identify backends from their compatible strings, which
458b317fa3bSChen-Yu Tsai  * means maintaining a large list of them. Or, since the backend is
459b317fa3bSChen-Yu Tsai  * registered and binded before the TCON, we can just go through the
460b317fa3bSChen-Yu Tsai  * list of registered backends and compare the device node.
46187969338SIcenowy Zheng  *
46287969338SIcenowy Zheng  * As the structures now store engines instead of backends, here this
46387969338SIcenowy Zheng  * function in fact searches the corresponding engine, and the ID is
46487969338SIcenowy Zheng  * requested via the get_id function of the engine.
465b317fa3bSChen-Yu Tsai  */
466e8d5bbf7SChen-Yu Tsai static struct sunxi_engine *
467e8d5bbf7SChen-Yu Tsai sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv,
468b317fa3bSChen-Yu Tsai 				struct device_node *node)
469b317fa3bSChen-Yu Tsai {
470b317fa3bSChen-Yu Tsai 	struct device_node *port, *ep, *remote;
471*be3fe0f9SChen-Yu Tsai 	struct sunxi_engine *engine = ERR_PTR(-EINVAL);
472b317fa3bSChen-Yu Tsai 
473b317fa3bSChen-Yu Tsai 	port = of_graph_get_port_by_id(node, 0);
474b317fa3bSChen-Yu Tsai 	if (!port)
475b317fa3bSChen-Yu Tsai 		return ERR_PTR(-EINVAL);
476b317fa3bSChen-Yu Tsai 
4771469619dSChen-Yu Tsai 	/*
4781469619dSChen-Yu Tsai 	 * This only works if there is only one path from the TCON
4791469619dSChen-Yu Tsai 	 * to any display engine. Otherwise the probe order of the
4801469619dSChen-Yu Tsai 	 * TCONs and display engines is not guaranteed. They may
4811469619dSChen-Yu Tsai 	 * either bind to the wrong one, or worse, bind to the same
4821469619dSChen-Yu Tsai 	 * one if additional checks are not done.
4831469619dSChen-Yu Tsai 	 *
4841469619dSChen-Yu Tsai 	 * Bail out if there are multiple input connections.
4851469619dSChen-Yu Tsai 	 */
486*be3fe0f9SChen-Yu Tsai 	if (of_get_available_child_count(port) != 1)
487*be3fe0f9SChen-Yu Tsai 		goto out_put_port;
4881469619dSChen-Yu Tsai 
489*be3fe0f9SChen-Yu Tsai 	/* Get the first connection without specifying an ID */
490*be3fe0f9SChen-Yu Tsai 	ep = of_get_next_available_child(port, NULL);
491*be3fe0f9SChen-Yu Tsai 	if (!ep)
492*be3fe0f9SChen-Yu Tsai 		goto out_put_port;
493*be3fe0f9SChen-Yu Tsai 
494b317fa3bSChen-Yu Tsai 	remote = of_graph_get_remote_port_parent(ep);
495b317fa3bSChen-Yu Tsai 	if (!remote)
496*be3fe0f9SChen-Yu Tsai 		goto out_put_ep;
497b317fa3bSChen-Yu Tsai 
49887969338SIcenowy Zheng 	/* does this node match any registered engines? */
499*be3fe0f9SChen-Yu Tsai 	list_for_each_entry(engine, &drv->engine_list, list)
500*be3fe0f9SChen-Yu Tsai 		if (remote == engine->node)
501*be3fe0f9SChen-Yu Tsai 			goto out_put_remote;
502b317fa3bSChen-Yu Tsai 
503b317fa3bSChen-Yu Tsai 	/* keep looking through upstream ports */
504e8d5bbf7SChen-Yu Tsai 	engine = sun4i_tcon_find_engine_traverse(drv, remote);
505b317fa3bSChen-Yu Tsai 
506*be3fe0f9SChen-Yu Tsai out_put_remote:
507*be3fe0f9SChen-Yu Tsai 	of_node_put(remote);
508*be3fe0f9SChen-Yu Tsai out_put_ep:
509*be3fe0f9SChen-Yu Tsai 	of_node_put(ep);
510*be3fe0f9SChen-Yu Tsai out_put_port:
511*be3fe0f9SChen-Yu Tsai 	of_node_put(port);
512*be3fe0f9SChen-Yu Tsai 
513*be3fe0f9SChen-Yu Tsai 	return engine;
514b317fa3bSChen-Yu Tsai }
515b317fa3bSChen-Yu Tsai 
516e8d5bbf7SChen-Yu Tsai /*
517e8d5bbf7SChen-Yu Tsai  * The device tree binding says that the remote endpoint ID of any
518e8d5bbf7SChen-Yu Tsai  * connection between components, up to and including the TCON, of
519e8d5bbf7SChen-Yu Tsai  * the display pipeline should be equal to the actual ID of the local
520e8d5bbf7SChen-Yu Tsai  * component. Thus we can look at any one of the input connections of
521e8d5bbf7SChen-Yu Tsai  * the TCONs, and use that connection's remote endpoint ID as our own.
522e8d5bbf7SChen-Yu Tsai  *
523e8d5bbf7SChen-Yu Tsai  * Since the user of this function already finds the input port,
524e8d5bbf7SChen-Yu Tsai  * the port is passed in directly without further checks.
525e8d5bbf7SChen-Yu Tsai  */
526e8d5bbf7SChen-Yu Tsai static int sun4i_tcon_of_get_id_from_port(struct device_node *port)
527e8d5bbf7SChen-Yu Tsai {
528e8d5bbf7SChen-Yu Tsai 	struct device_node *ep;
529e8d5bbf7SChen-Yu Tsai 	int ret = -EINVAL;
530e8d5bbf7SChen-Yu Tsai 
531e8d5bbf7SChen-Yu Tsai 	/* try finding an upstream endpoint */
532e8d5bbf7SChen-Yu Tsai 	for_each_available_child_of_node(port, ep) {
533e8d5bbf7SChen-Yu Tsai 		struct device_node *remote;
534e8d5bbf7SChen-Yu Tsai 		u32 reg;
535e8d5bbf7SChen-Yu Tsai 
536e8d5bbf7SChen-Yu Tsai 		remote = of_graph_get_remote_endpoint(ep);
537e8d5bbf7SChen-Yu Tsai 		if (!remote)
538e8d5bbf7SChen-Yu Tsai 			continue;
539e8d5bbf7SChen-Yu Tsai 
540e8d5bbf7SChen-Yu Tsai 		ret = of_property_read_u32(remote, "reg", &reg);
541e8d5bbf7SChen-Yu Tsai 		if (ret)
542e8d5bbf7SChen-Yu Tsai 			continue;
543e8d5bbf7SChen-Yu Tsai 
544e8d5bbf7SChen-Yu Tsai 		ret = reg;
545e8d5bbf7SChen-Yu Tsai 	}
546e8d5bbf7SChen-Yu Tsai 
547e8d5bbf7SChen-Yu Tsai 	return ret;
548e8d5bbf7SChen-Yu Tsai }
549e8d5bbf7SChen-Yu Tsai 
550e8d5bbf7SChen-Yu Tsai /*
551e8d5bbf7SChen-Yu Tsai  * Once we know the TCON's id, we can look through the list of
552e8d5bbf7SChen-Yu Tsai  * engines to find a matching one. We assume all engines have
553e8d5bbf7SChen-Yu Tsai  * been probed and added to the list.
554e8d5bbf7SChen-Yu Tsai  */
555e8d5bbf7SChen-Yu Tsai static struct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv,
556e8d5bbf7SChen-Yu Tsai 							int id)
557e8d5bbf7SChen-Yu Tsai {
558e8d5bbf7SChen-Yu Tsai 	struct sunxi_engine *engine;
559e8d5bbf7SChen-Yu Tsai 
560e8d5bbf7SChen-Yu Tsai 	list_for_each_entry(engine, &drv->engine_list, list)
561e8d5bbf7SChen-Yu Tsai 		if (engine->id == id)
562e8d5bbf7SChen-Yu Tsai 			return engine;
563e8d5bbf7SChen-Yu Tsai 
564e8d5bbf7SChen-Yu Tsai 	return ERR_PTR(-EINVAL);
565e8d5bbf7SChen-Yu Tsai }
566e8d5bbf7SChen-Yu Tsai 
567e8d5bbf7SChen-Yu Tsai /*
568e8d5bbf7SChen-Yu Tsai  * On SoCs with the old display pipeline design (Display Engine 1.0),
569e8d5bbf7SChen-Yu Tsai  * we assumed the TCON was always tied to just one backend. However
570e8d5bbf7SChen-Yu Tsai  * this proved not to be the case. On the A31, the TCON can select
571e8d5bbf7SChen-Yu Tsai  * either backend as its source. On the A20 (and likely on the A10),
572e8d5bbf7SChen-Yu Tsai  * the backend can choose which TCON to output to.
573e8d5bbf7SChen-Yu Tsai  *
574e8d5bbf7SChen-Yu Tsai  * The device tree binding says that the remote endpoint ID of any
575e8d5bbf7SChen-Yu Tsai  * connection between components, up to and including the TCON, of
576e8d5bbf7SChen-Yu Tsai  * the display pipeline should be equal to the actual ID of the local
577e8d5bbf7SChen-Yu Tsai  * component. Thus we should be able to look at any one of the input
578e8d5bbf7SChen-Yu Tsai  * connections of the TCONs, and use that connection's remote endpoint
579e8d5bbf7SChen-Yu Tsai  * ID as our own.
580e8d5bbf7SChen-Yu Tsai  *
581e8d5bbf7SChen-Yu Tsai  * However  the connections between the backend and TCON were assumed
582e8d5bbf7SChen-Yu Tsai  * to be always singular, and their endpoit IDs were all incorrectly
583e8d5bbf7SChen-Yu Tsai  * set to 0. This means for these old device trees, we cannot just look
584e8d5bbf7SChen-Yu Tsai  * up the remote endpoint ID of a TCON input endpoint. TCON1 would be
585e8d5bbf7SChen-Yu Tsai  * incorrectly identified as TCON0.
586e8d5bbf7SChen-Yu Tsai  *
587e8d5bbf7SChen-Yu Tsai  * This function first checks if the TCON node has 2 input endpoints.
588e8d5bbf7SChen-Yu Tsai  * If so, then the device tree is a corrected version, and it will use
589e8d5bbf7SChen-Yu Tsai  * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above
590e8d5bbf7SChen-Yu Tsai  * to fetch the ID and engine directly. If not, then it is likely an
591e8d5bbf7SChen-Yu Tsai  * old device trees, where the endpoint IDs were incorrect, but did not
592e8d5bbf7SChen-Yu Tsai  * have endpoint connections between the backend and TCON across
593e8d5bbf7SChen-Yu Tsai  * different display pipelines. It will fall back to the old method of
594e8d5bbf7SChen-Yu Tsai  * traversing the  of_graph to try and find a matching engine by device
595e8d5bbf7SChen-Yu Tsai  * node.
596e8d5bbf7SChen-Yu Tsai  *
597e8d5bbf7SChen-Yu Tsai  * In the case of single display pipeline device trees, either method
598e8d5bbf7SChen-Yu Tsai  * works.
599e8d5bbf7SChen-Yu Tsai  */
600e8d5bbf7SChen-Yu Tsai static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
601e8d5bbf7SChen-Yu Tsai 						   struct device_node *node)
602e8d5bbf7SChen-Yu Tsai {
603e8d5bbf7SChen-Yu Tsai 	struct device_node *port;
604e8d5bbf7SChen-Yu Tsai 	struct sunxi_engine *engine;
605e8d5bbf7SChen-Yu Tsai 
606e8d5bbf7SChen-Yu Tsai 	port = of_graph_get_port_by_id(node, 0);
607e8d5bbf7SChen-Yu Tsai 	if (!port)
608e8d5bbf7SChen-Yu Tsai 		return ERR_PTR(-EINVAL);
609e8d5bbf7SChen-Yu Tsai 
610e8d5bbf7SChen-Yu Tsai 	/*
611e8d5bbf7SChen-Yu Tsai 	 * Is this a corrected device tree with cross pipeline
612e8d5bbf7SChen-Yu Tsai 	 * connections between the backend and TCON?
613e8d5bbf7SChen-Yu Tsai 	 */
614e8d5bbf7SChen-Yu Tsai 	if (of_get_child_count(port) > 1) {
615e8d5bbf7SChen-Yu Tsai 		/* Get our ID directly from an upstream endpoint */
616e8d5bbf7SChen-Yu Tsai 		int id = sun4i_tcon_of_get_id_from_port(port);
617e8d5bbf7SChen-Yu Tsai 
618e8d5bbf7SChen-Yu Tsai 		/* Get our engine by matching our ID */
619e8d5bbf7SChen-Yu Tsai 		engine = sun4i_tcon_get_engine_by_id(drv, id);
620e8d5bbf7SChen-Yu Tsai 
621e8d5bbf7SChen-Yu Tsai 		of_node_put(port);
622e8d5bbf7SChen-Yu Tsai 		return engine;
623e8d5bbf7SChen-Yu Tsai 	}
624e8d5bbf7SChen-Yu Tsai 
625e8d5bbf7SChen-Yu Tsai 	/* Fallback to old method by traversing input endpoints */
626e8d5bbf7SChen-Yu Tsai 	of_node_put(port);
627e8d5bbf7SChen-Yu Tsai 	return sun4i_tcon_find_engine_traverse(drv, node);
628e8d5bbf7SChen-Yu Tsai }
629e8d5bbf7SChen-Yu Tsai 
6309026e0d1SMaxime Ripard static int sun4i_tcon_bind(struct device *dev, struct device *master,
6319026e0d1SMaxime Ripard 			   void *data)
6329026e0d1SMaxime Ripard {
6339026e0d1SMaxime Ripard 	struct drm_device *drm = data;
6349026e0d1SMaxime Ripard 	struct sun4i_drv *drv = drm->dev_private;
63587969338SIcenowy Zheng 	struct sunxi_engine *engine;
6369026e0d1SMaxime Ripard 	struct sun4i_tcon *tcon;
6379026e0d1SMaxime Ripard 	int ret;
6389026e0d1SMaxime Ripard 
63987969338SIcenowy Zheng 	engine = sun4i_tcon_find_engine(drv, dev->of_node);
64087969338SIcenowy Zheng 	if (IS_ERR(engine)) {
64187969338SIcenowy Zheng 		dev_err(dev, "Couldn't find matching engine\n");
64280a58240SChen-Yu Tsai 		return -EPROBE_DEFER;
643b317fa3bSChen-Yu Tsai 	}
64480a58240SChen-Yu Tsai 
6459026e0d1SMaxime Ripard 	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
6469026e0d1SMaxime Ripard 	if (!tcon)
6479026e0d1SMaxime Ripard 		return -ENOMEM;
6489026e0d1SMaxime Ripard 	dev_set_drvdata(dev, tcon);
6499026e0d1SMaxime Ripard 	tcon->drm = drm;
650ae558110SMaxime Ripard 	tcon->dev = dev;
65187969338SIcenowy Zheng 	tcon->id = engine->id;
65291ea2f29SChen-Yu Tsai 	tcon->quirks = of_device_get_match_data(dev);
6539026e0d1SMaxime Ripard 
6549026e0d1SMaxime Ripard 	tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
6559026e0d1SMaxime Ripard 	if (IS_ERR(tcon->lcd_rst)) {
6569026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't get our reset line\n");
6579026e0d1SMaxime Ripard 		return PTR_ERR(tcon->lcd_rst);
6589026e0d1SMaxime Ripard 	}
6599026e0d1SMaxime Ripard 
6609026e0d1SMaxime Ripard 	/* Make sure our TCON is reset */
661d57294c1SChen-Yu Tsai 	ret = reset_control_reset(tcon->lcd_rst);
6629026e0d1SMaxime Ripard 	if (ret) {
6639026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't deassert our reset line\n");
6649026e0d1SMaxime Ripard 		return ret;
6659026e0d1SMaxime Ripard 	}
6669026e0d1SMaxime Ripard 
6679026e0d1SMaxime Ripard 	ret = sun4i_tcon_init_clocks(dev, tcon);
6689026e0d1SMaxime Ripard 	if (ret) {
6699026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't init our TCON clocks\n");
6709026e0d1SMaxime Ripard 		goto err_assert_reset;
6719026e0d1SMaxime Ripard 	}
6729026e0d1SMaxime Ripard 
6734c7f16d1SChen-Yu Tsai 	ret = sun4i_tcon_init_regmap(dev, tcon);
6749026e0d1SMaxime Ripard 	if (ret) {
6754c7f16d1SChen-Yu Tsai 		dev_err(dev, "Couldn't init our TCON regmap\n");
6769026e0d1SMaxime Ripard 		goto err_free_clocks;
6779026e0d1SMaxime Ripard 	}
6789026e0d1SMaxime Ripard 
6794c7f16d1SChen-Yu Tsai 	ret = sun4i_dclk_create(dev, tcon);
6804c7f16d1SChen-Yu Tsai 	if (ret) {
6814c7f16d1SChen-Yu Tsai 		dev_err(dev, "Couldn't create our TCON dot clock\n");
6824c7f16d1SChen-Yu Tsai 		goto err_free_clocks;
6834c7f16d1SChen-Yu Tsai 	}
6844c7f16d1SChen-Yu Tsai 
6859026e0d1SMaxime Ripard 	ret = sun4i_tcon_init_irq(dev, tcon);
6869026e0d1SMaxime Ripard 	if (ret) {
6879026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't init our TCON interrupts\n");
6884c7f16d1SChen-Yu Tsai 		goto err_free_dotclock;
6899026e0d1SMaxime Ripard 	}
6909026e0d1SMaxime Ripard 
69187969338SIcenowy Zheng 	tcon->crtc = sun4i_crtc_init(drm, engine, tcon);
69246cce6daSChen-Yu Tsai 	if (IS_ERR(tcon->crtc)) {
69346cce6daSChen-Yu Tsai 		dev_err(dev, "Couldn't create our CRTC\n");
69446cce6daSChen-Yu Tsai 		ret = PTR_ERR(tcon->crtc);
69546cce6daSChen-Yu Tsai 		goto err_free_clocks;
69646cce6daSChen-Yu Tsai 	}
69746cce6daSChen-Yu Tsai 
698b9c8506cSChen-Yu Tsai 	ret = sun4i_rgb_init(drm, tcon);
69913fef095SChen-Yu Tsai 	if (ret < 0)
70013fef095SChen-Yu Tsai 		goto err_free_clocks;
70113fef095SChen-Yu Tsai 
70280a58240SChen-Yu Tsai 	list_add_tail(&tcon->list, &drv->tcon_list);
70380a58240SChen-Yu Tsai 
70413fef095SChen-Yu Tsai 	return 0;
7059026e0d1SMaxime Ripard 
7064c7f16d1SChen-Yu Tsai err_free_dotclock:
7074c7f16d1SChen-Yu Tsai 	sun4i_dclk_free(tcon);
7089026e0d1SMaxime Ripard err_free_clocks:
7099026e0d1SMaxime Ripard 	sun4i_tcon_free_clocks(tcon);
7109026e0d1SMaxime Ripard err_assert_reset:
7119026e0d1SMaxime Ripard 	reset_control_assert(tcon->lcd_rst);
7129026e0d1SMaxime Ripard 	return ret;
7139026e0d1SMaxime Ripard }
7149026e0d1SMaxime Ripard 
7159026e0d1SMaxime Ripard static void sun4i_tcon_unbind(struct device *dev, struct device *master,
7169026e0d1SMaxime Ripard 			      void *data)
7179026e0d1SMaxime Ripard {
7189026e0d1SMaxime Ripard 	struct sun4i_tcon *tcon = dev_get_drvdata(dev);
7199026e0d1SMaxime Ripard 
72080a58240SChen-Yu Tsai 	list_del(&tcon->list);
7214c7f16d1SChen-Yu Tsai 	sun4i_dclk_free(tcon);
7229026e0d1SMaxime Ripard 	sun4i_tcon_free_clocks(tcon);
7239026e0d1SMaxime Ripard }
7249026e0d1SMaxime Ripard 
725dfeb693dSJulia Lawall static const struct component_ops sun4i_tcon_ops = {
7269026e0d1SMaxime Ripard 	.bind	= sun4i_tcon_bind,
7279026e0d1SMaxime Ripard 	.unbind	= sun4i_tcon_unbind,
7289026e0d1SMaxime Ripard };
7299026e0d1SMaxime Ripard 
7309026e0d1SMaxime Ripard static int sun4i_tcon_probe(struct platform_device *pdev)
7319026e0d1SMaxime Ripard {
73229e57fabSMaxime Ripard 	struct device_node *node = pdev->dev.of_node;
733894f5a9fSMaxime Ripard 	struct drm_bridge *bridge;
73429e57fabSMaxime Ripard 	struct drm_panel *panel;
735ebc94461SRob Herring 	int ret;
73629e57fabSMaxime Ripard 
737ebc94461SRob Herring 	ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge);
738ebc94461SRob Herring 	if (ret == -EPROBE_DEFER)
739ebc94461SRob Herring 		return ret;
74029e57fabSMaxime Ripard 
7419026e0d1SMaxime Ripard 	return component_add(&pdev->dev, &sun4i_tcon_ops);
7429026e0d1SMaxime Ripard }
7439026e0d1SMaxime Ripard 
7449026e0d1SMaxime Ripard static int sun4i_tcon_remove(struct platform_device *pdev)
7459026e0d1SMaxime Ripard {
7469026e0d1SMaxime Ripard 	component_del(&pdev->dev, &sun4i_tcon_ops);
7479026e0d1SMaxime Ripard 
7489026e0d1SMaxime Ripard 	return 0;
7499026e0d1SMaxime Ripard }
7509026e0d1SMaxime Ripard 
75191ea2f29SChen-Yu Tsai static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
75291ea2f29SChen-Yu Tsai 	.has_unknown_mux = true,
75391ea2f29SChen-Yu Tsai 	.has_channel_1	= true,
75491ea2f29SChen-Yu Tsai };
75591ea2f29SChen-Yu Tsai 
75693a5ec14SChen-Yu Tsai static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
75793a5ec14SChen-Yu Tsai 	.has_channel_1	= true,
75893a5ec14SChen-Yu Tsai };
75993a5ec14SChen-Yu Tsai 
76093a5ec14SChen-Yu Tsai static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
76193a5ec14SChen-Yu Tsai 	.has_channel_1	= true,
76293a5ec14SChen-Yu Tsai };
76393a5ec14SChen-Yu Tsai 
76491ea2f29SChen-Yu Tsai static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
76591ea2f29SChen-Yu Tsai 	/* nothing is supported */
76691ea2f29SChen-Yu Tsai };
76791ea2f29SChen-Yu Tsai 
7681a0edb3fSIcenowy Zheng static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
7691a0edb3fSIcenowy Zheng 	/* nothing is supported */
7701a0edb3fSIcenowy Zheng };
7711a0edb3fSIcenowy Zheng 
7729026e0d1SMaxime Ripard static const struct of_device_id sun4i_tcon_of_table[] = {
77391ea2f29SChen-Yu Tsai 	{ .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
77493a5ec14SChen-Yu Tsai 	{ .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
77593a5ec14SChen-Yu Tsai 	{ .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
77691ea2f29SChen-Yu Tsai 	{ .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
7771a0edb3fSIcenowy Zheng 	{ .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
7789026e0d1SMaxime Ripard 	{ }
7799026e0d1SMaxime Ripard };
7809026e0d1SMaxime Ripard MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
7819026e0d1SMaxime Ripard 
7829026e0d1SMaxime Ripard static struct platform_driver sun4i_tcon_platform_driver = {
7839026e0d1SMaxime Ripard 	.probe		= sun4i_tcon_probe,
7849026e0d1SMaxime Ripard 	.remove		= sun4i_tcon_remove,
7859026e0d1SMaxime Ripard 	.driver		= {
7869026e0d1SMaxime Ripard 		.name		= "sun4i-tcon",
7879026e0d1SMaxime Ripard 		.of_match_table	= sun4i_tcon_of_table,
7889026e0d1SMaxime Ripard 	},
7899026e0d1SMaxime Ripard };
7909026e0d1SMaxime Ripard module_platform_driver(sun4i_tcon_platform_driver);
7919026e0d1SMaxime Ripard 
7929026e0d1SMaxime Ripard MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
7939026e0d1SMaxime Ripard MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver");
7949026e0d1SMaxime Ripard MODULE_LICENSE("GPL");
795