xref: /openbmc/linux/drivers/gpu/drm/sun4i/sun4i_tcon.c (revision 86a3ae587980f857284a11b86ef345f47298aade)
19026e0d1SMaxime Ripard /*
29026e0d1SMaxime Ripard  * Copyright (C) 2015 Free Electrons
39026e0d1SMaxime Ripard  * Copyright (C) 2015 NextThing Co
49026e0d1SMaxime Ripard  *
59026e0d1SMaxime Ripard  * Maxime Ripard <maxime.ripard@free-electrons.com>
69026e0d1SMaxime Ripard  *
79026e0d1SMaxime Ripard  * This program is free software; you can redistribute it and/or
89026e0d1SMaxime Ripard  * modify it under the terms of the GNU General Public License as
99026e0d1SMaxime Ripard  * published by the Free Software Foundation; either version 2 of
109026e0d1SMaxime Ripard  * the License, or (at your option) any later version.
119026e0d1SMaxime Ripard  */
129026e0d1SMaxime Ripard 
139026e0d1SMaxime Ripard #include <drm/drmP.h>
149026e0d1SMaxime Ripard #include <drm/drm_atomic_helper.h>
159026e0d1SMaxime Ripard #include <drm/drm_crtc.h>
169026e0d1SMaxime Ripard #include <drm/drm_crtc_helper.h>
17ad537fb2SChen-Yu Tsai #include <drm/drm_encoder.h>
189026e0d1SMaxime Ripard #include <drm/drm_modes.h>
19ebc94461SRob Herring #include <drm/drm_of.h>
209026e0d1SMaxime Ripard 
21ad537fb2SChen-Yu Tsai #include <uapi/drm/drm_mode.h>
22ad537fb2SChen-Yu Tsai 
239026e0d1SMaxime Ripard #include <linux/component.h>
249026e0d1SMaxime Ripard #include <linux/ioport.h>
259026e0d1SMaxime Ripard #include <linux/of_address.h>
2691ea2f29SChen-Yu Tsai #include <linux/of_device.h>
279026e0d1SMaxime Ripard #include <linux/of_irq.h>
289026e0d1SMaxime Ripard #include <linux/regmap.h>
299026e0d1SMaxime Ripard #include <linux/reset.h>
309026e0d1SMaxime Ripard 
319026e0d1SMaxime Ripard #include "sun4i_crtc.h"
329026e0d1SMaxime Ripard #include "sun4i_dotclock.h"
339026e0d1SMaxime Ripard #include "sun4i_drv.h"
34a0c1214eSMaxime Ripard #include "sun4i_lvds.h"
3529e57fabSMaxime Ripard #include "sun4i_rgb.h"
369026e0d1SMaxime Ripard #include "sun4i_tcon.h"
3787969338SIcenowy Zheng #include "sunxi_engine.h"
389026e0d1SMaxime Ripard 
39a0c1214eSMaxime Ripard static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder)
40a0c1214eSMaxime Ripard {
41a0c1214eSMaxime Ripard 	struct drm_connector *connector;
42a0c1214eSMaxime Ripard 	struct drm_connector_list_iter iter;
43a0c1214eSMaxime Ripard 
44a0c1214eSMaxime Ripard 	drm_connector_list_iter_begin(encoder->dev, &iter);
45a0c1214eSMaxime Ripard 	drm_for_each_connector_iter(connector, &iter)
46a0c1214eSMaxime Ripard 		if (connector->encoder == encoder) {
47a0c1214eSMaxime Ripard 			drm_connector_list_iter_end(&iter);
48a0c1214eSMaxime Ripard 			return connector;
49a0c1214eSMaxime Ripard 		}
50a0c1214eSMaxime Ripard 	drm_connector_list_iter_end(&iter);
51a0c1214eSMaxime Ripard 
52a0c1214eSMaxime Ripard 	return NULL;
53a0c1214eSMaxime Ripard }
54a0c1214eSMaxime Ripard 
55a0c1214eSMaxime Ripard static int sun4i_tcon_get_pixel_depth(const struct drm_encoder *encoder)
56a0c1214eSMaxime Ripard {
57a0c1214eSMaxime Ripard 	struct drm_connector *connector;
58a0c1214eSMaxime Ripard 	struct drm_display_info *info;
59a0c1214eSMaxime Ripard 
60a0c1214eSMaxime Ripard 	connector = sun4i_tcon_get_connector(encoder);
61a0c1214eSMaxime Ripard 	if (!connector)
62a0c1214eSMaxime Ripard 		return -EINVAL;
63a0c1214eSMaxime Ripard 
64a0c1214eSMaxime Ripard 	info = &connector->display_info;
65a0c1214eSMaxime Ripard 	if (info->num_bus_formats != 1)
66a0c1214eSMaxime Ripard 		return -EINVAL;
67a0c1214eSMaxime Ripard 
68a0c1214eSMaxime Ripard 	switch (info->bus_formats[0]) {
69a0c1214eSMaxime Ripard 	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
70a0c1214eSMaxime Ripard 		return 18;
71a0c1214eSMaxime Ripard 
72a0c1214eSMaxime Ripard 	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
73a0c1214eSMaxime Ripard 	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
74a0c1214eSMaxime Ripard 		return 24;
75a0c1214eSMaxime Ripard 	}
76a0c1214eSMaxime Ripard 
77a0c1214eSMaxime Ripard 	return -EINVAL;
78a0c1214eSMaxime Ripard }
79a0c1214eSMaxime Ripard 
8045e88f99SMaxime Ripard static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
8145e88f99SMaxime Ripard 					  bool enabled)
829026e0d1SMaxime Ripard {
8345e88f99SMaxime Ripard 	struct clk *clk;
849026e0d1SMaxime Ripard 
8545e88f99SMaxime Ripard 	switch (channel) {
8645e88f99SMaxime Ripard 	case 0:
879026e0d1SMaxime Ripard 		regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
889026e0d1SMaxime Ripard 				   SUN4I_TCON0_CTL_TCON_ENABLE,
8945e88f99SMaxime Ripard 				   enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0);
9045e88f99SMaxime Ripard 		clk = tcon->dclk;
9145e88f99SMaxime Ripard 		break;
9245e88f99SMaxime Ripard 	case 1:
9391ea2f29SChen-Yu Tsai 		WARN_ON(!tcon->quirks->has_channel_1);
949026e0d1SMaxime Ripard 		regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
959026e0d1SMaxime Ripard 				   SUN4I_TCON1_CTL_TCON_ENABLE,
9645e88f99SMaxime Ripard 				   enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0);
9745e88f99SMaxime Ripard 		clk = tcon->sclk1;
9845e88f99SMaxime Ripard 		break;
9945e88f99SMaxime Ripard 	default:
10045e88f99SMaxime Ripard 		DRM_WARN("Unknown channel... doing nothing\n");
10145e88f99SMaxime Ripard 		return;
1029026e0d1SMaxime Ripard 	}
10345e88f99SMaxime Ripard 
10445e88f99SMaxime Ripard 	if (enabled)
10545e88f99SMaxime Ripard 		clk_prepare_enable(clk);
10645e88f99SMaxime Ripard 	else
10745e88f99SMaxime Ripard 		clk_disable_unprepare(clk);
10845e88f99SMaxime Ripard }
10945e88f99SMaxime Ripard 
110a0c1214eSMaxime Ripard static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
111a0c1214eSMaxime Ripard 				       const struct drm_encoder *encoder,
112a0c1214eSMaxime Ripard 				       bool enabled)
113a0c1214eSMaxime Ripard {
114a0c1214eSMaxime Ripard 	if (enabled) {
115a0c1214eSMaxime Ripard 		u8 val;
116a0c1214eSMaxime Ripard 
117a0c1214eSMaxime Ripard 		regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
118a0c1214eSMaxime Ripard 				   SUN4I_TCON0_LVDS_IF_EN,
119a0c1214eSMaxime Ripard 				   SUN4I_TCON0_LVDS_IF_EN);
120a0c1214eSMaxime Ripard 
121a0c1214eSMaxime Ripard 		/*
122a0c1214eSMaxime Ripard 		 * As their name suggest, these values only apply to the A31
123a0c1214eSMaxime Ripard 		 * and later SoCs. We'll have to rework this when merging
124a0c1214eSMaxime Ripard 		 * support for the older SoCs.
125a0c1214eSMaxime Ripard 		 */
126a0c1214eSMaxime Ripard 		regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
127a0c1214eSMaxime Ripard 			     SUN6I_TCON0_LVDS_ANA0_C(2) |
128a0c1214eSMaxime Ripard 			     SUN6I_TCON0_LVDS_ANA0_V(3) |
129a0c1214eSMaxime Ripard 			     SUN6I_TCON0_LVDS_ANA0_PD(2) |
130a0c1214eSMaxime Ripard 			     SUN6I_TCON0_LVDS_ANA0_EN_LDO);
131a0c1214eSMaxime Ripard 		udelay(2);
132a0c1214eSMaxime Ripard 
133a0c1214eSMaxime Ripard 		regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
134a0c1214eSMaxime Ripard 				   SUN6I_TCON0_LVDS_ANA0_EN_MB,
135a0c1214eSMaxime Ripard 				   SUN6I_TCON0_LVDS_ANA0_EN_MB);
136a0c1214eSMaxime Ripard 		udelay(2);
137a0c1214eSMaxime Ripard 
138a0c1214eSMaxime Ripard 		regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
139a0c1214eSMaxime Ripard 				   SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
140a0c1214eSMaxime Ripard 				   SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
141a0c1214eSMaxime Ripard 
142a0c1214eSMaxime Ripard 		if (sun4i_tcon_get_pixel_depth(encoder) == 18)
143a0c1214eSMaxime Ripard 			val = 7;
144a0c1214eSMaxime Ripard 		else
145a0c1214eSMaxime Ripard 			val = 0xf;
146a0c1214eSMaxime Ripard 
147a0c1214eSMaxime Ripard 		regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
148a0c1214eSMaxime Ripard 				  SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
149a0c1214eSMaxime Ripard 				  SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
150a0c1214eSMaxime Ripard 	} else {
151a0c1214eSMaxime Ripard 		regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
152a0c1214eSMaxime Ripard 				   SUN4I_TCON0_LVDS_IF_EN, 0);
153a0c1214eSMaxime Ripard 	}
154a0c1214eSMaxime Ripard }
155a0c1214eSMaxime Ripard 
15645e88f99SMaxime Ripard void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
15745e88f99SMaxime Ripard 			   const struct drm_encoder *encoder,
15845e88f99SMaxime Ripard 			   bool enabled)
15945e88f99SMaxime Ripard {
160a0c1214eSMaxime Ripard 	bool is_lvds = false;
16145e88f99SMaxime Ripard 	int channel;
16245e88f99SMaxime Ripard 
16345e88f99SMaxime Ripard 	switch (encoder->encoder_type) {
164a0c1214eSMaxime Ripard 	case DRM_MODE_ENCODER_LVDS:
165a0c1214eSMaxime Ripard 		is_lvds = true;
166a0c1214eSMaxime Ripard 		/* Fallthrough */
16745e88f99SMaxime Ripard 	case DRM_MODE_ENCODER_NONE:
16845e88f99SMaxime Ripard 		channel = 0;
16945e88f99SMaxime Ripard 		break;
17045e88f99SMaxime Ripard 	case DRM_MODE_ENCODER_TMDS:
17145e88f99SMaxime Ripard 	case DRM_MODE_ENCODER_TVDAC:
17245e88f99SMaxime Ripard 		channel = 1;
17345e88f99SMaxime Ripard 		break;
17445e88f99SMaxime Ripard 	default:
17545e88f99SMaxime Ripard 		DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
17645e88f99SMaxime Ripard 		return;
17745e88f99SMaxime Ripard 	}
17845e88f99SMaxime Ripard 
179a0c1214eSMaxime Ripard 	if (is_lvds && !enabled)
180a0c1214eSMaxime Ripard 		sun4i_tcon_lvds_set_status(tcon, encoder, false);
181a0c1214eSMaxime Ripard 
18245e88f99SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
18345e88f99SMaxime Ripard 			   SUN4I_TCON_GCTL_TCON_ENABLE,
18445e88f99SMaxime Ripard 			   enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0);
18545e88f99SMaxime Ripard 
186a0c1214eSMaxime Ripard 	if (is_lvds && enabled)
187a0c1214eSMaxime Ripard 		sun4i_tcon_lvds_set_status(tcon, encoder, true);
188a0c1214eSMaxime Ripard 
18945e88f99SMaxime Ripard 	sun4i_tcon_channel_set_status(tcon, channel, enabled);
19045e88f99SMaxime Ripard }
1919026e0d1SMaxime Ripard 
1929026e0d1SMaxime Ripard void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
1939026e0d1SMaxime Ripard {
1949026e0d1SMaxime Ripard 	u32 mask, val = 0;
1959026e0d1SMaxime Ripard 
1969026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");
1979026e0d1SMaxime Ripard 
1989026e0d1SMaxime Ripard 	mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
1999026e0d1SMaxime Ripard 	       SUN4I_TCON_GINT0_VBLANK_ENABLE(1);
2009026e0d1SMaxime Ripard 
2019026e0d1SMaxime Ripard 	if (enable)
2029026e0d1SMaxime Ripard 		val = mask;
2039026e0d1SMaxime Ripard 
2049026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);
2059026e0d1SMaxime Ripard }
2069026e0d1SMaxime Ripard EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
2079026e0d1SMaxime Ripard 
20867e32645SChen-Yu Tsai /*
20967e32645SChen-Yu Tsai  * This function is a helper for TCON output muxing. The TCON output
21067e32645SChen-Yu Tsai  * muxing control register in earlier SoCs (without the TCON TOP block)
21167e32645SChen-Yu Tsai  * are located in TCON0. This helper returns a pointer to TCON0's
21267e32645SChen-Yu Tsai  * sun4i_tcon structure, or NULL if not found.
21367e32645SChen-Yu Tsai  */
21467e32645SChen-Yu Tsai static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm)
21567e32645SChen-Yu Tsai {
21667e32645SChen-Yu Tsai 	struct sun4i_drv *drv = drm->dev_private;
21767e32645SChen-Yu Tsai 	struct sun4i_tcon *tcon;
21867e32645SChen-Yu Tsai 
21967e32645SChen-Yu Tsai 	list_for_each_entry(tcon, &drv->tcon_list, list)
22067e32645SChen-Yu Tsai 		if (tcon->id == 0)
22167e32645SChen-Yu Tsai 			return tcon;
22267e32645SChen-Yu Tsai 
22367e32645SChen-Yu Tsai 	dev_warn(drm->dev,
22467e32645SChen-Yu Tsai 		 "TCON0 not found, display output muxing may not work\n");
22567e32645SChen-Yu Tsai 
22667e32645SChen-Yu Tsai 	return NULL;
22767e32645SChen-Yu Tsai }
22867e32645SChen-Yu Tsai 
229f8c73f4fSMaxime Ripard void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
230abcb8766SMaxime Ripard 			const struct drm_encoder *encoder)
231f8c73f4fSMaxime Ripard {
232ad537fb2SChen-Yu Tsai 	int ret = -ENOTSUPP;
233b7cb9b91SMaxime Ripard 
234ad537fb2SChen-Yu Tsai 	if (tcon->quirks->set_mux)
235ad537fb2SChen-Yu Tsai 		ret = tcon->quirks->set_mux(tcon, encoder);
236f8c73f4fSMaxime Ripard 
237ad537fb2SChen-Yu Tsai 	DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n",
238ad537fb2SChen-Yu Tsai 			 encoder->name, encoder->crtc->name, ret);
239f8c73f4fSMaxime Ripard }
240f8c73f4fSMaxime Ripard 
241961c645cSMaxime Ripard static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode,
2429026e0d1SMaxime Ripard 				    int channel)
2439026e0d1SMaxime Ripard {
2449026e0d1SMaxime Ripard 	int delay = mode->vtotal - mode->vdisplay;
2459026e0d1SMaxime Ripard 
2469026e0d1SMaxime Ripard 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2479026e0d1SMaxime Ripard 		delay /= 2;
2489026e0d1SMaxime Ripard 
2499026e0d1SMaxime Ripard 	if (channel == 1)
2509026e0d1SMaxime Ripard 		delay -= 2;
2519026e0d1SMaxime Ripard 
2529026e0d1SMaxime Ripard 	delay = min(delay, 30);
2539026e0d1SMaxime Ripard 
2549026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay);
2559026e0d1SMaxime Ripard 
2569026e0d1SMaxime Ripard 	return delay;
2579026e0d1SMaxime Ripard }
2589026e0d1SMaxime Ripard 
259ba19c537SMaxime Ripard static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
260ba19c537SMaxime Ripard 					const struct drm_display_mode *mode)
261ba19c537SMaxime Ripard {
262ba19c537SMaxime Ripard 	/* Configure the dot clock */
263ba19c537SMaxime Ripard 	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
264ba19c537SMaxime Ripard 
265ba19c537SMaxime Ripard 	/* Set the resolution */
266ba19c537SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
267ba19c537SMaxime Ripard 		     SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
268ba19c537SMaxime Ripard 		     SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
269ba19c537SMaxime Ripard }
270ba19c537SMaxime Ripard 
271a0c1214eSMaxime Ripard static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
272a0c1214eSMaxime Ripard 				      const struct drm_encoder *encoder,
273a0c1214eSMaxime Ripard 				      const struct drm_display_mode *mode)
274a0c1214eSMaxime Ripard {
275a0c1214eSMaxime Ripard 	unsigned int bp;
276a0c1214eSMaxime Ripard 	u8 clk_delay;
277a0c1214eSMaxime Ripard 	u32 reg, val = 0;
278a0c1214eSMaxime Ripard 
279a0c1214eSMaxime Ripard 	tcon->dclk_min_div = 7;
280a0c1214eSMaxime Ripard 	tcon->dclk_max_div = 7;
281a0c1214eSMaxime Ripard 	sun4i_tcon0_mode_set_common(tcon, mode);
282a0c1214eSMaxime Ripard 
283a0c1214eSMaxime Ripard 	/* Adjust clock delay */
284a0c1214eSMaxime Ripard 	clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
285a0c1214eSMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
286a0c1214eSMaxime Ripard 			   SUN4I_TCON0_CTL_CLK_DELAY_MASK,
287a0c1214eSMaxime Ripard 			   SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
288a0c1214eSMaxime Ripard 
289a0c1214eSMaxime Ripard 	/*
290a0c1214eSMaxime Ripard 	 * This is called a backporch in the register documentation,
291a0c1214eSMaxime Ripard 	 * but it really is the back porch + hsync
292a0c1214eSMaxime Ripard 	 */
293a0c1214eSMaxime Ripard 	bp = mode->crtc_htotal - mode->crtc_hsync_start;
294a0c1214eSMaxime Ripard 	DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
295a0c1214eSMaxime Ripard 			 mode->crtc_htotal, bp);
296a0c1214eSMaxime Ripard 
297a0c1214eSMaxime Ripard 	/* Set horizontal display timings */
298a0c1214eSMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
299a0c1214eSMaxime Ripard 		     SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) |
300a0c1214eSMaxime Ripard 		     SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
301a0c1214eSMaxime Ripard 
302a0c1214eSMaxime Ripard 	/*
303a0c1214eSMaxime Ripard 	 * This is called a backporch in the register documentation,
304a0c1214eSMaxime Ripard 	 * but it really is the back porch + hsync
305a0c1214eSMaxime Ripard 	 */
306a0c1214eSMaxime Ripard 	bp = mode->crtc_vtotal - mode->crtc_vsync_start;
307a0c1214eSMaxime Ripard 	DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
308a0c1214eSMaxime Ripard 			 mode->crtc_vtotal, bp);
309a0c1214eSMaxime Ripard 
310a0c1214eSMaxime Ripard 	/* Set vertical display timings */
311a0c1214eSMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
312a0c1214eSMaxime Ripard 		     SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
313a0c1214eSMaxime Ripard 		     SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
314a0c1214eSMaxime Ripard 
315a0c1214eSMaxime Ripard 	reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 |
316a0c1214eSMaxime Ripard 		SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL |
317a0c1214eSMaxime Ripard 		SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL;
318a0c1214eSMaxime Ripard 	if (sun4i_tcon_get_pixel_depth(encoder) == 24)
319a0c1214eSMaxime Ripard 		reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS;
320a0c1214eSMaxime Ripard 	else
321a0c1214eSMaxime Ripard 		reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS;
322a0c1214eSMaxime Ripard 
323a0c1214eSMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg);
324a0c1214eSMaxime Ripard 
325a0c1214eSMaxime Ripard 	/* Setup the polarity of the various signals */
326a0c1214eSMaxime Ripard 	if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
327a0c1214eSMaxime Ripard 		val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
328a0c1214eSMaxime Ripard 
329a0c1214eSMaxime Ripard 	if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
330a0c1214eSMaxime Ripard 		val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
331a0c1214eSMaxime Ripard 
332a0c1214eSMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
333a0c1214eSMaxime Ripard 
334a0c1214eSMaxime Ripard 	/* Map output pins to channel 0 */
335a0c1214eSMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
336a0c1214eSMaxime Ripard 			   SUN4I_TCON_GCTL_IOMAP_MASK,
337a0c1214eSMaxime Ripard 			   SUN4I_TCON_GCTL_IOMAP_TCON0);
338a0c1214eSMaxime Ripard }
339a0c1214eSMaxime Ripard 
340ba19c537SMaxime Ripard static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
3415b8f0910SMaxime Ripard 				     const struct drm_display_mode *mode)
3429026e0d1SMaxime Ripard {
3439026e0d1SMaxime Ripard 	unsigned int bp, hsync, vsync;
3449026e0d1SMaxime Ripard 	u8 clk_delay;
3459026e0d1SMaxime Ripard 	u32 val = 0;
3469026e0d1SMaxime Ripard 
347ec08d596SMaxime Ripard 	tcon->dclk_min_div = 6;
348ec08d596SMaxime Ripard 	tcon->dclk_max_div = 127;
349ba19c537SMaxime Ripard 	sun4i_tcon0_mode_set_common(tcon, mode);
35086cf6788SChen-Yu Tsai 
3519026e0d1SMaxime Ripard 	/* Adjust clock delay */
3529026e0d1SMaxime Ripard 	clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
3539026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
3549026e0d1SMaxime Ripard 			   SUN4I_TCON0_CTL_CLK_DELAY_MASK,
3559026e0d1SMaxime Ripard 			   SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
3569026e0d1SMaxime Ripard 
3579026e0d1SMaxime Ripard 	/*
3589026e0d1SMaxime Ripard 	 * This is called a backporch in the register documentation,
35923a1cb11SChen-Yu Tsai 	 * but it really is the back porch + hsync
3609026e0d1SMaxime Ripard 	 */
3619026e0d1SMaxime Ripard 	bp = mode->crtc_htotal - mode->crtc_hsync_start;
3629026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
3639026e0d1SMaxime Ripard 			 mode->crtc_htotal, bp);
3649026e0d1SMaxime Ripard 
3659026e0d1SMaxime Ripard 	/* Set horizontal display timings */
3669026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
3679026e0d1SMaxime Ripard 		     SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) |
3689026e0d1SMaxime Ripard 		     SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
3699026e0d1SMaxime Ripard 
3709026e0d1SMaxime Ripard 	/*
3719026e0d1SMaxime Ripard 	 * This is called a backporch in the register documentation,
37223a1cb11SChen-Yu Tsai 	 * but it really is the back porch + hsync
3739026e0d1SMaxime Ripard 	 */
3749026e0d1SMaxime Ripard 	bp = mode->crtc_vtotal - mode->crtc_vsync_start;
3759026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
3769026e0d1SMaxime Ripard 			 mode->crtc_vtotal, bp);
3779026e0d1SMaxime Ripard 
3789026e0d1SMaxime Ripard 	/* Set vertical display timings */
3799026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
380a88cbbd4SMaxime Ripard 		     SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
3819026e0d1SMaxime Ripard 		     SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
3829026e0d1SMaxime Ripard 
3839026e0d1SMaxime Ripard 	/* Set Hsync and Vsync length */
3849026e0d1SMaxime Ripard 	hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
3859026e0d1SMaxime Ripard 	vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
3869026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
3879026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
3889026e0d1SMaxime Ripard 		     SUN4I_TCON0_BASIC3_V_SYNC(vsync) |
3899026e0d1SMaxime Ripard 		     SUN4I_TCON0_BASIC3_H_SYNC(hsync));
3909026e0d1SMaxime Ripard 
3919026e0d1SMaxime Ripard 	/* Setup the polarity of the various signals */
3929026e0d1SMaxime Ripard 	if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
3939026e0d1SMaxime Ripard 		val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
3949026e0d1SMaxime Ripard 
3959026e0d1SMaxime Ripard 	if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
3969026e0d1SMaxime Ripard 		val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
3979026e0d1SMaxime Ripard 
3989026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
3999026e0d1SMaxime Ripard 			   SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,
4009026e0d1SMaxime Ripard 			   val);
4019026e0d1SMaxime Ripard 
4029026e0d1SMaxime Ripard 	/* Map output pins to channel 0 */
4039026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
4049026e0d1SMaxime Ripard 			   SUN4I_TCON_GCTL_IOMAP_MASK,
4059026e0d1SMaxime Ripard 			   SUN4I_TCON_GCTL_IOMAP_TCON0);
4069026e0d1SMaxime Ripard 
4079026e0d1SMaxime Ripard 	/* Enable the output on the pins */
4089026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
4099026e0d1SMaxime Ripard }
4109026e0d1SMaxime Ripard 
4115b8f0910SMaxime Ripard static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
4125b8f0910SMaxime Ripard 				 const struct drm_display_mode *mode)
4139026e0d1SMaxime Ripard {
414b8317a3dSMaxime Ripard 	unsigned int bp, hsync, vsync, vtotal;
4159026e0d1SMaxime Ripard 	u8 clk_delay;
4169026e0d1SMaxime Ripard 	u32 val;
4179026e0d1SMaxime Ripard 
41891ea2f29SChen-Yu Tsai 	WARN_ON(!tcon->quirks->has_channel_1);
4198e924047SMaxime Ripard 
42086cf6788SChen-Yu Tsai 	/* Configure the dot clock */
42186cf6788SChen-Yu Tsai 	clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
42286cf6788SChen-Yu Tsai 
4239026e0d1SMaxime Ripard 	/* Adjust clock delay */
4249026e0d1SMaxime Ripard 	clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
4259026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
4269026e0d1SMaxime Ripard 			   SUN4I_TCON1_CTL_CLK_DELAY_MASK,
4279026e0d1SMaxime Ripard 			   SUN4I_TCON1_CTL_CLK_DELAY(clk_delay));
4289026e0d1SMaxime Ripard 
4299026e0d1SMaxime Ripard 	/* Set interlaced mode */
4309026e0d1SMaxime Ripard 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
4319026e0d1SMaxime Ripard 		val = SUN4I_TCON1_CTL_INTERLACE_ENABLE;
4329026e0d1SMaxime Ripard 	else
4339026e0d1SMaxime Ripard 		val = 0;
4349026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
4359026e0d1SMaxime Ripard 			   SUN4I_TCON1_CTL_INTERLACE_ENABLE,
4369026e0d1SMaxime Ripard 			   val);
4379026e0d1SMaxime Ripard 
4389026e0d1SMaxime Ripard 	/* Set the input resolution */
4399026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
4409026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) |
4419026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay));
4429026e0d1SMaxime Ripard 
4439026e0d1SMaxime Ripard 	/* Set the upscaling resolution */
4449026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
4459026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) |
4469026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay));
4479026e0d1SMaxime Ripard 
4489026e0d1SMaxime Ripard 	/* Set the output resolution */
4499026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
4509026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) |
4519026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
4529026e0d1SMaxime Ripard 
4539026e0d1SMaxime Ripard 	/* Set horizontal display timings */
4543cb2f46bSMaxime Ripard 	bp = mode->crtc_htotal - mode->crtc_hsync_start;
4559026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
4569026e0d1SMaxime Ripard 			 mode->htotal, bp);
4579026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
4589026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
4599026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
4609026e0d1SMaxime Ripard 
4613cb2f46bSMaxime Ripard 	bp = mode->crtc_vtotal - mode->crtc_vsync_start;
4629026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
463b8317a3dSMaxime Ripard 			 mode->crtc_vtotal, bp);
464b8317a3dSMaxime Ripard 
465b8317a3dSMaxime Ripard 	/*
466b8317a3dSMaxime Ripard 	 * The vertical resolution needs to be doubled in all
467b8317a3dSMaxime Ripard 	 * cases. We could use crtc_vtotal and always multiply by two,
468b8317a3dSMaxime Ripard 	 * but that leads to a rounding error in interlace when vtotal
469b8317a3dSMaxime Ripard 	 * is odd.
470b8317a3dSMaxime Ripard 	 *
471b8317a3dSMaxime Ripard 	 * This happens with TV's PAL for example, where vtotal will
472b8317a3dSMaxime Ripard 	 * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be
473b8317a3dSMaxime Ripard 	 * 624, which apparently confuses the hardware.
474b8317a3dSMaxime Ripard 	 *
475b8317a3dSMaxime Ripard 	 * To work around this, we will always use vtotal, and
476b8317a3dSMaxime Ripard 	 * multiply by two only if we're not in interlace.
477b8317a3dSMaxime Ripard 	 */
478b8317a3dSMaxime Ripard 	vtotal = mode->vtotal;
479b8317a3dSMaxime Ripard 	if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
480b8317a3dSMaxime Ripard 		vtotal = vtotal * 2;
481b8317a3dSMaxime Ripard 
482b8317a3dSMaxime Ripard 	/* Set vertical display timings */
4839026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
484b8317a3dSMaxime Ripard 		     SUN4I_TCON1_BASIC4_V_TOTAL(vtotal) |
4859026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
4869026e0d1SMaxime Ripard 
4879026e0d1SMaxime Ripard 	/* Set Hsync and Vsync length */
4889026e0d1SMaxime Ripard 	hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
4899026e0d1SMaxime Ripard 	vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
4909026e0d1SMaxime Ripard 	DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
4919026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,
4929026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
4939026e0d1SMaxime Ripard 		     SUN4I_TCON1_BASIC5_H_SYNC(hsync));
4949026e0d1SMaxime Ripard 
4959026e0d1SMaxime Ripard 	/* Map output pins to channel 1 */
4969026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
4979026e0d1SMaxime Ripard 			   SUN4I_TCON_GCTL_IOMAP_MASK,
4989026e0d1SMaxime Ripard 			   SUN4I_TCON_GCTL_IOMAP_TCON1);
4999026e0d1SMaxime Ripard }
5005b8f0910SMaxime Ripard 
5015b8f0910SMaxime Ripard void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
5025b8f0910SMaxime Ripard 			 const struct drm_encoder *encoder,
5035b8f0910SMaxime Ripard 			 const struct drm_display_mode *mode)
5045b8f0910SMaxime Ripard {
5055b8f0910SMaxime Ripard 	switch (encoder->encoder_type) {
506a0c1214eSMaxime Ripard 	case DRM_MODE_ENCODER_LVDS:
507a0c1214eSMaxime Ripard 		sun4i_tcon0_mode_set_lvds(tcon, encoder, mode);
508a0c1214eSMaxime Ripard 		break;
5095b8f0910SMaxime Ripard 	case DRM_MODE_ENCODER_NONE:
510ba19c537SMaxime Ripard 		sun4i_tcon0_mode_set_rgb(tcon, mode);
5115b8f0910SMaxime Ripard 		sun4i_tcon_set_mux(tcon, 0, encoder);
5125b8f0910SMaxime Ripard 		break;
5135b8f0910SMaxime Ripard 	case DRM_MODE_ENCODER_TVDAC:
5145b8f0910SMaxime Ripard 	case DRM_MODE_ENCODER_TMDS:
5155b8f0910SMaxime Ripard 		sun4i_tcon1_mode_set(tcon, mode);
5165b8f0910SMaxime Ripard 		sun4i_tcon_set_mux(tcon, 1, encoder);
5175b8f0910SMaxime Ripard 		break;
5185b8f0910SMaxime Ripard 	default:
5195b8f0910SMaxime Ripard 		DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
5205b8f0910SMaxime Ripard 	}
5215b8f0910SMaxime Ripard }
5225b8f0910SMaxime Ripard EXPORT_SYMBOL(sun4i_tcon_mode_set);
5239026e0d1SMaxime Ripard 
5249026e0d1SMaxime Ripard static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
5259026e0d1SMaxime Ripard 					struct sun4i_crtc *scrtc)
5269026e0d1SMaxime Ripard {
5279026e0d1SMaxime Ripard 	unsigned long flags;
5289026e0d1SMaxime Ripard 
5299026e0d1SMaxime Ripard 	spin_lock_irqsave(&dev->event_lock, flags);
5309026e0d1SMaxime Ripard 	if (scrtc->event) {
5319026e0d1SMaxime Ripard 		drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event);
5329026e0d1SMaxime Ripard 		drm_crtc_vblank_put(&scrtc->crtc);
5339026e0d1SMaxime Ripard 		scrtc->event = NULL;
5349026e0d1SMaxime Ripard 	}
5359026e0d1SMaxime Ripard 	spin_unlock_irqrestore(&dev->event_lock, flags);
5369026e0d1SMaxime Ripard }
5379026e0d1SMaxime Ripard 
5389026e0d1SMaxime Ripard static irqreturn_t sun4i_tcon_handler(int irq, void *private)
5399026e0d1SMaxime Ripard {
5409026e0d1SMaxime Ripard 	struct sun4i_tcon *tcon = private;
5419026e0d1SMaxime Ripard 	struct drm_device *drm = tcon->drm;
54246cce6daSChen-Yu Tsai 	struct sun4i_crtc *scrtc = tcon->crtc;
5439026e0d1SMaxime Ripard 	unsigned int status;
5449026e0d1SMaxime Ripard 
5459026e0d1SMaxime Ripard 	regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
5469026e0d1SMaxime Ripard 
5479026e0d1SMaxime Ripard 	if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
5489026e0d1SMaxime Ripard 			SUN4I_TCON_GINT0_VBLANK_INT(1))))
5499026e0d1SMaxime Ripard 		return IRQ_NONE;
5509026e0d1SMaxime Ripard 
5519026e0d1SMaxime Ripard 	drm_crtc_handle_vblank(&scrtc->crtc);
5529026e0d1SMaxime Ripard 	sun4i_tcon_finish_page_flip(drm, scrtc);
5539026e0d1SMaxime Ripard 
5549026e0d1SMaxime Ripard 	/* Acknowledge the interrupt */
5559026e0d1SMaxime Ripard 	regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
5569026e0d1SMaxime Ripard 			   SUN4I_TCON_GINT0_VBLANK_INT(0) |
5579026e0d1SMaxime Ripard 			   SUN4I_TCON_GINT0_VBLANK_INT(1),
5589026e0d1SMaxime Ripard 			   0);
5599026e0d1SMaxime Ripard 
5609026e0d1SMaxime Ripard 	return IRQ_HANDLED;
5619026e0d1SMaxime Ripard }
5629026e0d1SMaxime Ripard 
5639026e0d1SMaxime Ripard static int sun4i_tcon_init_clocks(struct device *dev,
5649026e0d1SMaxime Ripard 				  struct sun4i_tcon *tcon)
5659026e0d1SMaxime Ripard {
5669026e0d1SMaxime Ripard 	tcon->clk = devm_clk_get(dev, "ahb");
5679026e0d1SMaxime Ripard 	if (IS_ERR(tcon->clk)) {
5689026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't get the TCON bus clock\n");
5699026e0d1SMaxime Ripard 		return PTR_ERR(tcon->clk);
5709026e0d1SMaxime Ripard 	}
5719026e0d1SMaxime Ripard 	clk_prepare_enable(tcon->clk);
5729026e0d1SMaxime Ripard 
5739026e0d1SMaxime Ripard 	tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
5749026e0d1SMaxime Ripard 	if (IS_ERR(tcon->sclk0)) {
5759026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
5769026e0d1SMaxime Ripard 		return PTR_ERR(tcon->sclk0);
5779026e0d1SMaxime Ripard 	}
5789026e0d1SMaxime Ripard 
57991ea2f29SChen-Yu Tsai 	if (tcon->quirks->has_channel_1) {
5809026e0d1SMaxime Ripard 		tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
5819026e0d1SMaxime Ripard 		if (IS_ERR(tcon->sclk1)) {
5829026e0d1SMaxime Ripard 			dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
5839026e0d1SMaxime Ripard 			return PTR_ERR(tcon->sclk1);
5849026e0d1SMaxime Ripard 		}
5858e924047SMaxime Ripard 	}
5869026e0d1SMaxime Ripard 
5874c7f16d1SChen-Yu Tsai 	return 0;
5889026e0d1SMaxime Ripard }
5899026e0d1SMaxime Ripard 
5909026e0d1SMaxime Ripard static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
5919026e0d1SMaxime Ripard {
5929026e0d1SMaxime Ripard 	clk_disable_unprepare(tcon->clk);
5939026e0d1SMaxime Ripard }
5949026e0d1SMaxime Ripard 
5959026e0d1SMaxime Ripard static int sun4i_tcon_init_irq(struct device *dev,
5969026e0d1SMaxime Ripard 			       struct sun4i_tcon *tcon)
5979026e0d1SMaxime Ripard {
5989026e0d1SMaxime Ripard 	struct platform_device *pdev = to_platform_device(dev);
5999026e0d1SMaxime Ripard 	int irq, ret;
6009026e0d1SMaxime Ripard 
6019026e0d1SMaxime Ripard 	irq = platform_get_irq(pdev, 0);
6029026e0d1SMaxime Ripard 	if (irq < 0) {
6039026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't retrieve the TCON interrupt\n");
6049026e0d1SMaxime Ripard 		return irq;
6059026e0d1SMaxime Ripard 	}
6069026e0d1SMaxime Ripard 
6079026e0d1SMaxime Ripard 	ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0,
6089026e0d1SMaxime Ripard 			       dev_name(dev), tcon);
6099026e0d1SMaxime Ripard 	if (ret) {
6109026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't request the IRQ\n");
6119026e0d1SMaxime Ripard 		return ret;
6129026e0d1SMaxime Ripard 	}
6139026e0d1SMaxime Ripard 
6149026e0d1SMaxime Ripard 	return 0;
6159026e0d1SMaxime Ripard }
6169026e0d1SMaxime Ripard 
6179026e0d1SMaxime Ripard static struct regmap_config sun4i_tcon_regmap_config = {
6189026e0d1SMaxime Ripard 	.reg_bits	= 32,
6199026e0d1SMaxime Ripard 	.val_bits	= 32,
6209026e0d1SMaxime Ripard 	.reg_stride	= 4,
6219026e0d1SMaxime Ripard 	.max_register	= 0x800,
6229026e0d1SMaxime Ripard };
6239026e0d1SMaxime Ripard 
6249026e0d1SMaxime Ripard static int sun4i_tcon_init_regmap(struct device *dev,
6259026e0d1SMaxime Ripard 				  struct sun4i_tcon *tcon)
6269026e0d1SMaxime Ripard {
6279026e0d1SMaxime Ripard 	struct platform_device *pdev = to_platform_device(dev);
6289026e0d1SMaxime Ripard 	struct resource *res;
6299026e0d1SMaxime Ripard 	void __iomem *regs;
6309026e0d1SMaxime Ripard 
6319026e0d1SMaxime Ripard 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6329026e0d1SMaxime Ripard 	regs = devm_ioremap_resource(dev, res);
633af346f55SWei Yongjun 	if (IS_ERR(regs))
6349026e0d1SMaxime Ripard 		return PTR_ERR(regs);
6359026e0d1SMaxime Ripard 
6369026e0d1SMaxime Ripard 	tcon->regs = devm_regmap_init_mmio(dev, regs,
6379026e0d1SMaxime Ripard 					   &sun4i_tcon_regmap_config);
6389026e0d1SMaxime Ripard 	if (IS_ERR(tcon->regs)) {
6399026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't create the TCON regmap\n");
6409026e0d1SMaxime Ripard 		return PTR_ERR(tcon->regs);
6419026e0d1SMaxime Ripard 	}
6429026e0d1SMaxime Ripard 
6439026e0d1SMaxime Ripard 	/* Make sure the TCON is disabled and all IRQs are off */
6449026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
6459026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
6469026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
6479026e0d1SMaxime Ripard 
6489026e0d1SMaxime Ripard 	/* Disable IO lines and set them to tristate */
6499026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
6509026e0d1SMaxime Ripard 	regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
6519026e0d1SMaxime Ripard 
6529026e0d1SMaxime Ripard 	return 0;
6539026e0d1SMaxime Ripard }
6549026e0d1SMaxime Ripard 
655b317fa3bSChen-Yu Tsai /*
656b317fa3bSChen-Yu Tsai  * On SoCs with the old display pipeline design (Display Engine 1.0),
657b317fa3bSChen-Yu Tsai  * the TCON is always tied to just one backend. Hence we can traverse
658b317fa3bSChen-Yu Tsai  * the of_graph upwards to find the backend our tcon is connected to,
659b317fa3bSChen-Yu Tsai  * and take its ID as our own.
660b317fa3bSChen-Yu Tsai  *
661b317fa3bSChen-Yu Tsai  * We can either identify backends from their compatible strings, which
662b317fa3bSChen-Yu Tsai  * means maintaining a large list of them. Or, since the backend is
663b317fa3bSChen-Yu Tsai  * registered and binded before the TCON, we can just go through the
664b317fa3bSChen-Yu Tsai  * list of registered backends and compare the device node.
66587969338SIcenowy Zheng  *
66687969338SIcenowy Zheng  * As the structures now store engines instead of backends, here this
66787969338SIcenowy Zheng  * function in fact searches the corresponding engine, and the ID is
66887969338SIcenowy Zheng  * requested via the get_id function of the engine.
669b317fa3bSChen-Yu Tsai  */
670e8d5bbf7SChen-Yu Tsai static struct sunxi_engine *
671e8d5bbf7SChen-Yu Tsai sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv,
672b317fa3bSChen-Yu Tsai 				struct device_node *node)
673b317fa3bSChen-Yu Tsai {
674b317fa3bSChen-Yu Tsai 	struct device_node *port, *ep, *remote;
675be3fe0f9SChen-Yu Tsai 	struct sunxi_engine *engine = ERR_PTR(-EINVAL);
676b317fa3bSChen-Yu Tsai 
677b317fa3bSChen-Yu Tsai 	port = of_graph_get_port_by_id(node, 0);
678b317fa3bSChen-Yu Tsai 	if (!port)
679b317fa3bSChen-Yu Tsai 		return ERR_PTR(-EINVAL);
680b317fa3bSChen-Yu Tsai 
6811469619dSChen-Yu Tsai 	/*
6821469619dSChen-Yu Tsai 	 * This only works if there is only one path from the TCON
6831469619dSChen-Yu Tsai 	 * to any display engine. Otherwise the probe order of the
6841469619dSChen-Yu Tsai 	 * TCONs and display engines is not guaranteed. They may
6851469619dSChen-Yu Tsai 	 * either bind to the wrong one, or worse, bind to the same
6861469619dSChen-Yu Tsai 	 * one if additional checks are not done.
6871469619dSChen-Yu Tsai 	 *
6881469619dSChen-Yu Tsai 	 * Bail out if there are multiple input connections.
6891469619dSChen-Yu Tsai 	 */
690be3fe0f9SChen-Yu Tsai 	if (of_get_available_child_count(port) != 1)
691be3fe0f9SChen-Yu Tsai 		goto out_put_port;
6921469619dSChen-Yu Tsai 
693be3fe0f9SChen-Yu Tsai 	/* Get the first connection without specifying an ID */
694be3fe0f9SChen-Yu Tsai 	ep = of_get_next_available_child(port, NULL);
695be3fe0f9SChen-Yu Tsai 	if (!ep)
696be3fe0f9SChen-Yu Tsai 		goto out_put_port;
697be3fe0f9SChen-Yu Tsai 
698b317fa3bSChen-Yu Tsai 	remote = of_graph_get_remote_port_parent(ep);
699b317fa3bSChen-Yu Tsai 	if (!remote)
700be3fe0f9SChen-Yu Tsai 		goto out_put_ep;
701b317fa3bSChen-Yu Tsai 
70287969338SIcenowy Zheng 	/* does this node match any registered engines? */
703be3fe0f9SChen-Yu Tsai 	list_for_each_entry(engine, &drv->engine_list, list)
704be3fe0f9SChen-Yu Tsai 		if (remote == engine->node)
705be3fe0f9SChen-Yu Tsai 			goto out_put_remote;
706b317fa3bSChen-Yu Tsai 
707b317fa3bSChen-Yu Tsai 	/* keep looking through upstream ports */
708e8d5bbf7SChen-Yu Tsai 	engine = sun4i_tcon_find_engine_traverse(drv, remote);
709b317fa3bSChen-Yu Tsai 
710be3fe0f9SChen-Yu Tsai out_put_remote:
711be3fe0f9SChen-Yu Tsai 	of_node_put(remote);
712be3fe0f9SChen-Yu Tsai out_put_ep:
713be3fe0f9SChen-Yu Tsai 	of_node_put(ep);
714be3fe0f9SChen-Yu Tsai out_put_port:
715be3fe0f9SChen-Yu Tsai 	of_node_put(port);
716be3fe0f9SChen-Yu Tsai 
717be3fe0f9SChen-Yu Tsai 	return engine;
718b317fa3bSChen-Yu Tsai }
719b317fa3bSChen-Yu Tsai 
720e8d5bbf7SChen-Yu Tsai /*
721e8d5bbf7SChen-Yu Tsai  * The device tree binding says that the remote endpoint ID of any
722e8d5bbf7SChen-Yu Tsai  * connection between components, up to and including the TCON, of
723e8d5bbf7SChen-Yu Tsai  * the display pipeline should be equal to the actual ID of the local
724e8d5bbf7SChen-Yu Tsai  * component. Thus we can look at any one of the input connections of
725e8d5bbf7SChen-Yu Tsai  * the TCONs, and use that connection's remote endpoint ID as our own.
726e8d5bbf7SChen-Yu Tsai  *
727e8d5bbf7SChen-Yu Tsai  * Since the user of this function already finds the input port,
728e8d5bbf7SChen-Yu Tsai  * the port is passed in directly without further checks.
729e8d5bbf7SChen-Yu Tsai  */
730e8d5bbf7SChen-Yu Tsai static int sun4i_tcon_of_get_id_from_port(struct device_node *port)
731e8d5bbf7SChen-Yu Tsai {
732e8d5bbf7SChen-Yu Tsai 	struct device_node *ep;
733e8d5bbf7SChen-Yu Tsai 	int ret = -EINVAL;
734e8d5bbf7SChen-Yu Tsai 
735e8d5bbf7SChen-Yu Tsai 	/* try finding an upstream endpoint */
736e8d5bbf7SChen-Yu Tsai 	for_each_available_child_of_node(port, ep) {
737e8d5bbf7SChen-Yu Tsai 		struct device_node *remote;
738e8d5bbf7SChen-Yu Tsai 		u32 reg;
739e8d5bbf7SChen-Yu Tsai 
740e8d5bbf7SChen-Yu Tsai 		remote = of_graph_get_remote_endpoint(ep);
741e8d5bbf7SChen-Yu Tsai 		if (!remote)
742e8d5bbf7SChen-Yu Tsai 			continue;
743e8d5bbf7SChen-Yu Tsai 
744e8d5bbf7SChen-Yu Tsai 		ret = of_property_read_u32(remote, "reg", &reg);
745e8d5bbf7SChen-Yu Tsai 		if (ret)
746e8d5bbf7SChen-Yu Tsai 			continue;
747e8d5bbf7SChen-Yu Tsai 
748e8d5bbf7SChen-Yu Tsai 		ret = reg;
749e8d5bbf7SChen-Yu Tsai 	}
750e8d5bbf7SChen-Yu Tsai 
751e8d5bbf7SChen-Yu Tsai 	return ret;
752e8d5bbf7SChen-Yu Tsai }
753e8d5bbf7SChen-Yu Tsai 
754e8d5bbf7SChen-Yu Tsai /*
755e8d5bbf7SChen-Yu Tsai  * Once we know the TCON's id, we can look through the list of
756e8d5bbf7SChen-Yu Tsai  * engines to find a matching one. We assume all engines have
757e8d5bbf7SChen-Yu Tsai  * been probed and added to the list.
758e8d5bbf7SChen-Yu Tsai  */
759e8d5bbf7SChen-Yu Tsai static struct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv,
760e8d5bbf7SChen-Yu Tsai 							int id)
761e8d5bbf7SChen-Yu Tsai {
762e8d5bbf7SChen-Yu Tsai 	struct sunxi_engine *engine;
763e8d5bbf7SChen-Yu Tsai 
764e8d5bbf7SChen-Yu Tsai 	list_for_each_entry(engine, &drv->engine_list, list)
765e8d5bbf7SChen-Yu Tsai 		if (engine->id == id)
766e8d5bbf7SChen-Yu Tsai 			return engine;
767e8d5bbf7SChen-Yu Tsai 
768e8d5bbf7SChen-Yu Tsai 	return ERR_PTR(-EINVAL);
769e8d5bbf7SChen-Yu Tsai }
770e8d5bbf7SChen-Yu Tsai 
771e8d5bbf7SChen-Yu Tsai /*
772e8d5bbf7SChen-Yu Tsai  * On SoCs with the old display pipeline design (Display Engine 1.0),
773e8d5bbf7SChen-Yu Tsai  * we assumed the TCON was always tied to just one backend. However
774e8d5bbf7SChen-Yu Tsai  * this proved not to be the case. On the A31, the TCON can select
775e8d5bbf7SChen-Yu Tsai  * either backend as its source. On the A20 (and likely on the A10),
776e8d5bbf7SChen-Yu Tsai  * the backend can choose which TCON to output to.
777e8d5bbf7SChen-Yu Tsai  *
778e8d5bbf7SChen-Yu Tsai  * The device tree binding says that the remote endpoint ID of any
779e8d5bbf7SChen-Yu Tsai  * connection between components, up to and including the TCON, of
780e8d5bbf7SChen-Yu Tsai  * the display pipeline should be equal to the actual ID of the local
781e8d5bbf7SChen-Yu Tsai  * component. Thus we should be able to look at any one of the input
782e8d5bbf7SChen-Yu Tsai  * connections of the TCONs, and use that connection's remote endpoint
783e8d5bbf7SChen-Yu Tsai  * ID as our own.
784e8d5bbf7SChen-Yu Tsai  *
785e8d5bbf7SChen-Yu Tsai  * However  the connections between the backend and TCON were assumed
786e8d5bbf7SChen-Yu Tsai  * to be always singular, and their endpoit IDs were all incorrectly
787e8d5bbf7SChen-Yu Tsai  * set to 0. This means for these old device trees, we cannot just look
788e8d5bbf7SChen-Yu Tsai  * up the remote endpoint ID of a TCON input endpoint. TCON1 would be
789e8d5bbf7SChen-Yu Tsai  * incorrectly identified as TCON0.
790e8d5bbf7SChen-Yu Tsai  *
791e8d5bbf7SChen-Yu Tsai  * This function first checks if the TCON node has 2 input endpoints.
792e8d5bbf7SChen-Yu Tsai  * If so, then the device tree is a corrected version, and it will use
793e8d5bbf7SChen-Yu Tsai  * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above
794e8d5bbf7SChen-Yu Tsai  * to fetch the ID and engine directly. If not, then it is likely an
795e8d5bbf7SChen-Yu Tsai  * old device trees, where the endpoint IDs were incorrect, but did not
796e8d5bbf7SChen-Yu Tsai  * have endpoint connections between the backend and TCON across
797e8d5bbf7SChen-Yu Tsai  * different display pipelines. It will fall back to the old method of
798e8d5bbf7SChen-Yu Tsai  * traversing the  of_graph to try and find a matching engine by device
799e8d5bbf7SChen-Yu Tsai  * node.
800e8d5bbf7SChen-Yu Tsai  *
801e8d5bbf7SChen-Yu Tsai  * In the case of single display pipeline device trees, either method
802e8d5bbf7SChen-Yu Tsai  * works.
803e8d5bbf7SChen-Yu Tsai  */
804e8d5bbf7SChen-Yu Tsai static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
805e8d5bbf7SChen-Yu Tsai 						   struct device_node *node)
806e8d5bbf7SChen-Yu Tsai {
807e8d5bbf7SChen-Yu Tsai 	struct device_node *port;
808e8d5bbf7SChen-Yu Tsai 	struct sunxi_engine *engine;
809e8d5bbf7SChen-Yu Tsai 
810e8d5bbf7SChen-Yu Tsai 	port = of_graph_get_port_by_id(node, 0);
811e8d5bbf7SChen-Yu Tsai 	if (!port)
812e8d5bbf7SChen-Yu Tsai 		return ERR_PTR(-EINVAL);
813e8d5bbf7SChen-Yu Tsai 
814e8d5bbf7SChen-Yu Tsai 	/*
815e8d5bbf7SChen-Yu Tsai 	 * Is this a corrected device tree with cross pipeline
816e8d5bbf7SChen-Yu Tsai 	 * connections between the backend and TCON?
817e8d5bbf7SChen-Yu Tsai 	 */
818e8d5bbf7SChen-Yu Tsai 	if (of_get_child_count(port) > 1) {
819e8d5bbf7SChen-Yu Tsai 		/* Get our ID directly from an upstream endpoint */
820e8d5bbf7SChen-Yu Tsai 		int id = sun4i_tcon_of_get_id_from_port(port);
821e8d5bbf7SChen-Yu Tsai 
822e8d5bbf7SChen-Yu Tsai 		/* Get our engine by matching our ID */
823e8d5bbf7SChen-Yu Tsai 		engine = sun4i_tcon_get_engine_by_id(drv, id);
824e8d5bbf7SChen-Yu Tsai 
825e8d5bbf7SChen-Yu Tsai 		of_node_put(port);
826e8d5bbf7SChen-Yu Tsai 		return engine;
827e8d5bbf7SChen-Yu Tsai 	}
828e8d5bbf7SChen-Yu Tsai 
829e8d5bbf7SChen-Yu Tsai 	/* Fallback to old method by traversing input endpoints */
830e8d5bbf7SChen-Yu Tsai 	of_node_put(port);
831e8d5bbf7SChen-Yu Tsai 	return sun4i_tcon_find_engine_traverse(drv, node);
832e8d5bbf7SChen-Yu Tsai }
833e8d5bbf7SChen-Yu Tsai 
8349026e0d1SMaxime Ripard static int sun4i_tcon_bind(struct device *dev, struct device *master,
8359026e0d1SMaxime Ripard 			   void *data)
8369026e0d1SMaxime Ripard {
8379026e0d1SMaxime Ripard 	struct drm_device *drm = data;
8389026e0d1SMaxime Ripard 	struct sun4i_drv *drv = drm->dev_private;
83987969338SIcenowy Zheng 	struct sunxi_engine *engine;
840a0c1214eSMaxime Ripard 	struct device_node *remote;
8419026e0d1SMaxime Ripard 	struct sun4i_tcon *tcon;
842a0c1214eSMaxime Ripard 	bool has_lvds_rst, has_lvds_alt, can_lvds;
8439026e0d1SMaxime Ripard 	int ret;
8449026e0d1SMaxime Ripard 
84587969338SIcenowy Zheng 	engine = sun4i_tcon_find_engine(drv, dev->of_node);
84687969338SIcenowy Zheng 	if (IS_ERR(engine)) {
84787969338SIcenowy Zheng 		dev_err(dev, "Couldn't find matching engine\n");
84880a58240SChen-Yu Tsai 		return -EPROBE_DEFER;
849b317fa3bSChen-Yu Tsai 	}
85080a58240SChen-Yu Tsai 
8519026e0d1SMaxime Ripard 	tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
8529026e0d1SMaxime Ripard 	if (!tcon)
8539026e0d1SMaxime Ripard 		return -ENOMEM;
8549026e0d1SMaxime Ripard 	dev_set_drvdata(dev, tcon);
8559026e0d1SMaxime Ripard 	tcon->drm = drm;
856ae558110SMaxime Ripard 	tcon->dev = dev;
85787969338SIcenowy Zheng 	tcon->id = engine->id;
85891ea2f29SChen-Yu Tsai 	tcon->quirks = of_device_get_match_data(dev);
8599026e0d1SMaxime Ripard 
8609026e0d1SMaxime Ripard 	tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
8619026e0d1SMaxime Ripard 	if (IS_ERR(tcon->lcd_rst)) {
8629026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't get our reset line\n");
8639026e0d1SMaxime Ripard 		return PTR_ERR(tcon->lcd_rst);
8649026e0d1SMaxime Ripard 	}
8659026e0d1SMaxime Ripard 
8669026e0d1SMaxime Ripard 	/* Make sure our TCON is reset */
867d57294c1SChen-Yu Tsai 	ret = reset_control_reset(tcon->lcd_rst);
8689026e0d1SMaxime Ripard 	if (ret) {
8699026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't deassert our reset line\n");
8709026e0d1SMaxime Ripard 		return ret;
8719026e0d1SMaxime Ripard 	}
8729026e0d1SMaxime Ripard 
873a0c1214eSMaxime Ripard 	/*
874a0c1214eSMaxime Ripard 	 * This can only be made optional since we've had DT nodes
875a0c1214eSMaxime Ripard 	 * without the LVDS reset properties.
876a0c1214eSMaxime Ripard 	 *
877a0c1214eSMaxime Ripard 	 * If the property is missing, just disable LVDS, and print a
878a0c1214eSMaxime Ripard 	 * warning.
879a0c1214eSMaxime Ripard 	 */
880a0c1214eSMaxime Ripard 	tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds");
881a0c1214eSMaxime Ripard 	if (IS_ERR(tcon->lvds_rst)) {
882a0c1214eSMaxime Ripard 		dev_err(dev, "Couldn't get our reset line\n");
883a0c1214eSMaxime Ripard 		return PTR_ERR(tcon->lvds_rst);
884a0c1214eSMaxime Ripard 	} else if (tcon->lvds_rst) {
885a0c1214eSMaxime Ripard 		has_lvds_rst = true;
886a0c1214eSMaxime Ripard 		reset_control_reset(tcon->lvds_rst);
887a0c1214eSMaxime Ripard 	} else {
888a0c1214eSMaxime Ripard 		has_lvds_rst = false;
889a0c1214eSMaxime Ripard 	}
890a0c1214eSMaxime Ripard 
891a0c1214eSMaxime Ripard 	/*
892a0c1214eSMaxime Ripard 	 * This can only be made optional since we've had DT nodes
893a0c1214eSMaxime Ripard 	 * without the LVDS reset properties.
894a0c1214eSMaxime Ripard 	 *
895a0c1214eSMaxime Ripard 	 * If the property is missing, just disable LVDS, and print a
896a0c1214eSMaxime Ripard 	 * warning.
897a0c1214eSMaxime Ripard 	 */
898a0c1214eSMaxime Ripard 	if (tcon->quirks->has_lvds_alt) {
899a0c1214eSMaxime Ripard 		tcon->lvds_pll = devm_clk_get(dev, "lvds-alt");
900a0c1214eSMaxime Ripard 		if (IS_ERR(tcon->lvds_pll)) {
901a0c1214eSMaxime Ripard 			if (PTR_ERR(tcon->lvds_pll) == -ENOENT) {
902a0c1214eSMaxime Ripard 				has_lvds_alt = false;
903a0c1214eSMaxime Ripard 			} else {
904a0c1214eSMaxime Ripard 				dev_err(dev, "Couldn't get the LVDS PLL\n");
905*86a3ae58SDan Carpenter 				return PTR_ERR(tcon->lvds_pll);
906a0c1214eSMaxime Ripard 			}
907a0c1214eSMaxime Ripard 		} else {
908a0c1214eSMaxime Ripard 			has_lvds_alt = true;
909a0c1214eSMaxime Ripard 		}
910a0c1214eSMaxime Ripard 	}
911a0c1214eSMaxime Ripard 
912a0c1214eSMaxime Ripard 	if (!has_lvds_rst || (tcon->quirks->has_lvds_alt && !has_lvds_alt)) {
913a0c1214eSMaxime Ripard 		dev_warn(dev,
914a0c1214eSMaxime Ripard 			 "Missing LVDS properties, Please upgrade your DT\n");
915a0c1214eSMaxime Ripard 		dev_warn(dev, "LVDS output disabled\n");
916a0c1214eSMaxime Ripard 		can_lvds = false;
917a0c1214eSMaxime Ripard 	} else {
918a0c1214eSMaxime Ripard 		can_lvds = true;
919a0c1214eSMaxime Ripard 	}
920a0c1214eSMaxime Ripard 
9219026e0d1SMaxime Ripard 	ret = sun4i_tcon_init_clocks(dev, tcon);
9229026e0d1SMaxime Ripard 	if (ret) {
9239026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't init our TCON clocks\n");
9249026e0d1SMaxime Ripard 		goto err_assert_reset;
9259026e0d1SMaxime Ripard 	}
9269026e0d1SMaxime Ripard 
9274c7f16d1SChen-Yu Tsai 	ret = sun4i_tcon_init_regmap(dev, tcon);
9289026e0d1SMaxime Ripard 	if (ret) {
9294c7f16d1SChen-Yu Tsai 		dev_err(dev, "Couldn't init our TCON regmap\n");
9309026e0d1SMaxime Ripard 		goto err_free_clocks;
9319026e0d1SMaxime Ripard 	}
9329026e0d1SMaxime Ripard 
9334c7f16d1SChen-Yu Tsai 	ret = sun4i_dclk_create(dev, tcon);
9344c7f16d1SChen-Yu Tsai 	if (ret) {
9354c7f16d1SChen-Yu Tsai 		dev_err(dev, "Couldn't create our TCON dot clock\n");
9364c7f16d1SChen-Yu Tsai 		goto err_free_clocks;
9374c7f16d1SChen-Yu Tsai 	}
9384c7f16d1SChen-Yu Tsai 
9399026e0d1SMaxime Ripard 	ret = sun4i_tcon_init_irq(dev, tcon);
9409026e0d1SMaxime Ripard 	if (ret) {
9419026e0d1SMaxime Ripard 		dev_err(dev, "Couldn't init our TCON interrupts\n");
9424c7f16d1SChen-Yu Tsai 		goto err_free_dotclock;
9439026e0d1SMaxime Ripard 	}
9449026e0d1SMaxime Ripard 
94587969338SIcenowy Zheng 	tcon->crtc = sun4i_crtc_init(drm, engine, tcon);
94646cce6daSChen-Yu Tsai 	if (IS_ERR(tcon->crtc)) {
94746cce6daSChen-Yu Tsai 		dev_err(dev, "Couldn't create our CRTC\n");
94846cce6daSChen-Yu Tsai 		ret = PTR_ERR(tcon->crtc);
94946cce6daSChen-Yu Tsai 		goto err_free_clocks;
95046cce6daSChen-Yu Tsai 	}
95146cce6daSChen-Yu Tsai 
952a0c1214eSMaxime Ripard 	/*
953a0c1214eSMaxime Ripard 	 * If we have an LVDS panel connected to the TCON, we should
954a0c1214eSMaxime Ripard 	 * just probe the LVDS connector. Otherwise, just probe RGB as
955a0c1214eSMaxime Ripard 	 * we used to.
956a0c1214eSMaxime Ripard 	 */
957a0c1214eSMaxime Ripard 	remote = of_graph_get_remote_node(dev->of_node, 1, 0);
958a0c1214eSMaxime Ripard 	if (of_device_is_compatible(remote, "panel-lvds"))
959a0c1214eSMaxime Ripard 		if (can_lvds)
960a0c1214eSMaxime Ripard 			ret = sun4i_lvds_init(drm, tcon);
961a0c1214eSMaxime Ripard 		else
962a0c1214eSMaxime Ripard 			ret = -EINVAL;
963a0c1214eSMaxime Ripard 	else
964b9c8506cSChen-Yu Tsai 		ret = sun4i_rgb_init(drm, tcon);
965a0c1214eSMaxime Ripard 	of_node_put(remote);
966a0c1214eSMaxime Ripard 
96713fef095SChen-Yu Tsai 	if (ret < 0)
96813fef095SChen-Yu Tsai 		goto err_free_clocks;
96913fef095SChen-Yu Tsai 
97027e18de7SChen-Yu Tsai 	if (tcon->quirks->needs_de_be_mux) {
97127e18de7SChen-Yu Tsai 		/*
97227e18de7SChen-Yu Tsai 		 * We assume there is no dynamic muxing of backends
97327e18de7SChen-Yu Tsai 		 * and TCONs, so we select the backend with same ID.
97427e18de7SChen-Yu Tsai 		 *
97527e18de7SChen-Yu Tsai 		 * While dynamic selection might be interesting, since
97627e18de7SChen-Yu Tsai 		 * the CRTC is tied to the TCON, while the layers are
97727e18de7SChen-Yu Tsai 		 * tied to the backends, this means, we will need to
97827e18de7SChen-Yu Tsai 		 * switch between groups of layers. There might not be
97927e18de7SChen-Yu Tsai 		 * a way to represent this constraint in DRM.
98027e18de7SChen-Yu Tsai 		 */
98127e18de7SChen-Yu Tsai 		regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
98227e18de7SChen-Yu Tsai 				   SUN4I_TCON0_CTL_SRC_SEL_MASK,
98327e18de7SChen-Yu Tsai 				   tcon->id);
98427e18de7SChen-Yu Tsai 		regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
98527e18de7SChen-Yu Tsai 				   SUN4I_TCON1_CTL_SRC_SEL_MASK,
98627e18de7SChen-Yu Tsai 				   tcon->id);
98727e18de7SChen-Yu Tsai 	}
98827e18de7SChen-Yu Tsai 
98980a58240SChen-Yu Tsai 	list_add_tail(&tcon->list, &drv->tcon_list);
99080a58240SChen-Yu Tsai 
99113fef095SChen-Yu Tsai 	return 0;
9929026e0d1SMaxime Ripard 
9934c7f16d1SChen-Yu Tsai err_free_dotclock:
9944c7f16d1SChen-Yu Tsai 	sun4i_dclk_free(tcon);
9959026e0d1SMaxime Ripard err_free_clocks:
9969026e0d1SMaxime Ripard 	sun4i_tcon_free_clocks(tcon);
9979026e0d1SMaxime Ripard err_assert_reset:
9989026e0d1SMaxime Ripard 	reset_control_assert(tcon->lcd_rst);
9999026e0d1SMaxime Ripard 	return ret;
10009026e0d1SMaxime Ripard }
10019026e0d1SMaxime Ripard 
10029026e0d1SMaxime Ripard static void sun4i_tcon_unbind(struct device *dev, struct device *master,
10039026e0d1SMaxime Ripard 			      void *data)
10049026e0d1SMaxime Ripard {
10059026e0d1SMaxime Ripard 	struct sun4i_tcon *tcon = dev_get_drvdata(dev);
10069026e0d1SMaxime Ripard 
100780a58240SChen-Yu Tsai 	list_del(&tcon->list);
10084c7f16d1SChen-Yu Tsai 	sun4i_dclk_free(tcon);
10099026e0d1SMaxime Ripard 	sun4i_tcon_free_clocks(tcon);
10109026e0d1SMaxime Ripard }
10119026e0d1SMaxime Ripard 
1012dfeb693dSJulia Lawall static const struct component_ops sun4i_tcon_ops = {
10139026e0d1SMaxime Ripard 	.bind	= sun4i_tcon_bind,
10149026e0d1SMaxime Ripard 	.unbind	= sun4i_tcon_unbind,
10159026e0d1SMaxime Ripard };
10169026e0d1SMaxime Ripard 
10179026e0d1SMaxime Ripard static int sun4i_tcon_probe(struct platform_device *pdev)
10189026e0d1SMaxime Ripard {
101929e57fabSMaxime Ripard 	struct device_node *node = pdev->dev.of_node;
1020894f5a9fSMaxime Ripard 	struct drm_bridge *bridge;
102129e57fabSMaxime Ripard 	struct drm_panel *panel;
1022ebc94461SRob Herring 	int ret;
102329e57fabSMaxime Ripard 
1024ebc94461SRob Herring 	ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge);
1025ebc94461SRob Herring 	if (ret == -EPROBE_DEFER)
1026ebc94461SRob Herring 		return ret;
102729e57fabSMaxime Ripard 
10289026e0d1SMaxime Ripard 	return component_add(&pdev->dev, &sun4i_tcon_ops);
10299026e0d1SMaxime Ripard }
10309026e0d1SMaxime Ripard 
10319026e0d1SMaxime Ripard static int sun4i_tcon_remove(struct platform_device *pdev)
10329026e0d1SMaxime Ripard {
10339026e0d1SMaxime Ripard 	component_del(&pdev->dev, &sun4i_tcon_ops);
10349026e0d1SMaxime Ripard 
10359026e0d1SMaxime Ripard 	return 0;
10369026e0d1SMaxime Ripard }
10379026e0d1SMaxime Ripard 
1038ad537fb2SChen-Yu Tsai /* platform specific TCON muxing callbacks */
10394bb206bfSJonathan Liu static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon,
10404bb206bfSJonathan Liu 				  const struct drm_encoder *encoder)
10414bb206bfSJonathan Liu {
10424bb206bfSJonathan Liu 	struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
10434bb206bfSJonathan Liu 	u32 shift;
10444bb206bfSJonathan Liu 
10454bb206bfSJonathan Liu 	if (!tcon0)
10464bb206bfSJonathan Liu 		return -EINVAL;
10474bb206bfSJonathan Liu 
10484bb206bfSJonathan Liu 	switch (encoder->encoder_type) {
10494bb206bfSJonathan Liu 	case DRM_MODE_ENCODER_TMDS:
10504bb206bfSJonathan Liu 		/* HDMI */
10514bb206bfSJonathan Liu 		shift = 8;
10524bb206bfSJonathan Liu 		break;
10534bb206bfSJonathan Liu 	default:
10544bb206bfSJonathan Liu 		return -EINVAL;
10554bb206bfSJonathan Liu 	}
10564bb206bfSJonathan Liu 
10574bb206bfSJonathan Liu 	regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
10584bb206bfSJonathan Liu 			   0x3 << shift, tcon->id << shift);
10594bb206bfSJonathan Liu 
10604bb206bfSJonathan Liu 	return 0;
10614bb206bfSJonathan Liu }
10624bb206bfSJonathan Liu 
1063ad537fb2SChen-Yu Tsai static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon,
1064abcb8766SMaxime Ripard 				  const struct drm_encoder *encoder)
1065ad537fb2SChen-Yu Tsai {
1066ad537fb2SChen-Yu Tsai 	u32 val;
1067ad537fb2SChen-Yu Tsai 
1068ad537fb2SChen-Yu Tsai 	if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1069ad537fb2SChen-Yu Tsai 		val = 1;
1070ad537fb2SChen-Yu Tsai 	else
1071ad537fb2SChen-Yu Tsai 		val = 0;
1072ad537fb2SChen-Yu Tsai 
1073ad537fb2SChen-Yu Tsai 	/*
1074ad537fb2SChen-Yu Tsai 	 * FIXME: Undocumented bits
1075ad537fb2SChen-Yu Tsai 	 */
1076ad537fb2SChen-Yu Tsai 	return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
1077ad537fb2SChen-Yu Tsai }
1078ad537fb2SChen-Yu Tsai 
107967e32645SChen-Yu Tsai static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,
1080abcb8766SMaxime Ripard 			      const struct drm_encoder *encoder)
108167e32645SChen-Yu Tsai {
108267e32645SChen-Yu Tsai 	struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
108367e32645SChen-Yu Tsai 	u32 shift;
108467e32645SChen-Yu Tsai 
108567e32645SChen-Yu Tsai 	if (!tcon0)
108667e32645SChen-Yu Tsai 		return -EINVAL;
108767e32645SChen-Yu Tsai 
108867e32645SChen-Yu Tsai 	switch (encoder->encoder_type) {
108967e32645SChen-Yu Tsai 	case DRM_MODE_ENCODER_TMDS:
109067e32645SChen-Yu Tsai 		/* HDMI */
109167e32645SChen-Yu Tsai 		shift = 8;
109267e32645SChen-Yu Tsai 		break;
109367e32645SChen-Yu Tsai 	default:
109467e32645SChen-Yu Tsai 		/* TODO A31 has MIPI DSI but A31s does not */
109567e32645SChen-Yu Tsai 		return -EINVAL;
109667e32645SChen-Yu Tsai 	}
109767e32645SChen-Yu Tsai 
109867e32645SChen-Yu Tsai 	regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
109967e32645SChen-Yu Tsai 			   0x3 << shift, tcon->id << shift);
110067e32645SChen-Yu Tsai 
110167e32645SChen-Yu Tsai 	return 0;
110267e32645SChen-Yu Tsai }
110367e32645SChen-Yu Tsai 
11044bb206bfSJonathan Liu static const struct sun4i_tcon_quirks sun4i_a10_quirks = {
11054bb206bfSJonathan Liu 	.has_channel_1		= true,
11064bb206bfSJonathan Liu 	.set_mux		= sun4i_a10_tcon_set_mux,
11074bb206bfSJonathan Liu };
11084bb206bfSJonathan Liu 
110991ea2f29SChen-Yu Tsai static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
111091ea2f29SChen-Yu Tsai 	.has_channel_1		= true,
1111ad537fb2SChen-Yu Tsai 	.set_mux		= sun5i_a13_tcon_set_mux,
111291ea2f29SChen-Yu Tsai };
111391ea2f29SChen-Yu Tsai 
111493a5ec14SChen-Yu Tsai static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
111593a5ec14SChen-Yu Tsai 	.has_channel_1		= true,
1116a0c1214eSMaxime Ripard 	.has_lvds_alt		= true,
111727e18de7SChen-Yu Tsai 	.needs_de_be_mux	= true,
111867e32645SChen-Yu Tsai 	.set_mux		= sun6i_tcon_set_mux,
111993a5ec14SChen-Yu Tsai };
112093a5ec14SChen-Yu Tsai 
112193a5ec14SChen-Yu Tsai static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
112293a5ec14SChen-Yu Tsai 	.has_channel_1		= true,
112327e18de7SChen-Yu Tsai 	.needs_de_be_mux	= true,
112493a5ec14SChen-Yu Tsai };
112593a5ec14SChen-Yu Tsai 
1126aaddb6d2SJonathan Liu static const struct sun4i_tcon_quirks sun7i_a20_quirks = {
1127aaddb6d2SJonathan Liu 	.has_channel_1		= true,
1128aaddb6d2SJonathan Liu 	/* Same display pipeline structure as A10 */
1129aaddb6d2SJonathan Liu 	.set_mux		= sun4i_a10_tcon_set_mux,
1130aaddb6d2SJonathan Liu };
1131aaddb6d2SJonathan Liu 
113291ea2f29SChen-Yu Tsai static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
1133a0c1214eSMaxime Ripard 	.has_lvds_alt		= true,
113491ea2f29SChen-Yu Tsai };
113591ea2f29SChen-Yu Tsai 
11362f0d7bb1SMaxime Ripard static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
11372f0d7bb1SMaxime Ripard 	/* nothing is supported */
11382f0d7bb1SMaxime Ripard };
11392f0d7bb1SMaxime Ripard 
11401a0edb3fSIcenowy Zheng static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
11411a0edb3fSIcenowy Zheng 	/* nothing is supported */
11421a0edb3fSIcenowy Zheng };
11431a0edb3fSIcenowy Zheng 
1144ff71c2cfSChen-Yu Tsai /* sun4i_drv uses this list to check if a device node is a TCON */
1145ff71c2cfSChen-Yu Tsai const struct of_device_id sun4i_tcon_of_table[] = {
11464bb206bfSJonathan Liu 	{ .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
114791ea2f29SChen-Yu Tsai 	{ .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
114893a5ec14SChen-Yu Tsai 	{ .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
114993a5ec14SChen-Yu Tsai 	{ .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1150aaddb6d2SJonathan Liu 	{ .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
115191ea2f29SChen-Yu Tsai 	{ .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
11522f0d7bb1SMaxime Ripard 	{ .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
11531a0edb3fSIcenowy Zheng 	{ .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
11549026e0d1SMaxime Ripard 	{ }
11559026e0d1SMaxime Ripard };
11569026e0d1SMaxime Ripard MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
1157ff71c2cfSChen-Yu Tsai EXPORT_SYMBOL(sun4i_tcon_of_table);
11589026e0d1SMaxime Ripard 
11599026e0d1SMaxime Ripard static struct platform_driver sun4i_tcon_platform_driver = {
11609026e0d1SMaxime Ripard 	.probe		= sun4i_tcon_probe,
11619026e0d1SMaxime Ripard 	.remove		= sun4i_tcon_remove,
11629026e0d1SMaxime Ripard 	.driver		= {
11639026e0d1SMaxime Ripard 		.name		= "sun4i-tcon",
11649026e0d1SMaxime Ripard 		.of_match_table	= sun4i_tcon_of_table,
11659026e0d1SMaxime Ripard 	},
11669026e0d1SMaxime Ripard };
11679026e0d1SMaxime Ripard module_platform_driver(sun4i_tcon_platform_driver);
11689026e0d1SMaxime Ripard 
11699026e0d1SMaxime Ripard MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
11709026e0d1SMaxime Ripard MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver");
11719026e0d1SMaxime Ripard MODULE_LICENSE("GPL");
1172