1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 /* RS600 / Radeon X1250/X1270 integrated GPU 29 * 30 * This file gather function specific to RS600 which is the IGP of 31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740 32 * is the X1250/X1270 supporting AMD CPU). The display engine are 33 * the avivo one, bios is an atombios, 3D block are the one of the 34 * R4XX family. The GART is different from the RS400 one and is very 35 * close to the one of the R600 family (R600 likely being an evolution 36 * of the RS600 GART block). 37 */ 38 #include "drmP.h" 39 #include "radeon.h" 40 #include "atom.h" 41 #include "rs600d.h" 42 43 #include "rs600_reg_safe.h" 44 45 void rs600_gpu_init(struct radeon_device *rdev); 46 int rs600_mc_wait_for_idle(struct radeon_device *rdev); 47 48 /* 49 * GART. 50 */ 51 void rs600_gart_tlb_flush(struct radeon_device *rdev) 52 { 53 uint32_t tmp; 54 55 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 56 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 57 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 58 59 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 60 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1); 61 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 62 63 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 64 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 65 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 66 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 67 } 68 69 int rs600_gart_init(struct radeon_device *rdev) 70 { 71 int r; 72 73 if (rdev->gart.table.vram.robj) { 74 WARN(1, "RS600 GART already initialized.\n"); 75 return 0; 76 } 77 /* Initialize common gart structure */ 78 r = radeon_gart_init(rdev); 79 if (r) { 80 return r; 81 } 82 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 83 return radeon_gart_table_vram_alloc(rdev); 84 } 85 86 int rs600_gart_enable(struct radeon_device *rdev) 87 { 88 u32 tmp; 89 int r, i; 90 91 if (rdev->gart.table.vram.robj == NULL) { 92 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 93 return -EINVAL; 94 } 95 r = radeon_gart_table_vram_pin(rdev); 96 if (r) 97 return r; 98 /* Enable bus master */ 99 tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; 100 WREG32(R_00004C_BUS_CNTL, tmp); 101 /* FIXME: setup default page */ 102 WREG32_MC(R_000100_MC_PT0_CNTL, 103 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | 104 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); 105 for (i = 0; i < 19; i++) { 106 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, 107 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | 108 S_00016C_SYSTEM_ACCESS_MODE_MASK( 109 V_00016C_SYSTEM_ACCESS_MODE_IN_SYS) | 110 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( 111 V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE) | 112 S_00016C_EFFECTIVE_L1_CACHE_SIZE(1) | 113 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | 114 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(1)); 115 } 116 117 /* System context map to GART space */ 118 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_start); 119 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.gtt_end); 120 121 /* enable first context */ 122 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); 123 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); 124 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, 125 S_000102_ENABLE_PAGE_TABLE(1) | 126 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); 127 /* disable all other contexts */ 128 for (i = 1; i < 8; i++) { 129 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); 130 } 131 132 /* setup the page table */ 133 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 134 rdev->gart.table_addr); 135 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); 136 137 /* enable page tables */ 138 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 139 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); 140 tmp = RREG32_MC(R_000009_MC_CNTL1); 141 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); 142 rs600_gart_tlb_flush(rdev); 143 rdev->gart.ready = true; 144 return 0; 145 } 146 147 void rs600_gart_disable(struct radeon_device *rdev) 148 { 149 u32 tmp; 150 int r; 151 152 /* FIXME: disable out of gart access */ 153 WREG32_MC(R_000100_MC_PT0_CNTL, 0); 154 tmp = RREG32_MC(R_000009_MC_CNTL1); 155 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); 156 if (rdev->gart.table.vram.robj) { 157 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); 158 if (r == 0) { 159 radeon_bo_kunmap(rdev->gart.table.vram.robj); 160 radeon_bo_unpin(rdev->gart.table.vram.robj); 161 radeon_bo_unreserve(rdev->gart.table.vram.robj); 162 } 163 } 164 } 165 166 void rs600_gart_fini(struct radeon_device *rdev) 167 { 168 rs600_gart_disable(rdev); 169 radeon_gart_table_vram_free(rdev); 170 radeon_gart_fini(rdev); 171 } 172 173 #define R600_PTE_VALID (1 << 0) 174 #define R600_PTE_SYSTEM (1 << 1) 175 #define R600_PTE_SNOOPED (1 << 2) 176 #define R600_PTE_READABLE (1 << 5) 177 #define R600_PTE_WRITEABLE (1 << 6) 178 179 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 180 { 181 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; 182 183 if (i < 0 || i > rdev->gart.num_gpu_pages) { 184 return -EINVAL; 185 } 186 addr = addr & 0xFFFFFFFFFFFFF000ULL; 187 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 188 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 189 writeq(addr, ((void __iomem *)ptr) + (i * 8)); 190 return 0; 191 } 192 193 int rs600_irq_set(struct radeon_device *rdev) 194 { 195 uint32_t tmp = 0; 196 uint32_t mode_int = 0; 197 198 if (rdev->irq.sw_int) { 199 tmp |= S_000040_SW_INT_EN(1); 200 } 201 if (rdev->irq.crtc_vblank_int[0]) { 202 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); 203 } 204 if (rdev->irq.crtc_vblank_int[1]) { 205 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); 206 } 207 WREG32(R_000040_GEN_INT_CNTL, tmp); 208 WREG32(R_006540_DxMODE_INT_MASK, mode_int); 209 return 0; 210 } 211 212 static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int) 213 { 214 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); 215 uint32_t irq_mask = ~C_000044_SW_INT; 216 217 if (G_000044_DISPLAY_INT_STAT(irqs)) { 218 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); 219 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) { 220 WREG32(R_006534_D1MODE_VBLANK_STATUS, 221 S_006534_D1MODE_VBLANK_ACK(1)); 222 } 223 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) { 224 WREG32(R_006D34_D2MODE_VBLANK_STATUS, 225 S_006D34_D2MODE_VBLANK_ACK(1)); 226 } 227 } else { 228 *r500_disp_int = 0; 229 } 230 231 if (irqs) { 232 WREG32(R_000044_GEN_INT_STATUS, irqs); 233 } 234 return irqs & irq_mask; 235 } 236 237 void rs600_irq_disable(struct radeon_device *rdev) 238 { 239 u32 tmp; 240 241 WREG32(R_000040_GEN_INT_CNTL, 0); 242 WREG32(R_006540_DxMODE_INT_MASK, 0); 243 /* Wait and acknowledge irq */ 244 mdelay(1); 245 rs600_irq_ack(rdev, &tmp); 246 } 247 248 int rs600_irq_process(struct radeon_device *rdev) 249 { 250 uint32_t status, msi_rearm; 251 uint32_t r500_disp_int; 252 253 status = rs600_irq_ack(rdev, &r500_disp_int); 254 if (!status && !r500_disp_int) { 255 return IRQ_NONE; 256 } 257 while (status || r500_disp_int) { 258 /* SW interrupt */ 259 if (G_000040_SW_INT_EN(status)) 260 radeon_fence_process(rdev); 261 /* Vertical blank interrupts */ 262 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) 263 drm_handle_vblank(rdev->ddev, 0); 264 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) 265 drm_handle_vblank(rdev->ddev, 1); 266 status = rs600_irq_ack(rdev, &r500_disp_int); 267 } 268 if (rdev->msi_enabled) { 269 switch (rdev->family) { 270 case CHIP_RS600: 271 case CHIP_RS690: 272 case CHIP_RS740: 273 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; 274 WREG32(RADEON_BUS_CNTL, msi_rearm); 275 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); 276 break; 277 default: 278 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; 279 WREG32(RADEON_MSI_REARM_EN, msi_rearm); 280 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); 281 break; 282 } 283 } 284 return IRQ_HANDLED; 285 } 286 287 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) 288 { 289 if (crtc == 0) 290 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); 291 else 292 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); 293 } 294 295 int rs600_mc_wait_for_idle(struct radeon_device *rdev) 296 { 297 unsigned i; 298 299 for (i = 0; i < rdev->usec_timeout; i++) { 300 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) 301 return 0; 302 udelay(1); 303 } 304 return -1; 305 } 306 307 void rs600_gpu_init(struct radeon_device *rdev) 308 { 309 /* FIXME: HDP same place on rs600 ? */ 310 r100_hdp_reset(rdev); 311 /* FIXME: is this correct ? */ 312 r420_pipes_init(rdev); 313 /* Wait for mc idle */ 314 if (rs600_mc_wait_for_idle(rdev)) 315 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 316 } 317 318 void rs600_vram_info(struct radeon_device *rdev) 319 { 320 /* FIXME: to do or is these values sane ? */ 321 rdev->mc.vram_is_ddr = true; 322 rdev->mc.vram_width = 128; 323 } 324 325 void rs600_bandwidth_update(struct radeon_device *rdev) 326 { 327 /* FIXME: implement, should this be like rs690 ? */ 328 } 329 330 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) 331 { 332 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 333 S_000070_MC_IND_CITF_ARB0(1)); 334 return RREG32(R_000074_MC_IND_DATA); 335 } 336 337 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 338 { 339 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 340 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); 341 WREG32(R_000074_MC_IND_DATA, v); 342 } 343 344 void rs600_debugfs(struct radeon_device *rdev) 345 { 346 if (r100_debugfs_rbbm_init(rdev)) 347 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 348 } 349 350 void rs600_set_safe_registers(struct radeon_device *rdev) 351 { 352 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; 353 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); 354 } 355 356 static void rs600_mc_program(struct radeon_device *rdev) 357 { 358 struct rv515_mc_save save; 359 360 /* Stops all mc clients */ 361 rv515_mc_stop(rdev, &save); 362 363 /* Wait for mc idle */ 364 if (rs600_mc_wait_for_idle(rdev)) 365 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 366 367 /* FIXME: What does AGP means for such chipset ? */ 368 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); 369 WREG32_MC(R_000006_AGP_BASE, 0); 370 WREG32_MC(R_000007_AGP_BASE_2, 0); 371 /* Program MC */ 372 WREG32_MC(R_000004_MC_FB_LOCATION, 373 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 374 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 375 WREG32(R_000134_HDP_FB_LOCATION, 376 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 377 378 rv515_mc_resume(rdev, &save); 379 } 380 381 static int rs600_startup(struct radeon_device *rdev) 382 { 383 int r; 384 385 rs600_mc_program(rdev); 386 /* Resume clock */ 387 rv515_clock_startup(rdev); 388 /* Initialize GPU configuration (# pipes, ...) */ 389 rs600_gpu_init(rdev); 390 /* Initialize GART (initialize after TTM so we can allocate 391 * memory through TTM but finalize after TTM) */ 392 r = rs600_gart_enable(rdev); 393 if (r) 394 return r; 395 /* Enable IRQ */ 396 rs600_irq_set(rdev); 397 /* 1M ring buffer */ 398 r = r100_cp_init(rdev, 1024 * 1024); 399 if (r) { 400 dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 401 return r; 402 } 403 r = r100_wb_init(rdev); 404 if (r) 405 dev_err(rdev->dev, "failled initializing WB (%d).\n", r); 406 r = r100_ib_init(rdev); 407 if (r) { 408 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 409 return r; 410 } 411 return 0; 412 } 413 414 int rs600_resume(struct radeon_device *rdev) 415 { 416 /* Make sur GART are not working */ 417 rs600_gart_disable(rdev); 418 /* Resume clock before doing reset */ 419 rv515_clock_startup(rdev); 420 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 421 if (radeon_gpu_reset(rdev)) { 422 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 423 RREG32(R_000E40_RBBM_STATUS), 424 RREG32(R_0007C0_CP_STAT)); 425 } 426 /* post */ 427 atom_asic_init(rdev->mode_info.atom_context); 428 /* Resume clock after posting */ 429 rv515_clock_startup(rdev); 430 return rs600_startup(rdev); 431 } 432 433 int rs600_suspend(struct radeon_device *rdev) 434 { 435 r100_cp_disable(rdev); 436 r100_wb_disable(rdev); 437 rs600_irq_disable(rdev); 438 rs600_gart_disable(rdev); 439 return 0; 440 } 441 442 void rs600_fini(struct radeon_device *rdev) 443 { 444 rs600_suspend(rdev); 445 r100_cp_fini(rdev); 446 r100_wb_fini(rdev); 447 r100_ib_fini(rdev); 448 radeon_gem_fini(rdev); 449 rs600_gart_fini(rdev); 450 radeon_irq_kms_fini(rdev); 451 radeon_fence_driver_fini(rdev); 452 radeon_bo_fini(rdev); 453 radeon_atombios_fini(rdev); 454 kfree(rdev->bios); 455 rdev->bios = NULL; 456 } 457 458 int rs600_init(struct radeon_device *rdev) 459 { 460 int r; 461 462 /* Disable VGA */ 463 rv515_vga_render_disable(rdev); 464 /* Initialize scratch registers */ 465 radeon_scratch_init(rdev); 466 /* Initialize surface registers */ 467 radeon_surface_init(rdev); 468 /* BIOS */ 469 if (!radeon_get_bios(rdev)) { 470 if (ASIC_IS_AVIVO(rdev)) 471 return -EINVAL; 472 } 473 if (rdev->is_atom_bios) { 474 r = radeon_atombios_init(rdev); 475 if (r) 476 return r; 477 } else { 478 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); 479 return -EINVAL; 480 } 481 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 482 if (radeon_gpu_reset(rdev)) { 483 dev_warn(rdev->dev, 484 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 485 RREG32(R_000E40_RBBM_STATUS), 486 RREG32(R_0007C0_CP_STAT)); 487 } 488 /* check if cards are posted or not */ 489 if (radeon_boot_test_post_card(rdev) == false) 490 return -EINVAL; 491 492 /* Initialize clocks */ 493 radeon_get_clock_info(rdev->ddev); 494 /* Initialize power management */ 495 radeon_pm_init(rdev); 496 /* Get vram informations */ 497 rs600_vram_info(rdev); 498 /* Initialize memory controller (also test AGP) */ 499 r = r420_mc_init(rdev); 500 if (r) 501 return r; 502 rs600_debugfs(rdev); 503 /* Fence driver */ 504 r = radeon_fence_driver_init(rdev); 505 if (r) 506 return r; 507 r = radeon_irq_kms_init(rdev); 508 if (r) 509 return r; 510 /* Memory manager */ 511 r = radeon_bo_init(rdev); 512 if (r) 513 return r; 514 r = rs600_gart_init(rdev); 515 if (r) 516 return r; 517 rs600_set_safe_registers(rdev); 518 rdev->accel_working = true; 519 r = rs600_startup(rdev); 520 if (r) { 521 /* Somethings want wront with the accel init stop accel */ 522 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 523 rs600_suspend(rdev); 524 r100_cp_fini(rdev); 525 r100_wb_fini(rdev); 526 r100_ib_fini(rdev); 527 rs600_gart_fini(rdev); 528 radeon_irq_kms_fini(rdev); 529 rdev->accel_working = false; 530 } 531 return 0; 532 } 533