1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 /* RS600 / Radeon X1250/X1270 integrated GPU 29 * 30 * This file gather function specific to RS600 which is the IGP of 31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740 32 * is the X1250/X1270 supporting AMD CPU). The display engine are 33 * the avivo one, bios is an atombios, 3D block are the one of the 34 * R4XX family. The GART is different from the RS400 one and is very 35 * close to the one of the R600 family (R600 likely being an evolution 36 * of the RS600 GART block). 37 */ 38 #include "drmP.h" 39 #include "radeon.h" 40 #include "atom.h" 41 #include "rs600d.h" 42 43 #include "rs600_reg_safe.h" 44 45 void rs600_gpu_init(struct radeon_device *rdev); 46 int rs600_mc_wait_for_idle(struct radeon_device *rdev); 47 48 /* hpd for digital panel detect/disconnect */ 49 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 50 { 51 u32 tmp; 52 bool connected = false; 53 54 switch (hpd) { 55 case RADEON_HPD_1: 56 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); 57 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) 58 connected = true; 59 break; 60 case RADEON_HPD_2: 61 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); 62 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) 63 connected = true; 64 break; 65 default: 66 break; 67 } 68 return connected; 69 } 70 71 void rs600_hpd_set_polarity(struct radeon_device *rdev, 72 enum radeon_hpd_id hpd) 73 { 74 u32 tmp; 75 bool connected = rs600_hpd_sense(rdev, hpd); 76 77 switch (hpd) { 78 case RADEON_HPD_1: 79 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 80 if (connected) 81 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 82 else 83 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 84 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 85 break; 86 case RADEON_HPD_2: 87 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 88 if (connected) 89 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 90 else 91 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 92 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 93 break; 94 default: 95 break; 96 } 97 } 98 99 void rs600_hpd_init(struct radeon_device *rdev) 100 { 101 struct drm_device *dev = rdev->ddev; 102 struct drm_connector *connector; 103 104 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 105 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 106 switch (radeon_connector->hpd.hpd) { 107 case RADEON_HPD_1: 108 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 109 S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); 110 rdev->irq.hpd[0] = true; 111 break; 112 case RADEON_HPD_2: 113 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 114 S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); 115 rdev->irq.hpd[1] = true; 116 break; 117 default: 118 break; 119 } 120 } 121 if (rdev->irq.installed) 122 rs600_irq_set(rdev); 123 } 124 125 void rs600_hpd_fini(struct radeon_device *rdev) 126 { 127 struct drm_device *dev = rdev->ddev; 128 struct drm_connector *connector; 129 130 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 131 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 132 switch (radeon_connector->hpd.hpd) { 133 case RADEON_HPD_1: 134 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 135 S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); 136 rdev->irq.hpd[0] = false; 137 break; 138 case RADEON_HPD_2: 139 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 140 S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); 141 rdev->irq.hpd[1] = false; 142 break; 143 default: 144 break; 145 } 146 } 147 } 148 149 /* 150 * GART. 151 */ 152 void rs600_gart_tlb_flush(struct radeon_device *rdev) 153 { 154 uint32_t tmp; 155 156 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 157 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 158 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 159 160 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 161 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1); 162 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 163 164 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 165 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 166 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 167 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 168 } 169 170 int rs600_gart_init(struct radeon_device *rdev) 171 { 172 int r; 173 174 if (rdev->gart.table.vram.robj) { 175 WARN(1, "RS600 GART already initialized.\n"); 176 return 0; 177 } 178 /* Initialize common gart structure */ 179 r = radeon_gart_init(rdev); 180 if (r) { 181 return r; 182 } 183 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 184 return radeon_gart_table_vram_alloc(rdev); 185 } 186 187 int rs600_gart_enable(struct radeon_device *rdev) 188 { 189 u32 tmp; 190 int r, i; 191 192 if (rdev->gart.table.vram.robj == NULL) { 193 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 194 return -EINVAL; 195 } 196 r = radeon_gart_table_vram_pin(rdev); 197 if (r) 198 return r; 199 radeon_gart_restore(rdev); 200 /* Enable bus master */ 201 tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; 202 WREG32(R_00004C_BUS_CNTL, tmp); 203 /* FIXME: setup default page */ 204 WREG32_MC(R_000100_MC_PT0_CNTL, 205 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | 206 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); 207 208 for (i = 0; i < 19; i++) { 209 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, 210 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | 211 S_00016C_SYSTEM_ACCESS_MODE_MASK( 212 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | 213 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( 214 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | 215 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | 216 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | 217 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); 218 } 219 /* enable first context */ 220 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, 221 S_000102_ENABLE_PAGE_TABLE(1) | 222 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); 223 224 /* disable all other contexts */ 225 for (i = 1; i < 8; i++) 226 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); 227 228 /* setup the page table */ 229 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 230 rdev->gart.table_addr); 231 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); 232 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); 233 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); 234 235 /* System context maps to VRAM space */ 236 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); 237 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); 238 239 /* enable page tables */ 240 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 241 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); 242 tmp = RREG32_MC(R_000009_MC_CNTL1); 243 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); 244 rs600_gart_tlb_flush(rdev); 245 rdev->gart.ready = true; 246 return 0; 247 } 248 249 void rs600_gart_disable(struct radeon_device *rdev) 250 { 251 u32 tmp; 252 int r; 253 254 /* FIXME: disable out of gart access */ 255 WREG32_MC(R_000100_MC_PT0_CNTL, 0); 256 tmp = RREG32_MC(R_000009_MC_CNTL1); 257 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); 258 if (rdev->gart.table.vram.robj) { 259 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); 260 if (r == 0) { 261 radeon_bo_kunmap(rdev->gart.table.vram.robj); 262 radeon_bo_unpin(rdev->gart.table.vram.robj); 263 radeon_bo_unreserve(rdev->gart.table.vram.robj); 264 } 265 } 266 } 267 268 void rs600_gart_fini(struct radeon_device *rdev) 269 { 270 rs600_gart_disable(rdev); 271 radeon_gart_table_vram_free(rdev); 272 radeon_gart_fini(rdev); 273 } 274 275 #define R600_PTE_VALID (1 << 0) 276 #define R600_PTE_SYSTEM (1 << 1) 277 #define R600_PTE_SNOOPED (1 << 2) 278 #define R600_PTE_READABLE (1 << 5) 279 #define R600_PTE_WRITEABLE (1 << 6) 280 281 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 282 { 283 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; 284 285 if (i < 0 || i > rdev->gart.num_gpu_pages) { 286 return -EINVAL; 287 } 288 addr = addr & 0xFFFFFFFFFFFFF000ULL; 289 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 290 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 291 writeq(addr, ((void __iomem *)ptr) + (i * 8)); 292 return 0; 293 } 294 295 int rs600_irq_set(struct radeon_device *rdev) 296 { 297 uint32_t tmp = 0; 298 uint32_t mode_int = 0; 299 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & 300 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 301 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & 302 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 303 304 if (!rdev->irq.installed) { 305 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); 306 WREG32(R_000040_GEN_INT_CNTL, 0); 307 return -EINVAL; 308 } 309 if (rdev->irq.sw_int) { 310 tmp |= S_000040_SW_INT_EN(1); 311 } 312 if (rdev->irq.crtc_vblank_int[0]) { 313 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); 314 } 315 if (rdev->irq.crtc_vblank_int[1]) { 316 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); 317 } 318 if (rdev->irq.hpd[0]) { 319 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 320 } 321 if (rdev->irq.hpd[1]) { 322 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 323 } 324 WREG32(R_000040_GEN_INT_CNTL, tmp); 325 WREG32(R_006540_DxMODE_INT_MASK, mode_int); 326 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 327 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 328 return 0; 329 } 330 331 static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int) 332 { 333 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); 334 uint32_t irq_mask = ~C_000044_SW_INT; 335 u32 tmp; 336 337 if (G_000044_DISPLAY_INT_STAT(irqs)) { 338 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); 339 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) { 340 WREG32(R_006534_D1MODE_VBLANK_STATUS, 341 S_006534_D1MODE_VBLANK_ACK(1)); 342 } 343 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) { 344 WREG32(R_006D34_D2MODE_VBLANK_STATUS, 345 S_006D34_D2MODE_VBLANK_ACK(1)); 346 } 347 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) { 348 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 349 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); 350 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 351 } 352 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) { 353 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 354 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); 355 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 356 } 357 } else { 358 *r500_disp_int = 0; 359 } 360 361 if (irqs) { 362 WREG32(R_000044_GEN_INT_STATUS, irqs); 363 } 364 return irqs & irq_mask; 365 } 366 367 void rs600_irq_disable(struct radeon_device *rdev) 368 { 369 u32 tmp; 370 371 WREG32(R_000040_GEN_INT_CNTL, 0); 372 WREG32(R_006540_DxMODE_INT_MASK, 0); 373 /* Wait and acknowledge irq */ 374 mdelay(1); 375 rs600_irq_ack(rdev, &tmp); 376 } 377 378 int rs600_irq_process(struct radeon_device *rdev) 379 { 380 uint32_t status, msi_rearm; 381 uint32_t r500_disp_int; 382 bool queue_hotplug = false; 383 384 status = rs600_irq_ack(rdev, &r500_disp_int); 385 if (!status && !r500_disp_int) { 386 return IRQ_NONE; 387 } 388 while (status || r500_disp_int) { 389 /* SW interrupt */ 390 if (G_000044_SW_INT(status)) 391 radeon_fence_process(rdev); 392 /* Vertical blank interrupts */ 393 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) { 394 drm_handle_vblank(rdev->ddev, 0); 395 rdev->pm.vblank_sync = true; 396 wake_up(&rdev->irq.vblank_queue); 397 } 398 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) { 399 drm_handle_vblank(rdev->ddev, 1); 400 rdev->pm.vblank_sync = true; 401 wake_up(&rdev->irq.vblank_queue); 402 } 403 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) { 404 queue_hotplug = true; 405 DRM_DEBUG("HPD1\n"); 406 } 407 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) { 408 queue_hotplug = true; 409 DRM_DEBUG("HPD2\n"); 410 } 411 status = rs600_irq_ack(rdev, &r500_disp_int); 412 } 413 if (queue_hotplug) 414 queue_work(rdev->wq, &rdev->hotplug_work); 415 if (rdev->msi_enabled) { 416 switch (rdev->family) { 417 case CHIP_RS600: 418 case CHIP_RS690: 419 case CHIP_RS740: 420 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; 421 WREG32(RADEON_BUS_CNTL, msi_rearm); 422 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); 423 break; 424 default: 425 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; 426 WREG32(RADEON_MSI_REARM_EN, msi_rearm); 427 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); 428 break; 429 } 430 } 431 return IRQ_HANDLED; 432 } 433 434 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) 435 { 436 if (crtc == 0) 437 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); 438 else 439 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); 440 } 441 442 int rs600_mc_wait_for_idle(struct radeon_device *rdev) 443 { 444 unsigned i; 445 446 for (i = 0; i < rdev->usec_timeout; i++) { 447 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) 448 return 0; 449 udelay(1); 450 } 451 return -1; 452 } 453 454 void rs600_gpu_init(struct radeon_device *rdev) 455 { 456 r100_hdp_reset(rdev); 457 r420_pipes_init(rdev); 458 /* Wait for mc idle */ 459 if (rs600_mc_wait_for_idle(rdev)) 460 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 461 } 462 463 void rs600_mc_init(struct radeon_device *rdev) 464 { 465 u64 base; 466 467 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 468 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 469 rdev->mc.vram_is_ddr = true; 470 rdev->mc.vram_width = 128; 471 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 472 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 473 rdev->mc.visible_vram_size = rdev->mc.aper_size; 474 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 475 base = RREG32_MC(R_000004_MC_FB_LOCATION); 476 base = G_000004_MC_FB_START(base) << 16; 477 radeon_vram_location(rdev, &rdev->mc, base); 478 radeon_gtt_location(rdev, &rdev->mc); 479 } 480 481 void rs600_bandwidth_update(struct radeon_device *rdev) 482 { 483 /* FIXME: implement, should this be like rs690 ? */ 484 } 485 486 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) 487 { 488 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 489 S_000070_MC_IND_CITF_ARB0(1)); 490 return RREG32(R_000074_MC_IND_DATA); 491 } 492 493 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 494 { 495 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 496 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); 497 WREG32(R_000074_MC_IND_DATA, v); 498 } 499 500 void rs600_debugfs(struct radeon_device *rdev) 501 { 502 if (r100_debugfs_rbbm_init(rdev)) 503 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 504 } 505 506 void rs600_set_safe_registers(struct radeon_device *rdev) 507 { 508 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; 509 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); 510 } 511 512 static void rs600_mc_program(struct radeon_device *rdev) 513 { 514 struct rv515_mc_save save; 515 516 /* Stops all mc clients */ 517 rv515_mc_stop(rdev, &save); 518 519 /* Wait for mc idle */ 520 if (rs600_mc_wait_for_idle(rdev)) 521 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 522 523 /* FIXME: What does AGP means for such chipset ? */ 524 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); 525 WREG32_MC(R_000006_AGP_BASE, 0); 526 WREG32_MC(R_000007_AGP_BASE_2, 0); 527 /* Program MC */ 528 WREG32_MC(R_000004_MC_FB_LOCATION, 529 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 530 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 531 WREG32(R_000134_HDP_FB_LOCATION, 532 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 533 534 rv515_mc_resume(rdev, &save); 535 } 536 537 static int rs600_startup(struct radeon_device *rdev) 538 { 539 int r; 540 541 rs600_mc_program(rdev); 542 /* Resume clock */ 543 rv515_clock_startup(rdev); 544 /* Initialize GPU configuration (# pipes, ...) */ 545 rs600_gpu_init(rdev); 546 /* Initialize GART (initialize after TTM so we can allocate 547 * memory through TTM but finalize after TTM) */ 548 r = rs600_gart_enable(rdev); 549 if (r) 550 return r; 551 /* Enable IRQ */ 552 rs600_irq_set(rdev); 553 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 554 /* 1M ring buffer */ 555 r = r100_cp_init(rdev, 1024 * 1024); 556 if (r) { 557 dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 558 return r; 559 } 560 r = r100_wb_init(rdev); 561 if (r) 562 dev_err(rdev->dev, "failled initializing WB (%d).\n", r); 563 r = r100_ib_init(rdev); 564 if (r) { 565 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 566 return r; 567 } 568 return 0; 569 } 570 571 int rs600_resume(struct radeon_device *rdev) 572 { 573 /* Make sur GART are not working */ 574 rs600_gart_disable(rdev); 575 /* Resume clock before doing reset */ 576 rv515_clock_startup(rdev); 577 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 578 if (radeon_gpu_reset(rdev)) { 579 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 580 RREG32(R_000E40_RBBM_STATUS), 581 RREG32(R_0007C0_CP_STAT)); 582 } 583 /* post */ 584 atom_asic_init(rdev->mode_info.atom_context); 585 /* Resume clock after posting */ 586 rv515_clock_startup(rdev); 587 /* Initialize surface registers */ 588 radeon_surface_init(rdev); 589 return rs600_startup(rdev); 590 } 591 592 int rs600_suspend(struct radeon_device *rdev) 593 { 594 r100_cp_disable(rdev); 595 r100_wb_disable(rdev); 596 rs600_irq_disable(rdev); 597 rs600_gart_disable(rdev); 598 return 0; 599 } 600 601 void rs600_fini(struct radeon_device *rdev) 602 { 603 r100_cp_fini(rdev); 604 r100_wb_fini(rdev); 605 r100_ib_fini(rdev); 606 radeon_gem_fini(rdev); 607 rs600_gart_fini(rdev); 608 radeon_irq_kms_fini(rdev); 609 radeon_fence_driver_fini(rdev); 610 radeon_bo_fini(rdev); 611 radeon_atombios_fini(rdev); 612 kfree(rdev->bios); 613 rdev->bios = NULL; 614 } 615 616 int rs600_init(struct radeon_device *rdev) 617 { 618 int r; 619 620 /* Disable VGA */ 621 rv515_vga_render_disable(rdev); 622 /* Initialize scratch registers */ 623 radeon_scratch_init(rdev); 624 /* Initialize surface registers */ 625 radeon_surface_init(rdev); 626 /* BIOS */ 627 if (!radeon_get_bios(rdev)) { 628 if (ASIC_IS_AVIVO(rdev)) 629 return -EINVAL; 630 } 631 if (rdev->is_atom_bios) { 632 r = radeon_atombios_init(rdev); 633 if (r) 634 return r; 635 } else { 636 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); 637 return -EINVAL; 638 } 639 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 640 if (radeon_gpu_reset(rdev)) { 641 dev_warn(rdev->dev, 642 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 643 RREG32(R_000E40_RBBM_STATUS), 644 RREG32(R_0007C0_CP_STAT)); 645 } 646 /* check if cards are posted or not */ 647 if (radeon_boot_test_post_card(rdev) == false) 648 return -EINVAL; 649 650 /* Initialize clocks */ 651 radeon_get_clock_info(rdev->ddev); 652 /* Initialize power management */ 653 radeon_pm_init(rdev); 654 /* initialize memory controller */ 655 rs600_mc_init(rdev); 656 rs600_debugfs(rdev); 657 /* Fence driver */ 658 r = radeon_fence_driver_init(rdev); 659 if (r) 660 return r; 661 r = radeon_irq_kms_init(rdev); 662 if (r) 663 return r; 664 /* Memory manager */ 665 r = radeon_bo_init(rdev); 666 if (r) 667 return r; 668 r = rs600_gart_init(rdev); 669 if (r) 670 return r; 671 rs600_set_safe_registers(rdev); 672 rdev->accel_working = true; 673 r = rs600_startup(rdev); 674 if (r) { 675 /* Somethings want wront with the accel init stop accel */ 676 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 677 r100_cp_fini(rdev); 678 r100_wb_fini(rdev); 679 r100_ib_fini(rdev); 680 rs600_gart_fini(rdev); 681 radeon_irq_kms_fini(rdev); 682 rdev->accel_working = false; 683 } 684 return 0; 685 } 686