1ecc0b326SMichel Dänzer /* 2ecc0b326SMichel Dänzer * Copyright 2009 VMware, Inc. 3ecc0b326SMichel Dänzer * 4ecc0b326SMichel Dänzer * Permission is hereby granted, free of charge, to any person obtaining a 5ecc0b326SMichel Dänzer * copy of this software and associated documentation files (the "Software"), 6ecc0b326SMichel Dänzer * to deal in the Software without restriction, including without limitation 7ecc0b326SMichel Dänzer * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8ecc0b326SMichel Dänzer * and/or sell copies of the Software, and to permit persons to whom the 9ecc0b326SMichel Dänzer * Software is furnished to do so, subject to the following conditions: 10ecc0b326SMichel Dänzer * 11ecc0b326SMichel Dänzer * The above copyright notice and this permission notice shall be included in 12ecc0b326SMichel Dänzer * all copies or substantial portions of the Software. 13ecc0b326SMichel Dänzer * 14ecc0b326SMichel Dänzer * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15ecc0b326SMichel Dänzer * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16ecc0b326SMichel Dänzer * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17ecc0b326SMichel Dänzer * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18ecc0b326SMichel Dänzer * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19ecc0b326SMichel Dänzer * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20ecc0b326SMichel Dänzer * OTHER DEALINGS IN THE SOFTWARE. 21ecc0b326SMichel Dänzer * 22ecc0b326SMichel Dänzer * Authors: Michel Dänzer 23ecc0b326SMichel Dänzer */ 24ecc0b326SMichel Dänzer #include <drm/drmP.h> 25ecc0b326SMichel Dänzer #include <drm/radeon_drm.h> 26ecc0b326SMichel Dänzer #include "radeon_reg.h" 27ecc0b326SMichel Dänzer #include "radeon.h" 28ecc0b326SMichel Dänzer 29ecc0b326SMichel Dänzer 30ecc0b326SMichel Dänzer /* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */ 31ecc0b326SMichel Dänzer void radeon_test_moves(struct radeon_device *rdev) 32ecc0b326SMichel Dänzer { 334c788679SJerome Glisse struct radeon_bo *vram_obj = NULL; 344c788679SJerome Glisse struct radeon_bo **gtt_obj = NULL; 35ecc0b326SMichel Dänzer struct radeon_fence *fence = NULL; 36ecc0b326SMichel Dänzer uint64_t gtt_addr, vram_addr; 37ecc0b326SMichel Dänzer unsigned i, n, size; 38ecc0b326SMichel Dänzer int r; 39ecc0b326SMichel Dänzer 40ecc0b326SMichel Dänzer size = 1024 * 1024; 41ecc0b326SMichel Dänzer 42ecc0b326SMichel Dänzer /* Number of tests = 4324cae9e7SMichel Dänzer * (Total GTT - IB pool - writeback page - ring buffers) / test size 44ecc0b326SMichel Dänzer */ 45*7b1f2485SChristian König n = rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024; 46*7b1f2485SChristian König n -= rdev->cp.ring_size; 4724cae9e7SMichel Dänzer if (rdev->wb.wb_obj) 4824cae9e7SMichel Dänzer n -= RADEON_GPU_PAGE_SIZE; 4924cae9e7SMichel Dänzer if (rdev->ih.ring_obj) 5024cae9e7SMichel Dänzer n -= rdev->ih.ring_size; 5124cae9e7SMichel Dänzer n /= size; 52ecc0b326SMichel Dänzer 53ecc0b326SMichel Dänzer gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL); 54ecc0b326SMichel Dänzer if (!gtt_obj) { 55ecc0b326SMichel Dänzer DRM_ERROR("Failed to allocate %d pointers\n", n); 56ecc0b326SMichel Dänzer r = 1; 57ecc0b326SMichel Dänzer goto out_cleanup; 58ecc0b326SMichel Dänzer } 59ecc0b326SMichel Dänzer 60441921d5SDaniel Vetter r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 614c788679SJerome Glisse &vram_obj); 62ecc0b326SMichel Dänzer if (r) { 63ecc0b326SMichel Dänzer DRM_ERROR("Failed to create VRAM object\n"); 64ecc0b326SMichel Dänzer goto out_cleanup; 65ecc0b326SMichel Dänzer } 664c788679SJerome Glisse r = radeon_bo_reserve(vram_obj, false); 674c788679SJerome Glisse if (unlikely(r != 0)) 684c788679SJerome Glisse goto out_cleanup; 694c788679SJerome Glisse r = radeon_bo_pin(vram_obj, RADEON_GEM_DOMAIN_VRAM, &vram_addr); 70ecc0b326SMichel Dänzer if (r) { 71ecc0b326SMichel Dänzer DRM_ERROR("Failed to pin VRAM object\n"); 72ecc0b326SMichel Dänzer goto out_cleanup; 73ecc0b326SMichel Dänzer } 74ecc0b326SMichel Dänzer for (i = 0; i < n; i++) { 75ecc0b326SMichel Dänzer void *gtt_map, *vram_map; 76ecc0b326SMichel Dänzer void **gtt_start, **gtt_end; 77ecc0b326SMichel Dänzer void **vram_start, **vram_end; 78ecc0b326SMichel Dänzer 79441921d5SDaniel Vetter r = radeon_bo_create(rdev, size, PAGE_SIZE, true, 804c788679SJerome Glisse RADEON_GEM_DOMAIN_GTT, gtt_obj + i); 81ecc0b326SMichel Dänzer if (r) { 82ecc0b326SMichel Dänzer DRM_ERROR("Failed to create GTT object %d\n", i); 83ecc0b326SMichel Dänzer goto out_cleanup; 84ecc0b326SMichel Dänzer } 85ecc0b326SMichel Dänzer 864c788679SJerome Glisse r = radeon_bo_reserve(gtt_obj[i], false); 874c788679SJerome Glisse if (unlikely(r != 0)) 884c788679SJerome Glisse goto out_cleanup; 894c788679SJerome Glisse r = radeon_bo_pin(gtt_obj[i], RADEON_GEM_DOMAIN_GTT, >t_addr); 90ecc0b326SMichel Dänzer if (r) { 91ecc0b326SMichel Dänzer DRM_ERROR("Failed to pin GTT object %d\n", i); 92ecc0b326SMichel Dänzer goto out_cleanup; 93ecc0b326SMichel Dänzer } 94ecc0b326SMichel Dänzer 954c788679SJerome Glisse r = radeon_bo_kmap(gtt_obj[i], >t_map); 96ecc0b326SMichel Dänzer if (r) { 97ecc0b326SMichel Dänzer DRM_ERROR("Failed to map GTT object %d\n", i); 98ecc0b326SMichel Dänzer goto out_cleanup; 99ecc0b326SMichel Dänzer } 100ecc0b326SMichel Dänzer 101ecc0b326SMichel Dänzer for (gtt_start = gtt_map, gtt_end = gtt_map + size; 102ecc0b326SMichel Dänzer gtt_start < gtt_end; 103ecc0b326SMichel Dänzer gtt_start++) 104ecc0b326SMichel Dänzer *gtt_start = gtt_start; 105ecc0b326SMichel Dänzer 1064c788679SJerome Glisse radeon_bo_kunmap(gtt_obj[i]); 107ecc0b326SMichel Dänzer 1087465280cSAlex Deucher r = radeon_fence_create(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); 109ecc0b326SMichel Dänzer if (r) { 110ecc0b326SMichel Dänzer DRM_ERROR("Failed to create GTT->VRAM fence %d\n", i); 111ecc0b326SMichel Dänzer goto out_cleanup; 112ecc0b326SMichel Dänzer } 113ecc0b326SMichel Dänzer 114a77f1718SMatt Turner r = radeon_copy(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, fence); 115ecc0b326SMichel Dänzer if (r) { 116ecc0b326SMichel Dänzer DRM_ERROR("Failed GTT->VRAM copy %d\n", i); 117ecc0b326SMichel Dänzer goto out_cleanup; 118ecc0b326SMichel Dänzer } 119ecc0b326SMichel Dänzer 120ecc0b326SMichel Dänzer r = radeon_fence_wait(fence, false); 121ecc0b326SMichel Dänzer if (r) { 122ecc0b326SMichel Dänzer DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i); 123ecc0b326SMichel Dänzer goto out_cleanup; 124ecc0b326SMichel Dänzer } 125ecc0b326SMichel Dänzer 126ecc0b326SMichel Dänzer radeon_fence_unref(&fence); 127ecc0b326SMichel Dänzer 1284c788679SJerome Glisse r = radeon_bo_kmap(vram_obj, &vram_map); 129ecc0b326SMichel Dänzer if (r) { 130ecc0b326SMichel Dänzer DRM_ERROR("Failed to map VRAM object after copy %d\n", i); 131ecc0b326SMichel Dänzer goto out_cleanup; 132ecc0b326SMichel Dänzer } 133ecc0b326SMichel Dänzer 134ecc0b326SMichel Dänzer for (gtt_start = gtt_map, gtt_end = gtt_map + size, 135ecc0b326SMichel Dänzer vram_start = vram_map, vram_end = vram_map + size; 136ecc0b326SMichel Dänzer vram_start < vram_end; 137ecc0b326SMichel Dänzer gtt_start++, vram_start++) { 138ecc0b326SMichel Dänzer if (*vram_start != gtt_start) { 139ecc0b326SMichel Dänzer DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, " 1404fb1a35cSMichel Dänzer "expected 0x%p (GTT/VRAM offset " 1414fb1a35cSMichel Dänzer "0x%16llx/0x%16llx)\n", 1424fb1a35cSMichel Dänzer i, *vram_start, gtt_start, 1434fb1a35cSMichel Dänzer (unsigned long long) 1444fb1a35cSMichel Dänzer (gtt_addr - rdev->mc.gtt_start + 1454fb1a35cSMichel Dänzer (void*)gtt_start - gtt_map), 1464fb1a35cSMichel Dänzer (unsigned long long) 1474fb1a35cSMichel Dänzer (vram_addr - rdev->mc.vram_start + 1484fb1a35cSMichel Dänzer (void*)gtt_start - gtt_map)); 1494c788679SJerome Glisse radeon_bo_kunmap(vram_obj); 150ecc0b326SMichel Dänzer goto out_cleanup; 151ecc0b326SMichel Dänzer } 152ecc0b326SMichel Dänzer *vram_start = vram_start; 153ecc0b326SMichel Dänzer } 154ecc0b326SMichel Dänzer 1554c788679SJerome Glisse radeon_bo_kunmap(vram_obj); 156ecc0b326SMichel Dänzer 1577465280cSAlex Deucher r = radeon_fence_create(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); 158ecc0b326SMichel Dänzer if (r) { 159ecc0b326SMichel Dänzer DRM_ERROR("Failed to create VRAM->GTT fence %d\n", i); 160ecc0b326SMichel Dänzer goto out_cleanup; 161ecc0b326SMichel Dänzer } 162ecc0b326SMichel Dänzer 163a77f1718SMatt Turner r = radeon_copy(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, fence); 164ecc0b326SMichel Dänzer if (r) { 165ecc0b326SMichel Dänzer DRM_ERROR("Failed VRAM->GTT copy %d\n", i); 166ecc0b326SMichel Dänzer goto out_cleanup; 167ecc0b326SMichel Dänzer } 168ecc0b326SMichel Dänzer 169ecc0b326SMichel Dänzer r = radeon_fence_wait(fence, false); 170ecc0b326SMichel Dänzer if (r) { 171ecc0b326SMichel Dänzer DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i); 172ecc0b326SMichel Dänzer goto out_cleanup; 173ecc0b326SMichel Dänzer } 174ecc0b326SMichel Dänzer 175ecc0b326SMichel Dänzer radeon_fence_unref(&fence); 176ecc0b326SMichel Dänzer 1774c788679SJerome Glisse r = radeon_bo_kmap(gtt_obj[i], >t_map); 178ecc0b326SMichel Dänzer if (r) { 179ecc0b326SMichel Dänzer DRM_ERROR("Failed to map GTT object after copy %d\n", i); 180ecc0b326SMichel Dänzer goto out_cleanup; 181ecc0b326SMichel Dänzer } 182ecc0b326SMichel Dänzer 183ecc0b326SMichel Dänzer for (gtt_start = gtt_map, gtt_end = gtt_map + size, 184ecc0b326SMichel Dänzer vram_start = vram_map, vram_end = vram_map + size; 185ecc0b326SMichel Dänzer gtt_start < gtt_end; 186ecc0b326SMichel Dänzer gtt_start++, vram_start++) { 187ecc0b326SMichel Dänzer if (*gtt_start != vram_start) { 188ecc0b326SMichel Dänzer DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, " 1894fb1a35cSMichel Dänzer "expected 0x%p (VRAM/GTT offset " 1904fb1a35cSMichel Dänzer "0x%16llx/0x%16llx)\n", 1914fb1a35cSMichel Dänzer i, *gtt_start, vram_start, 1924fb1a35cSMichel Dänzer (unsigned long long) 1934fb1a35cSMichel Dänzer (vram_addr - rdev->mc.vram_start + 1944fb1a35cSMichel Dänzer (void*)vram_start - vram_map), 1954fb1a35cSMichel Dänzer (unsigned long long) 1964fb1a35cSMichel Dänzer (gtt_addr - rdev->mc.gtt_start + 1974fb1a35cSMichel Dänzer (void*)vram_start - vram_map)); 1984c788679SJerome Glisse radeon_bo_kunmap(gtt_obj[i]); 199ecc0b326SMichel Dänzer goto out_cleanup; 200ecc0b326SMichel Dänzer } 201ecc0b326SMichel Dänzer } 202ecc0b326SMichel Dänzer 2034c788679SJerome Glisse radeon_bo_kunmap(gtt_obj[i]); 204ecc0b326SMichel Dänzer 205ecc0b326SMichel Dänzer DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n", 206d594e46aSJerome Glisse gtt_addr - rdev->mc.gtt_start); 207ecc0b326SMichel Dänzer } 208ecc0b326SMichel Dänzer 209ecc0b326SMichel Dänzer out_cleanup: 210ecc0b326SMichel Dänzer if (vram_obj) { 2114c788679SJerome Glisse if (radeon_bo_is_reserved(vram_obj)) { 2124c788679SJerome Glisse radeon_bo_unpin(vram_obj); 2134c788679SJerome Glisse radeon_bo_unreserve(vram_obj); 2144c788679SJerome Glisse } 2154c788679SJerome Glisse radeon_bo_unref(&vram_obj); 216ecc0b326SMichel Dänzer } 217ecc0b326SMichel Dänzer if (gtt_obj) { 218ecc0b326SMichel Dänzer for (i = 0; i < n; i++) { 219ecc0b326SMichel Dänzer if (gtt_obj[i]) { 2204c788679SJerome Glisse if (radeon_bo_is_reserved(gtt_obj[i])) { 2214c788679SJerome Glisse radeon_bo_unpin(gtt_obj[i]); 2224c788679SJerome Glisse radeon_bo_unreserve(gtt_obj[i]); 2234c788679SJerome Glisse } 2244c788679SJerome Glisse radeon_bo_unref(>t_obj[i]); 225ecc0b326SMichel Dänzer } 226ecc0b326SMichel Dänzer } 227ecc0b326SMichel Dänzer kfree(gtt_obj); 228ecc0b326SMichel Dänzer } 229ecc0b326SMichel Dänzer if (fence) { 230ecc0b326SMichel Dänzer radeon_fence_unref(&fence); 231ecc0b326SMichel Dänzer } 232ecc0b326SMichel Dänzer if (r) { 233ecc0b326SMichel Dänzer printk(KERN_WARNING "Error while testing BO move.\n"); 234ecc0b326SMichel Dänzer } 235ecc0b326SMichel Dänzer } 236