1ecc0b326SMichel Dänzer /* 2ecc0b326SMichel Dänzer * Copyright 2009 VMware, Inc. 3ecc0b326SMichel Dänzer * 4ecc0b326SMichel Dänzer * Permission is hereby granted, free of charge, to any person obtaining a 5ecc0b326SMichel Dänzer * copy of this software and associated documentation files (the "Software"), 6ecc0b326SMichel Dänzer * to deal in the Software without restriction, including without limitation 7ecc0b326SMichel Dänzer * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8ecc0b326SMichel Dänzer * and/or sell copies of the Software, and to permit persons to whom the 9ecc0b326SMichel Dänzer * Software is furnished to do so, subject to the following conditions: 10ecc0b326SMichel Dänzer * 11ecc0b326SMichel Dänzer * The above copyright notice and this permission notice shall be included in 12ecc0b326SMichel Dänzer * all copies or substantial portions of the Software. 13ecc0b326SMichel Dänzer * 14ecc0b326SMichel Dänzer * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15ecc0b326SMichel Dänzer * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16ecc0b326SMichel Dänzer * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17ecc0b326SMichel Dänzer * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18ecc0b326SMichel Dänzer * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19ecc0b326SMichel Dänzer * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20ecc0b326SMichel Dänzer * OTHER DEALINGS IN THE SOFTWARE. 21ecc0b326SMichel Dänzer * 22ecc0b326SMichel Dänzer * Authors: Michel Dänzer 23ecc0b326SMichel Dänzer */ 24ecc0b326SMichel Dänzer #include <drm/drmP.h> 25ecc0b326SMichel Dänzer #include <drm/radeon_drm.h> 26ecc0b326SMichel Dänzer #include "radeon_reg.h" 27ecc0b326SMichel Dänzer #include "radeon.h" 28ecc0b326SMichel Dänzer 29ecc0b326SMichel Dänzer 30ecc0b326SMichel Dänzer /* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */ 31ecc0b326SMichel Dänzer void radeon_test_moves(struct radeon_device *rdev) 32ecc0b326SMichel Dänzer { 334c788679SJerome Glisse struct radeon_bo *vram_obj = NULL; 344c788679SJerome Glisse struct radeon_bo **gtt_obj = NULL; 35ecc0b326SMichel Dänzer struct radeon_fence *fence = NULL; 36ecc0b326SMichel Dänzer uint64_t gtt_addr, vram_addr; 37ecc0b326SMichel Dänzer unsigned i, n, size; 38ecc0b326SMichel Dänzer int r; 39ecc0b326SMichel Dänzer 40ecc0b326SMichel Dänzer size = 1024 * 1024; 41ecc0b326SMichel Dänzer 42ecc0b326SMichel Dänzer /* Number of tests = 43ecc0b326SMichel Dänzer * (Total GTT - IB pool - writeback page - ring buffer) / test size 44ecc0b326SMichel Dänzer */ 45794f3141SDave Airlie n = ((u32)(rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024 - RADEON_GPU_PAGE_SIZE - 46794f3141SDave Airlie rdev->cp.ring_size)) / size; 47ecc0b326SMichel Dänzer 48ecc0b326SMichel Dänzer gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL); 49ecc0b326SMichel Dänzer if (!gtt_obj) { 50ecc0b326SMichel Dänzer DRM_ERROR("Failed to allocate %d pointers\n", n); 51ecc0b326SMichel Dänzer r = 1; 52ecc0b326SMichel Dänzer goto out_cleanup; 53ecc0b326SMichel Dänzer } 54ecc0b326SMichel Dänzer 55*441921d5SDaniel Vetter r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 564c788679SJerome Glisse &vram_obj); 57ecc0b326SMichel Dänzer if (r) { 58ecc0b326SMichel Dänzer DRM_ERROR("Failed to create VRAM object\n"); 59ecc0b326SMichel Dänzer goto out_cleanup; 60ecc0b326SMichel Dänzer } 614c788679SJerome Glisse r = radeon_bo_reserve(vram_obj, false); 624c788679SJerome Glisse if (unlikely(r != 0)) 634c788679SJerome Glisse goto out_cleanup; 644c788679SJerome Glisse r = radeon_bo_pin(vram_obj, RADEON_GEM_DOMAIN_VRAM, &vram_addr); 65ecc0b326SMichel Dänzer if (r) { 66ecc0b326SMichel Dänzer DRM_ERROR("Failed to pin VRAM object\n"); 67ecc0b326SMichel Dänzer goto out_cleanup; 68ecc0b326SMichel Dänzer } 69ecc0b326SMichel Dänzer for (i = 0; i < n; i++) { 70ecc0b326SMichel Dänzer void *gtt_map, *vram_map; 71ecc0b326SMichel Dänzer void **gtt_start, **gtt_end; 72ecc0b326SMichel Dänzer void **vram_start, **vram_end; 73ecc0b326SMichel Dänzer 74*441921d5SDaniel Vetter r = radeon_bo_create(rdev, size, PAGE_SIZE, true, 754c788679SJerome Glisse RADEON_GEM_DOMAIN_GTT, gtt_obj + i); 76ecc0b326SMichel Dänzer if (r) { 77ecc0b326SMichel Dänzer DRM_ERROR("Failed to create GTT object %d\n", i); 78ecc0b326SMichel Dänzer goto out_cleanup; 79ecc0b326SMichel Dänzer } 80ecc0b326SMichel Dänzer 814c788679SJerome Glisse r = radeon_bo_reserve(gtt_obj[i], false); 824c788679SJerome Glisse if (unlikely(r != 0)) 834c788679SJerome Glisse goto out_cleanup; 844c788679SJerome Glisse r = radeon_bo_pin(gtt_obj[i], RADEON_GEM_DOMAIN_GTT, >t_addr); 85ecc0b326SMichel Dänzer if (r) { 86ecc0b326SMichel Dänzer DRM_ERROR("Failed to pin GTT object %d\n", i); 87ecc0b326SMichel Dänzer goto out_cleanup; 88ecc0b326SMichel Dänzer } 89ecc0b326SMichel Dänzer 904c788679SJerome Glisse r = radeon_bo_kmap(gtt_obj[i], >t_map); 91ecc0b326SMichel Dänzer if (r) { 92ecc0b326SMichel Dänzer DRM_ERROR("Failed to map GTT object %d\n", i); 93ecc0b326SMichel Dänzer goto out_cleanup; 94ecc0b326SMichel Dänzer } 95ecc0b326SMichel Dänzer 96ecc0b326SMichel Dänzer for (gtt_start = gtt_map, gtt_end = gtt_map + size; 97ecc0b326SMichel Dänzer gtt_start < gtt_end; 98ecc0b326SMichel Dänzer gtt_start++) 99ecc0b326SMichel Dänzer *gtt_start = gtt_start; 100ecc0b326SMichel Dänzer 1014c788679SJerome Glisse radeon_bo_kunmap(gtt_obj[i]); 102ecc0b326SMichel Dänzer 103ecc0b326SMichel Dänzer r = radeon_fence_create(rdev, &fence); 104ecc0b326SMichel Dänzer if (r) { 105ecc0b326SMichel Dänzer DRM_ERROR("Failed to create GTT->VRAM fence %d\n", i); 106ecc0b326SMichel Dänzer goto out_cleanup; 107ecc0b326SMichel Dänzer } 108ecc0b326SMichel Dänzer 109a77f1718SMatt Turner r = radeon_copy(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, fence); 110ecc0b326SMichel Dänzer if (r) { 111ecc0b326SMichel Dänzer DRM_ERROR("Failed GTT->VRAM copy %d\n", i); 112ecc0b326SMichel Dänzer goto out_cleanup; 113ecc0b326SMichel Dänzer } 114ecc0b326SMichel Dänzer 115ecc0b326SMichel Dänzer r = radeon_fence_wait(fence, false); 116ecc0b326SMichel Dänzer if (r) { 117ecc0b326SMichel Dänzer DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i); 118ecc0b326SMichel Dänzer goto out_cleanup; 119ecc0b326SMichel Dänzer } 120ecc0b326SMichel Dänzer 121ecc0b326SMichel Dänzer radeon_fence_unref(&fence); 122ecc0b326SMichel Dänzer 1234c788679SJerome Glisse r = radeon_bo_kmap(vram_obj, &vram_map); 124ecc0b326SMichel Dänzer if (r) { 125ecc0b326SMichel Dänzer DRM_ERROR("Failed to map VRAM object after copy %d\n", i); 126ecc0b326SMichel Dänzer goto out_cleanup; 127ecc0b326SMichel Dänzer } 128ecc0b326SMichel Dänzer 129ecc0b326SMichel Dänzer for (gtt_start = gtt_map, gtt_end = gtt_map + size, 130ecc0b326SMichel Dänzer vram_start = vram_map, vram_end = vram_map + size; 131ecc0b326SMichel Dänzer vram_start < vram_end; 132ecc0b326SMichel Dänzer gtt_start++, vram_start++) { 133ecc0b326SMichel Dänzer if (*vram_start != gtt_start) { 134ecc0b326SMichel Dänzer DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, " 135ecc0b326SMichel Dänzer "expected 0x%p (GTT map 0x%p-0x%p)\n", 136ecc0b326SMichel Dänzer i, *vram_start, gtt_start, gtt_map, 137ecc0b326SMichel Dänzer gtt_end); 1384c788679SJerome Glisse radeon_bo_kunmap(vram_obj); 139ecc0b326SMichel Dänzer goto out_cleanup; 140ecc0b326SMichel Dänzer } 141ecc0b326SMichel Dänzer *vram_start = vram_start; 142ecc0b326SMichel Dänzer } 143ecc0b326SMichel Dänzer 1444c788679SJerome Glisse radeon_bo_kunmap(vram_obj); 145ecc0b326SMichel Dänzer 146ecc0b326SMichel Dänzer r = radeon_fence_create(rdev, &fence); 147ecc0b326SMichel Dänzer if (r) { 148ecc0b326SMichel Dänzer DRM_ERROR("Failed to create VRAM->GTT fence %d\n", i); 149ecc0b326SMichel Dänzer goto out_cleanup; 150ecc0b326SMichel Dänzer } 151ecc0b326SMichel Dänzer 152a77f1718SMatt Turner r = radeon_copy(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, fence); 153ecc0b326SMichel Dänzer if (r) { 154ecc0b326SMichel Dänzer DRM_ERROR("Failed VRAM->GTT copy %d\n", i); 155ecc0b326SMichel Dänzer goto out_cleanup; 156ecc0b326SMichel Dänzer } 157ecc0b326SMichel Dänzer 158ecc0b326SMichel Dänzer r = radeon_fence_wait(fence, false); 159ecc0b326SMichel Dänzer if (r) { 160ecc0b326SMichel Dänzer DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i); 161ecc0b326SMichel Dänzer goto out_cleanup; 162ecc0b326SMichel Dänzer } 163ecc0b326SMichel Dänzer 164ecc0b326SMichel Dänzer radeon_fence_unref(&fence); 165ecc0b326SMichel Dänzer 1664c788679SJerome Glisse r = radeon_bo_kmap(gtt_obj[i], >t_map); 167ecc0b326SMichel Dänzer if (r) { 168ecc0b326SMichel Dänzer DRM_ERROR("Failed to map GTT object after copy %d\n", i); 169ecc0b326SMichel Dänzer goto out_cleanup; 170ecc0b326SMichel Dänzer } 171ecc0b326SMichel Dänzer 172ecc0b326SMichel Dänzer for (gtt_start = gtt_map, gtt_end = gtt_map + size, 173ecc0b326SMichel Dänzer vram_start = vram_map, vram_end = vram_map + size; 174ecc0b326SMichel Dänzer gtt_start < gtt_end; 175ecc0b326SMichel Dänzer gtt_start++, vram_start++) { 176ecc0b326SMichel Dänzer if (*gtt_start != vram_start) { 177ecc0b326SMichel Dänzer DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, " 178ecc0b326SMichel Dänzer "expected 0x%p (VRAM map 0x%p-0x%p)\n", 179ecc0b326SMichel Dänzer i, *gtt_start, vram_start, vram_map, 180ecc0b326SMichel Dänzer vram_end); 1814c788679SJerome Glisse radeon_bo_kunmap(gtt_obj[i]); 182ecc0b326SMichel Dänzer goto out_cleanup; 183ecc0b326SMichel Dänzer } 184ecc0b326SMichel Dänzer } 185ecc0b326SMichel Dänzer 1864c788679SJerome Glisse radeon_bo_kunmap(gtt_obj[i]); 187ecc0b326SMichel Dänzer 188ecc0b326SMichel Dänzer DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n", 189d594e46aSJerome Glisse gtt_addr - rdev->mc.gtt_start); 190ecc0b326SMichel Dänzer } 191ecc0b326SMichel Dänzer 192ecc0b326SMichel Dänzer out_cleanup: 193ecc0b326SMichel Dänzer if (vram_obj) { 1944c788679SJerome Glisse if (radeon_bo_is_reserved(vram_obj)) { 1954c788679SJerome Glisse radeon_bo_unpin(vram_obj); 1964c788679SJerome Glisse radeon_bo_unreserve(vram_obj); 1974c788679SJerome Glisse } 1984c788679SJerome Glisse radeon_bo_unref(&vram_obj); 199ecc0b326SMichel Dänzer } 200ecc0b326SMichel Dänzer if (gtt_obj) { 201ecc0b326SMichel Dänzer for (i = 0; i < n; i++) { 202ecc0b326SMichel Dänzer if (gtt_obj[i]) { 2034c788679SJerome Glisse if (radeon_bo_is_reserved(gtt_obj[i])) { 2044c788679SJerome Glisse radeon_bo_unpin(gtt_obj[i]); 2054c788679SJerome Glisse radeon_bo_unreserve(gtt_obj[i]); 2064c788679SJerome Glisse } 2074c788679SJerome Glisse radeon_bo_unref(>t_obj[i]); 208ecc0b326SMichel Dänzer } 209ecc0b326SMichel Dänzer } 210ecc0b326SMichel Dänzer kfree(gtt_obj); 211ecc0b326SMichel Dänzer } 212ecc0b326SMichel Dänzer if (fence) { 213ecc0b326SMichel Dänzer radeon_fence_unref(&fence); 214ecc0b326SMichel Dänzer } 215ecc0b326SMichel Dänzer if (r) { 216ecc0b326SMichel Dänzer printk(KERN_WARNING "Error while testing BO move.\n"); 217ecc0b326SMichel Dänzer } 218ecc0b326SMichel Dänzer } 219