xref: /openbmc/linux/drivers/gpu/drm/radeon/radeon_pm.c (revision 0fcbe9473ac9c53463a61c9c83db8293bee15d12)
17433874eSRafał Miłecki /*
27433874eSRafał Miłecki  * Permission is hereby granted, free of charge, to any person obtaining a
37433874eSRafał Miłecki  * copy of this software and associated documentation files (the "Software"),
47433874eSRafał Miłecki  * to deal in the Software without restriction, including without limitation
57433874eSRafał Miłecki  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
67433874eSRafał Miłecki  * and/or sell copies of the Software, and to permit persons to whom the
77433874eSRafał Miłecki  * Software is furnished to do so, subject to the following conditions:
87433874eSRafał Miłecki  *
97433874eSRafał Miłecki  * The above copyright notice and this permission notice shall be included in
107433874eSRafał Miłecki  * all copies or substantial portions of the Software.
117433874eSRafał Miłecki  *
127433874eSRafał Miłecki  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
137433874eSRafał Miłecki  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
147433874eSRafał Miłecki  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
157433874eSRafał Miłecki  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
167433874eSRafał Miłecki  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
177433874eSRafał Miłecki  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
187433874eSRafał Miłecki  * OTHER DEALINGS IN THE SOFTWARE.
197433874eSRafał Miłecki  *
207433874eSRafał Miłecki  * Authors: Rafał Miłecki <zajec5@gmail.com>
2156278a8eSAlex Deucher  *          Alex Deucher <alexdeucher@gmail.com>
227433874eSRafał Miłecki  */
237433874eSRafał Miłecki #include "drmP.h"
247433874eSRafał Miłecki #include "radeon.h"
25f735261bSDave Airlie #include "avivod.h"
26ce8f5370SAlex Deucher #ifdef CONFIG_ACPI
27ce8f5370SAlex Deucher #include <linux/acpi.h>
28ce8f5370SAlex Deucher #endif
29ce8f5370SAlex Deucher #include <linux/power_supply.h>
307433874eSRafał Miłecki 
31c913e23aSRafał Miłecki #define RADEON_IDLE_LOOP_MS 100
32c913e23aSRafał Miłecki #define RADEON_RECLOCK_DELAY_MS 200
3373a6d3fcSRafał Miłecki #define RADEON_WAIT_VBLANK_TIMEOUT 200
342031f77cSAlex Deucher #define RADEON_WAIT_IDLE_TIMEOUT 200
35c913e23aSRafał Miłecki 
36ce8f5370SAlex Deucher static void radeon_dynpm_idle_work_handler(struct work_struct *work);
37c913e23aSRafał Miłecki static int radeon_debugfs_pm_init(struct radeon_device *rdev);
38ce8f5370SAlex Deucher static bool radeon_pm_in_vbl(struct radeon_device *rdev);
39ce8f5370SAlex Deucher static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
40ce8f5370SAlex Deucher static void radeon_pm_update_profile(struct radeon_device *rdev);
41ce8f5370SAlex Deucher static void radeon_pm_set_clocks(struct radeon_device *rdev);
42ce8f5370SAlex Deucher 
43ce8f5370SAlex Deucher #define ACPI_AC_CLASS           "ac_adapter"
44ce8f5370SAlex Deucher 
45ce8f5370SAlex Deucher #ifdef CONFIG_ACPI
46ce8f5370SAlex Deucher static int radeon_acpi_event(struct notifier_block *nb,
47ce8f5370SAlex Deucher 			     unsigned long val,
48ce8f5370SAlex Deucher 			     void *data)
49ce8f5370SAlex Deucher {
50ce8f5370SAlex Deucher 	struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
51ce8f5370SAlex Deucher 	struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
52ce8f5370SAlex Deucher 
53ce8f5370SAlex Deucher 	if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
54ce8f5370SAlex Deucher 		if (power_supply_is_system_supplied() > 0)
55ce8a3eb2SAlex Deucher 			DRM_DEBUG("pm: AC\n");
56ce8f5370SAlex Deucher 		else
57ce8a3eb2SAlex Deucher 			DRM_DEBUG("pm: DC\n");
58ce8f5370SAlex Deucher 
59ce8f5370SAlex Deucher 		if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
60ce8f5370SAlex Deucher 			if (rdev->pm.profile == PM_PROFILE_AUTO) {
61ce8f5370SAlex Deucher 				mutex_lock(&rdev->pm.mutex);
62ce8f5370SAlex Deucher 				radeon_pm_update_profile(rdev);
63ce8f5370SAlex Deucher 				radeon_pm_set_clocks(rdev);
64ce8f5370SAlex Deucher 				mutex_unlock(&rdev->pm.mutex);
65ce8f5370SAlex Deucher 			}
66ce8f5370SAlex Deucher 		}
67ce8f5370SAlex Deucher 	}
68ce8f5370SAlex Deucher 
69ce8f5370SAlex Deucher 	return NOTIFY_OK;
70ce8f5370SAlex Deucher }
71ce8f5370SAlex Deucher #endif
72ce8f5370SAlex Deucher 
73ce8f5370SAlex Deucher static void radeon_pm_update_profile(struct radeon_device *rdev)
74ce8f5370SAlex Deucher {
75ce8f5370SAlex Deucher 	switch (rdev->pm.profile) {
76ce8f5370SAlex Deucher 	case PM_PROFILE_DEFAULT:
77ce8f5370SAlex Deucher 		rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
78ce8f5370SAlex Deucher 		break;
79ce8f5370SAlex Deucher 	case PM_PROFILE_AUTO:
80ce8f5370SAlex Deucher 		if (power_supply_is_system_supplied() > 0) {
81ce8f5370SAlex Deucher 			if (rdev->pm.active_crtc_count > 1)
82ce8f5370SAlex Deucher 				rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
83ce8f5370SAlex Deucher 			else
84ce8f5370SAlex Deucher 				rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
85ce8f5370SAlex Deucher 		} else {
86ce8f5370SAlex Deucher 			if (rdev->pm.active_crtc_count > 1)
87c9e75b21SAlex Deucher 				rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
88ce8f5370SAlex Deucher 			else
89c9e75b21SAlex Deucher 				rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
90ce8f5370SAlex Deucher 		}
91ce8f5370SAlex Deucher 		break;
92ce8f5370SAlex Deucher 	case PM_PROFILE_LOW:
93ce8f5370SAlex Deucher 		if (rdev->pm.active_crtc_count > 1)
94ce8f5370SAlex Deucher 			rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
95ce8f5370SAlex Deucher 		else
96ce8f5370SAlex Deucher 			rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
97ce8f5370SAlex Deucher 		break;
98c9e75b21SAlex Deucher 	case PM_PROFILE_MID:
99c9e75b21SAlex Deucher 		if (rdev->pm.active_crtc_count > 1)
100c9e75b21SAlex Deucher 			rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
101c9e75b21SAlex Deucher 		else
102c9e75b21SAlex Deucher 			rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
103c9e75b21SAlex Deucher 		break;
104ce8f5370SAlex Deucher 	case PM_PROFILE_HIGH:
105ce8f5370SAlex Deucher 		if (rdev->pm.active_crtc_count > 1)
106ce8f5370SAlex Deucher 			rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
107ce8f5370SAlex Deucher 		else
108ce8f5370SAlex Deucher 			rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
109ce8f5370SAlex Deucher 		break;
110ce8f5370SAlex Deucher 	}
111ce8f5370SAlex Deucher 
112ce8f5370SAlex Deucher 	if (rdev->pm.active_crtc_count == 0) {
113ce8f5370SAlex Deucher 		rdev->pm.requested_power_state_index =
114ce8f5370SAlex Deucher 			rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
115ce8f5370SAlex Deucher 		rdev->pm.requested_clock_mode_index =
116ce8f5370SAlex Deucher 			rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
117ce8f5370SAlex Deucher 	} else {
118ce8f5370SAlex Deucher 		rdev->pm.requested_power_state_index =
119ce8f5370SAlex Deucher 			rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
120ce8f5370SAlex Deucher 		rdev->pm.requested_clock_mode_index =
121ce8f5370SAlex Deucher 			rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
122ce8f5370SAlex Deucher 	}
123ce8f5370SAlex Deucher }
124c913e23aSRafał Miłecki 
1255876dd24SMatthew Garrett static void radeon_unmap_vram_bos(struct radeon_device *rdev)
1265876dd24SMatthew Garrett {
1275876dd24SMatthew Garrett 	struct radeon_bo *bo, *n;
1285876dd24SMatthew Garrett 
1295876dd24SMatthew Garrett 	if (list_empty(&rdev->gem.objects))
1305876dd24SMatthew Garrett 		return;
1315876dd24SMatthew Garrett 
1325876dd24SMatthew Garrett 	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
1335876dd24SMatthew Garrett 		if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
1345876dd24SMatthew Garrett 			ttm_bo_unmap_virtual(&bo->tbo);
1355876dd24SMatthew Garrett 	}
1365876dd24SMatthew Garrett }
1375876dd24SMatthew Garrett 
138ce8f5370SAlex Deucher static void radeon_sync_with_vblank(struct radeon_device *rdev)
139ce8f5370SAlex Deucher {
140ce8f5370SAlex Deucher 	if (rdev->pm.active_crtcs) {
141ce8f5370SAlex Deucher 		rdev->pm.vblank_sync = false;
142ce8f5370SAlex Deucher 		wait_event_timeout(
143ce8f5370SAlex Deucher 			rdev->irq.vblank_queue, rdev->pm.vblank_sync,
144ce8f5370SAlex Deucher 			msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
145ce8f5370SAlex Deucher 	}
146ce8f5370SAlex Deucher }
147ce8f5370SAlex Deucher 
148ce8f5370SAlex Deucher static void radeon_set_power_state(struct radeon_device *rdev)
149ce8f5370SAlex Deucher {
150ce8f5370SAlex Deucher 	u32 sclk, mclk;
15192645879SAlex Deucher 	bool misc_after = false;
152ce8f5370SAlex Deucher 
153ce8f5370SAlex Deucher 	if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
154ce8f5370SAlex Deucher 	    (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
155ce8f5370SAlex Deucher 		return;
156ce8f5370SAlex Deucher 
157ce8f5370SAlex Deucher 	if (radeon_gui_idle(rdev)) {
158ce8f5370SAlex Deucher 		sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
159ce8f5370SAlex Deucher 			clock_info[rdev->pm.requested_clock_mode_index].sclk;
160ce8f5370SAlex Deucher 		if (sclk > rdev->clock.default_sclk)
161ce8f5370SAlex Deucher 			sclk = rdev->clock.default_sclk;
162ce8f5370SAlex Deucher 
163ce8f5370SAlex Deucher 		mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
164ce8f5370SAlex Deucher 			clock_info[rdev->pm.requested_clock_mode_index].mclk;
165ce8f5370SAlex Deucher 		if (mclk > rdev->clock.default_mclk)
166ce8f5370SAlex Deucher 			mclk = rdev->clock.default_mclk;
167ce8f5370SAlex Deucher 
16892645879SAlex Deucher 		/* upvolt before raising clocks, downvolt after lowering clocks */
16992645879SAlex Deucher 		if (sclk < rdev->pm.current_sclk)
17092645879SAlex Deucher 			misc_after = true;
17192645879SAlex Deucher 
17292645879SAlex Deucher 		radeon_sync_with_vblank(rdev);
17392645879SAlex Deucher 
17492645879SAlex Deucher 		if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
17592645879SAlex Deucher 			if (!radeon_pm_in_vbl(rdev))
17692645879SAlex Deucher 				return;
17792645879SAlex Deucher 		}
17892645879SAlex Deucher 
17992645879SAlex Deucher 		radeon_pm_prepare(rdev);
18092645879SAlex Deucher 
18192645879SAlex Deucher 		if (!misc_after)
182ce8f5370SAlex Deucher 			/* voltage, pcie lanes, etc.*/
183ce8f5370SAlex Deucher 			radeon_pm_misc(rdev);
184ce8f5370SAlex Deucher 
185ce8f5370SAlex Deucher 		/* set engine clock */
186ce8f5370SAlex Deucher 		if (sclk != rdev->pm.current_sclk) {
187ce8f5370SAlex Deucher 			radeon_pm_debug_check_in_vbl(rdev, false);
188ce8f5370SAlex Deucher 			radeon_set_engine_clock(rdev, sclk);
189ce8f5370SAlex Deucher 			radeon_pm_debug_check_in_vbl(rdev, true);
190ce8f5370SAlex Deucher 			rdev->pm.current_sclk = sclk;
191ce8a3eb2SAlex Deucher 			DRM_DEBUG("Setting: e: %d\n", sclk);
192ce8f5370SAlex Deucher 		}
193ce8f5370SAlex Deucher 
194ce8f5370SAlex Deucher 		/* set memory clock */
195ce8f5370SAlex Deucher 		if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
196ce8f5370SAlex Deucher 			radeon_pm_debug_check_in_vbl(rdev, false);
197ce8f5370SAlex Deucher 			radeon_set_memory_clock(rdev, mclk);
198ce8f5370SAlex Deucher 			radeon_pm_debug_check_in_vbl(rdev, true);
199ce8f5370SAlex Deucher 			rdev->pm.current_mclk = mclk;
200ce8a3eb2SAlex Deucher 			DRM_DEBUG("Setting: m: %d\n", mclk);
201ce8f5370SAlex Deucher 		}
20292645879SAlex Deucher 
20392645879SAlex Deucher 		if (misc_after)
20492645879SAlex Deucher 			/* voltage, pcie lanes, etc.*/
20592645879SAlex Deucher 			radeon_pm_misc(rdev);
20692645879SAlex Deucher 
207ce8f5370SAlex Deucher 		radeon_pm_finish(rdev);
208ce8f5370SAlex Deucher 
209ce8f5370SAlex Deucher 		rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
210ce8f5370SAlex Deucher 		rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
211ce8f5370SAlex Deucher 	} else
212ce8a3eb2SAlex Deucher 		DRM_DEBUG("pm: GUI not idle!!!\n");
213ce8f5370SAlex Deucher }
214ce8f5370SAlex Deucher 
215ce8f5370SAlex Deucher static void radeon_pm_set_clocks(struct radeon_device *rdev)
216a424816fSAlex Deucher {
2172aba631cSMatthew Garrett 	int i;
2182aba631cSMatthew Garrett 
219612e06ceSMatthew Garrett 	mutex_lock(&rdev->ddev->struct_mutex);
220612e06ceSMatthew Garrett 	mutex_lock(&rdev->vram_mutex);
221a424816fSAlex Deucher 	mutex_lock(&rdev->cp.mutex);
2224f3218cbSAlex Deucher 
2234f3218cbSAlex Deucher 	/* gui idle int has issues on older chips it seems */
2244f3218cbSAlex Deucher 	if (rdev->family >= CHIP_R600) {
225ce8f5370SAlex Deucher 		if (rdev->irq.installed) {
226a424816fSAlex Deucher 			/* wait for GPU idle */
227a424816fSAlex Deucher 			rdev->pm.gui_idle = false;
228a424816fSAlex Deucher 			rdev->irq.gui_idle = true;
229a424816fSAlex Deucher 			radeon_irq_set(rdev);
230a424816fSAlex Deucher 			wait_event_interruptible_timeout(
231a424816fSAlex Deucher 				rdev->irq.idle_queue, rdev->pm.gui_idle,
232a424816fSAlex Deucher 				msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
233a424816fSAlex Deucher 			rdev->irq.gui_idle = false;
234a424816fSAlex Deucher 			radeon_irq_set(rdev);
235ce8f5370SAlex Deucher 		}
23601434b4bSMatthew Garrett 	} else {
237ce8f5370SAlex Deucher 		if (rdev->cp.ready) {
23801434b4bSMatthew Garrett 			struct radeon_fence *fence;
23901434b4bSMatthew Garrett 			radeon_ring_alloc(rdev, 64);
24001434b4bSMatthew Garrett 			radeon_fence_create(rdev, &fence);
24101434b4bSMatthew Garrett 			radeon_fence_emit(rdev, fence);
24201434b4bSMatthew Garrett 			radeon_ring_commit(rdev);
24301434b4bSMatthew Garrett 			radeon_fence_wait(fence, false);
24401434b4bSMatthew Garrett 			radeon_fence_unref(&fence);
2454f3218cbSAlex Deucher 		}
246ce8f5370SAlex Deucher 	}
2475876dd24SMatthew Garrett 	radeon_unmap_vram_bos(rdev);
2485876dd24SMatthew Garrett 
249ce8f5370SAlex Deucher 	if (rdev->irq.installed) {
2502aba631cSMatthew Garrett 		for (i = 0; i < rdev->num_crtc; i++) {
2512aba631cSMatthew Garrett 			if (rdev->pm.active_crtcs & (1 << i)) {
2522aba631cSMatthew Garrett 				rdev->pm.req_vblank |= (1 << i);
2532aba631cSMatthew Garrett 				drm_vblank_get(rdev->ddev, i);
2542aba631cSMatthew Garrett 			}
2552aba631cSMatthew Garrett 		}
2562aba631cSMatthew Garrett 	}
2572aba631cSMatthew Garrett 
258ce8f5370SAlex Deucher 	radeon_set_power_state(rdev);
2592aba631cSMatthew Garrett 
260ce8f5370SAlex Deucher 	if (rdev->irq.installed) {
2612aba631cSMatthew Garrett 		for (i = 0; i < rdev->num_crtc; i++) {
2622aba631cSMatthew Garrett 			if (rdev->pm.req_vblank & (1 << i)) {
2632aba631cSMatthew Garrett 				rdev->pm.req_vblank &= ~(1 << i);
2642aba631cSMatthew Garrett 				drm_vblank_put(rdev->ddev, i);
2652aba631cSMatthew Garrett 			}
2662aba631cSMatthew Garrett 		}
2672aba631cSMatthew Garrett 	}
268a424816fSAlex Deucher 
269a424816fSAlex Deucher 	/* update display watermarks based on new power state */
270a424816fSAlex Deucher 	radeon_update_bandwidth_info(rdev);
271a424816fSAlex Deucher 	if (rdev->pm.active_crtc_count)
272a424816fSAlex Deucher 		radeon_bandwidth_update(rdev);
273a424816fSAlex Deucher 
274ce8f5370SAlex Deucher 	rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2752aba631cSMatthew Garrett 
276a424816fSAlex Deucher 	mutex_unlock(&rdev->cp.mutex);
277612e06ceSMatthew Garrett 	mutex_unlock(&rdev->vram_mutex);
278612e06ceSMatthew Garrett 	mutex_unlock(&rdev->ddev->struct_mutex);
279a424816fSAlex Deucher }
280a424816fSAlex Deucher 
281ce8f5370SAlex Deucher static ssize_t radeon_get_pm_profile(struct device *dev,
282a424816fSAlex Deucher 				     struct device_attribute *attr,
283a424816fSAlex Deucher 				     char *buf)
284a424816fSAlex Deucher {
285a424816fSAlex Deucher 	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
286a424816fSAlex Deucher 	struct radeon_device *rdev = ddev->dev_private;
287ce8f5370SAlex Deucher 	int cp = rdev->pm.profile;
288a424816fSAlex Deucher 
289a424816fSAlex Deucher 	return snprintf(buf, PAGE_SIZE, "%s\n",
290ce8f5370SAlex Deucher 			(cp == PM_PROFILE_AUTO) ? "auto" :
291ce8f5370SAlex Deucher 			(cp == PM_PROFILE_LOW) ? "low" :
292ce8f5370SAlex Deucher 			(cp == PM_PROFILE_HIGH) ? "high" : "default");
293a424816fSAlex Deucher }
294a424816fSAlex Deucher 
295ce8f5370SAlex Deucher static ssize_t radeon_set_pm_profile(struct device *dev,
296a424816fSAlex Deucher 				     struct device_attribute *attr,
297a424816fSAlex Deucher 				     const char *buf,
298a424816fSAlex Deucher 				     size_t count)
299a424816fSAlex Deucher {
300a424816fSAlex Deucher 	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
301a424816fSAlex Deucher 	struct radeon_device *rdev = ddev->dev_private;
302a424816fSAlex Deucher 
303a424816fSAlex Deucher 	mutex_lock(&rdev->pm.mutex);
304ce8f5370SAlex Deucher 	if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
305ce8f5370SAlex Deucher 		if (strncmp("default", buf, strlen("default")) == 0)
306ce8f5370SAlex Deucher 			rdev->pm.profile = PM_PROFILE_DEFAULT;
307ce8f5370SAlex Deucher 		else if (strncmp("auto", buf, strlen("auto")) == 0)
308ce8f5370SAlex Deucher 			rdev->pm.profile = PM_PROFILE_AUTO;
309ce8f5370SAlex Deucher 		else if (strncmp("low", buf, strlen("low")) == 0)
310ce8f5370SAlex Deucher 			rdev->pm.profile = PM_PROFILE_LOW;
311c9e75b21SAlex Deucher 		else if (strncmp("mid", buf, strlen("mid")) == 0)
312c9e75b21SAlex Deucher 			rdev->pm.profile = PM_PROFILE_MID;
313ce8f5370SAlex Deucher 		else if (strncmp("high", buf, strlen("high")) == 0)
314ce8f5370SAlex Deucher 			rdev->pm.profile = PM_PROFILE_HIGH;
315ce8f5370SAlex Deucher 		else {
316ce8f5370SAlex Deucher 			DRM_ERROR("invalid power profile!\n");
317ce8f5370SAlex Deucher 			goto fail;
318ce8f5370SAlex Deucher 		}
319ce8f5370SAlex Deucher 		radeon_pm_update_profile(rdev);
320ce8f5370SAlex Deucher 		radeon_pm_set_clocks(rdev);
321ce8f5370SAlex Deucher 	}
322ce8f5370SAlex Deucher fail:
323a424816fSAlex Deucher 	mutex_unlock(&rdev->pm.mutex);
324a424816fSAlex Deucher 
325a424816fSAlex Deucher 	return count;
326a424816fSAlex Deucher }
327a424816fSAlex Deucher 
328ce8f5370SAlex Deucher static ssize_t radeon_get_pm_method(struct device *dev,
329ce8f5370SAlex Deucher 				    struct device_attribute *attr,
330ce8f5370SAlex Deucher 				    char *buf)
33156278a8eSAlex Deucher {
332ce8f5370SAlex Deucher 	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
333ce8f5370SAlex Deucher 	struct radeon_device *rdev = ddev->dev_private;
334ce8f5370SAlex Deucher 	int pm = rdev->pm.pm_method;
33556278a8eSAlex Deucher 
336ce8f5370SAlex Deucher 	return snprintf(buf, PAGE_SIZE, "%s\n",
337ce8f5370SAlex Deucher 			(pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
33856278a8eSAlex Deucher }
33956278a8eSAlex Deucher 
340ce8f5370SAlex Deucher static ssize_t radeon_set_pm_method(struct device *dev,
341ce8f5370SAlex Deucher 				    struct device_attribute *attr,
342ce8f5370SAlex Deucher 				    const char *buf,
343ce8f5370SAlex Deucher 				    size_t count)
344d0d6cb81SRafał Miłecki {
345ce8f5370SAlex Deucher 	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
346ce8f5370SAlex Deucher 	struct radeon_device *rdev = ddev->dev_private;
347ce8f5370SAlex Deucher 
348ce8f5370SAlex Deucher 
349ce8f5370SAlex Deucher 	if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
350ce8f5370SAlex Deucher 		mutex_lock(&rdev->pm.mutex);
351ce8f5370SAlex Deucher 		rdev->pm.pm_method = PM_METHOD_DYNPM;
352ce8f5370SAlex Deucher 		rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
353ce8f5370SAlex Deucher 		rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
354ce8f5370SAlex Deucher 		mutex_unlock(&rdev->pm.mutex);
355ce8f5370SAlex Deucher 	} else if (strncmp("profile", buf, strlen("profile")) == 0) {
356ce8f5370SAlex Deucher 		mutex_lock(&rdev->pm.mutex);
357ce8f5370SAlex Deucher 		rdev->pm.pm_method = PM_METHOD_PROFILE;
358ce8f5370SAlex Deucher 		/* disable dynpm */
359ce8f5370SAlex Deucher 		rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
360ce8f5370SAlex Deucher 		rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
361ce8f5370SAlex Deucher 		cancel_delayed_work(&rdev->pm.dynpm_idle_work);
362ce8f5370SAlex Deucher 		mutex_unlock(&rdev->pm.mutex);
363ce8f5370SAlex Deucher 	} else {
364ce8f5370SAlex Deucher 		DRM_ERROR("invalid power method!\n");
365ce8f5370SAlex Deucher 		goto fail;
366d0d6cb81SRafał Miłecki 	}
367ce8f5370SAlex Deucher 	radeon_pm_compute_clocks(rdev);
368ce8f5370SAlex Deucher fail:
369ce8f5370SAlex Deucher 	return count;
370ce8f5370SAlex Deucher }
371ce8f5370SAlex Deucher 
372ce8f5370SAlex Deucher static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
373ce8f5370SAlex Deucher static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
374ce8f5370SAlex Deucher 
375ce8f5370SAlex Deucher void radeon_pm_suspend(struct radeon_device *rdev)
376ce8f5370SAlex Deucher {
377ce8f5370SAlex Deucher 	mutex_lock(&rdev->pm.mutex);
378ce8f5370SAlex Deucher 	cancel_delayed_work(&rdev->pm.dynpm_idle_work);
379ce8f5370SAlex Deucher 	mutex_unlock(&rdev->pm.mutex);
380ce8f5370SAlex Deucher }
381ce8f5370SAlex Deucher 
382ce8f5370SAlex Deucher void radeon_pm_resume(struct radeon_device *rdev)
383ce8f5370SAlex Deucher {
384f8ed8b4cSAlex Deucher 	/* asic init will reset the default power state */
385f8ed8b4cSAlex Deucher 	mutex_lock(&rdev->pm.mutex);
386f8ed8b4cSAlex Deucher 	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
387f8ed8b4cSAlex Deucher 	rdev->pm.current_clock_mode_index = 0;
388f8ed8b4cSAlex Deucher 	rdev->pm.current_sclk = rdev->clock.default_sclk;
389f8ed8b4cSAlex Deucher 	rdev->pm.current_mclk = rdev->clock.default_mclk;
3904d60173fSAlex Deucher 	rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
391f8ed8b4cSAlex Deucher 	mutex_unlock(&rdev->pm.mutex);
392ce8f5370SAlex Deucher 	radeon_pm_compute_clocks(rdev);
393d0d6cb81SRafał Miłecki }
394d0d6cb81SRafał Miłecki 
3957433874eSRafał Miłecki int radeon_pm_init(struct radeon_device *rdev)
3967433874eSRafał Miłecki {
39726481fb1SDave Airlie 	int ret;
398ce8f5370SAlex Deucher 	/* default to profile method */
399ce8f5370SAlex Deucher 	rdev->pm.pm_method = PM_METHOD_PROFILE;
400f8ed8b4cSAlex Deucher 	rdev->pm.profile = PM_PROFILE_DEFAULT;
401ce8f5370SAlex Deucher 	rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
402ce8f5370SAlex Deucher 	rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
403ce8f5370SAlex Deucher 	rdev->pm.dynpm_can_upclock = true;
404ce8f5370SAlex Deucher 	rdev->pm.dynpm_can_downclock = true;
405f8ed8b4cSAlex Deucher 	rdev->pm.current_sclk = rdev->clock.default_sclk;
406f8ed8b4cSAlex Deucher 	rdev->pm.current_mclk = rdev->clock.default_mclk;
407c913e23aSRafał Miłecki 
40856278a8eSAlex Deucher 	if (rdev->bios) {
40956278a8eSAlex Deucher 		if (rdev->is_atom_bios)
41056278a8eSAlex Deucher 			radeon_atombios_get_power_modes(rdev);
41156278a8eSAlex Deucher 		else
41256278a8eSAlex Deucher 			radeon_combios_get_power_modes(rdev);
413ce8f5370SAlex Deucher 		radeon_pm_init_profile(rdev);
41456278a8eSAlex Deucher 	}
41556278a8eSAlex Deucher 
416ce8f5370SAlex Deucher 	if (rdev->pm.num_power_states > 1) {
417ce8f5370SAlex Deucher 		/* where's the best place to put these? */
41826481fb1SDave Airlie 		ret = device_create_file(rdev->dev, &dev_attr_power_profile);
41926481fb1SDave Airlie 		if (ret)
42026481fb1SDave Airlie 			DRM_ERROR("failed to create device file for power profile\n");
42126481fb1SDave Airlie 		ret = device_create_file(rdev->dev, &dev_attr_power_method);
42226481fb1SDave Airlie 		if (ret)
42326481fb1SDave Airlie 			DRM_ERROR("failed to create device file for power method\n");
424ce8f5370SAlex Deucher 
425ce8f5370SAlex Deucher #ifdef CONFIG_ACPI
426ce8f5370SAlex Deucher 		rdev->acpi_nb.notifier_call = radeon_acpi_event;
427ce8f5370SAlex Deucher 		register_acpi_notifier(&rdev->acpi_nb);
428ce8f5370SAlex Deucher #endif
429ce8f5370SAlex Deucher 		INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
430ce8f5370SAlex Deucher 
4317433874eSRafał Miłecki 		if (radeon_debugfs_pm_init(rdev)) {
432c142c3e5SRafał Miłecki 			DRM_ERROR("Failed to register debugfs file for PM!\n");
4337433874eSRafał Miłecki 		}
4347433874eSRafał Miłecki 
435c913e23aSRafał Miłecki 		DRM_INFO("radeon: power management initialized\n");
436ce8f5370SAlex Deucher 	}
437c913e23aSRafał Miłecki 
4387433874eSRafał Miłecki 	return 0;
4397433874eSRafał Miłecki }
4407433874eSRafał Miłecki 
44129fb52caSAlex Deucher void radeon_pm_fini(struct radeon_device *rdev)
44229fb52caSAlex Deucher {
443ce8f5370SAlex Deucher 	if (rdev->pm.num_power_states > 1) {
444a424816fSAlex Deucher 		mutex_lock(&rdev->pm.mutex);
445ce8f5370SAlex Deucher 		if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
446ce8f5370SAlex Deucher 			rdev->pm.profile = PM_PROFILE_DEFAULT;
447ce8f5370SAlex Deucher 			radeon_pm_update_profile(rdev);
448ce8f5370SAlex Deucher 			radeon_pm_set_clocks(rdev);
449ce8f5370SAlex Deucher 		} else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
450ce8f5370SAlex Deucher 			/* cancel work */
451ce8f5370SAlex Deucher 			cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
452ce8f5370SAlex Deucher 			/* reset default clocks */
453ce8f5370SAlex Deucher 			rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
454ce8f5370SAlex Deucher 			rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
455ce8f5370SAlex Deucher 			radeon_pm_set_clocks(rdev);
45658e21dffSAlex Deucher 		}
457ce8f5370SAlex Deucher 		mutex_unlock(&rdev->pm.mutex);
45858e21dffSAlex Deucher 
459ce8f5370SAlex Deucher 		device_remove_file(rdev->dev, &dev_attr_power_profile);
460ce8f5370SAlex Deucher 		device_remove_file(rdev->dev, &dev_attr_power_method);
461ce8f5370SAlex Deucher #ifdef CONFIG_ACPI
462ce8f5370SAlex Deucher 		unregister_acpi_notifier(&rdev->acpi_nb);
463ce8f5370SAlex Deucher #endif
464ce8f5370SAlex Deucher 	}
465a424816fSAlex Deucher 
46629fb52caSAlex Deucher 	if (rdev->pm.i2c_bus)
46729fb52caSAlex Deucher 		radeon_i2c_destroy(rdev->pm.i2c_bus);
46829fb52caSAlex Deucher }
46929fb52caSAlex Deucher 
470c913e23aSRafał Miłecki void radeon_pm_compute_clocks(struct radeon_device *rdev)
471c913e23aSRafał Miłecki {
472c913e23aSRafał Miłecki 	struct drm_device *ddev = rdev->ddev;
473a48b9b4eSAlex Deucher 	struct drm_crtc *crtc;
474c913e23aSRafał Miłecki 	struct radeon_crtc *radeon_crtc;
475c913e23aSRafał Miłecki 
476ce8f5370SAlex Deucher 	if (rdev->pm.num_power_states < 2)
477ce8f5370SAlex Deucher 		return;
478ce8f5370SAlex Deucher 
479c913e23aSRafał Miłecki 	mutex_lock(&rdev->pm.mutex);
480c913e23aSRafał Miłecki 
481c913e23aSRafał Miłecki 	rdev->pm.active_crtcs = 0;
482a48b9b4eSAlex Deucher 	rdev->pm.active_crtc_count = 0;
483a48b9b4eSAlex Deucher 	list_for_each_entry(crtc,
484a48b9b4eSAlex Deucher 		&ddev->mode_config.crtc_list, head) {
485a48b9b4eSAlex Deucher 		radeon_crtc = to_radeon_crtc(crtc);
486a48b9b4eSAlex Deucher 		if (radeon_crtc->enabled) {
487c913e23aSRafał Miłecki 			rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
488a48b9b4eSAlex Deucher 			rdev->pm.active_crtc_count++;
489c913e23aSRafał Miłecki 		}
490c913e23aSRafał Miłecki 	}
491c913e23aSRafał Miłecki 
492ce8f5370SAlex Deucher 	if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
493ce8f5370SAlex Deucher 		radeon_pm_update_profile(rdev);
494ce8f5370SAlex Deucher 		radeon_pm_set_clocks(rdev);
495ce8f5370SAlex Deucher 	} else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
496ce8f5370SAlex Deucher 		if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
497a48b9b4eSAlex Deucher 			if (rdev->pm.active_crtc_count > 1) {
498ce8f5370SAlex Deucher 				if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
499ce8f5370SAlex Deucher 					cancel_delayed_work(&rdev->pm.dynpm_idle_work);
500c913e23aSRafał Miłecki 
501ce8f5370SAlex Deucher 					rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
502ce8f5370SAlex Deucher 					rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
503ce8f5370SAlex Deucher 					radeon_pm_get_dynpm_state(rdev);
504ce8f5370SAlex Deucher 					radeon_pm_set_clocks(rdev);
505c913e23aSRafał Miłecki 
506c913e23aSRafał Miłecki 					DRM_DEBUG("radeon: dynamic power management deactivated\n");
507c913e23aSRafał Miłecki 				}
508a48b9b4eSAlex Deucher 			} else if (rdev->pm.active_crtc_count == 1) {
509c913e23aSRafał Miłecki 				/* TODO: Increase clocks if needed for current mode */
510c913e23aSRafał Miłecki 
511ce8f5370SAlex Deucher 				if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
512ce8f5370SAlex Deucher 					rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
513ce8f5370SAlex Deucher 					rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
514ce8f5370SAlex Deucher 					radeon_pm_get_dynpm_state(rdev);
515ce8f5370SAlex Deucher 					radeon_pm_set_clocks(rdev);
516c913e23aSRafał Miłecki 
517ce8f5370SAlex Deucher 					queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
518c913e23aSRafał Miłecki 							   msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
519ce8f5370SAlex Deucher 				} else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
520ce8f5370SAlex Deucher 					rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
521ce8f5370SAlex Deucher 					queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
522c913e23aSRafał Miłecki 							   msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
523c913e23aSRafał Miłecki 					DRM_DEBUG("radeon: dynamic power management activated\n");
524c913e23aSRafał Miłecki 				}
525a48b9b4eSAlex Deucher 			} else { /* count == 0 */
526ce8f5370SAlex Deucher 				if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
527ce8f5370SAlex Deucher 					cancel_delayed_work(&rdev->pm.dynpm_idle_work);
528c913e23aSRafał Miłecki 
529ce8f5370SAlex Deucher 					rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
530ce8f5370SAlex Deucher 					rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
531ce8f5370SAlex Deucher 					radeon_pm_get_dynpm_state(rdev);
532ce8f5370SAlex Deucher 					radeon_pm_set_clocks(rdev);
533ce8f5370SAlex Deucher 				}
534ce8f5370SAlex Deucher 			}
53573a6d3fcSRafał Miłecki 		}
536c913e23aSRafał Miłecki 	}
537c913e23aSRafał Miłecki 
538c913e23aSRafał Miłecki 	mutex_unlock(&rdev->pm.mutex);
539c913e23aSRafał Miłecki }
540c913e23aSRafał Miłecki 
541ce8f5370SAlex Deucher static bool radeon_pm_in_vbl(struct radeon_device *rdev)
542f735261bSDave Airlie {
543539d2418SAlex Deucher 	u32 stat_crtc = 0, vbl = 0, position = 0;
544f735261bSDave Airlie 	bool in_vbl = true;
545f735261bSDave Airlie 
546bae6b562SAlex Deucher 	if (ASIC_IS_DCE4(rdev)) {
547f735261bSDave Airlie 		if (rdev->pm.active_crtcs & (1 << 0)) {
548539d2418SAlex Deucher 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
549539d2418SAlex Deucher 				     EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
550539d2418SAlex Deucher 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
551539d2418SAlex Deucher 					  EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
552f735261bSDave Airlie 		}
553f735261bSDave Airlie 		if (rdev->pm.active_crtcs & (1 << 1)) {
554539d2418SAlex Deucher 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
555539d2418SAlex Deucher 				     EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
556539d2418SAlex Deucher 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
557539d2418SAlex Deucher 					  EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
558bae6b562SAlex Deucher 		}
559bae6b562SAlex Deucher 		if (rdev->pm.active_crtcs & (1 << 2)) {
560539d2418SAlex Deucher 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
561539d2418SAlex Deucher 				     EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
562539d2418SAlex Deucher 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
563539d2418SAlex Deucher 					  EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
564bae6b562SAlex Deucher 		}
565bae6b562SAlex Deucher 		if (rdev->pm.active_crtcs & (1 << 3)) {
566539d2418SAlex Deucher 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
567539d2418SAlex Deucher 				     EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
568539d2418SAlex Deucher 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
569539d2418SAlex Deucher 					  EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
570bae6b562SAlex Deucher 		}
571bae6b562SAlex Deucher 		if (rdev->pm.active_crtcs & (1 << 4)) {
572539d2418SAlex Deucher 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
573539d2418SAlex Deucher 				     EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
574539d2418SAlex Deucher 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
575539d2418SAlex Deucher 					  EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
576bae6b562SAlex Deucher 		}
577bae6b562SAlex Deucher 		if (rdev->pm.active_crtcs & (1 << 5)) {
578539d2418SAlex Deucher 			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
579539d2418SAlex Deucher 				     EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
580539d2418SAlex Deucher 			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
581539d2418SAlex Deucher 					  EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
582bae6b562SAlex Deucher 		}
583bae6b562SAlex Deucher 	} else if (ASIC_IS_AVIVO(rdev)) {
584bae6b562SAlex Deucher 		if (rdev->pm.active_crtcs & (1 << 0)) {
585539d2418SAlex Deucher 			vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
586539d2418SAlex Deucher 			position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
587bae6b562SAlex Deucher 		}
588bae6b562SAlex Deucher 		if (rdev->pm.active_crtcs & (1 << 1)) {
589539d2418SAlex Deucher 			vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
590539d2418SAlex Deucher 			position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
591bae6b562SAlex Deucher 		}
592539d2418SAlex Deucher 		if (position < vbl && position > 1)
593539d2418SAlex Deucher 			in_vbl = false;
594bae6b562SAlex Deucher 	} else {
595bae6b562SAlex Deucher 		if (rdev->pm.active_crtcs & (1 << 0)) {
596bae6b562SAlex Deucher 			stat_crtc = RREG32(RADEON_CRTC_STATUS);
597bae6b562SAlex Deucher 			if (!(stat_crtc & 1))
598bae6b562SAlex Deucher 				in_vbl = false;
599bae6b562SAlex Deucher 		}
600bae6b562SAlex Deucher 		if (rdev->pm.active_crtcs & (1 << 1)) {
601bae6b562SAlex Deucher 			stat_crtc = RREG32(RADEON_CRTC2_STATUS);
602bae6b562SAlex Deucher 			if (!(stat_crtc & 1))
603f735261bSDave Airlie 				in_vbl = false;
604f735261bSDave Airlie 		}
605f735261bSDave Airlie 	}
606f81f2024SMatthew Garrett 
607539d2418SAlex Deucher 	if (position < vbl && position > 1)
608539d2418SAlex Deucher 		in_vbl = false;
609539d2418SAlex Deucher 
610f81f2024SMatthew Garrett 	return in_vbl;
611f81f2024SMatthew Garrett }
612f81f2024SMatthew Garrett 
613ce8f5370SAlex Deucher static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
614f81f2024SMatthew Garrett {
615f81f2024SMatthew Garrett 	u32 stat_crtc = 0;
616f81f2024SMatthew Garrett 	bool in_vbl = radeon_pm_in_vbl(rdev);
617f81f2024SMatthew Garrett 
618f735261bSDave Airlie 	if (in_vbl == false)
619ce8a3eb2SAlex Deucher 		DRM_DEBUG("not in vbl for pm change %08x at %s\n", stat_crtc,
620bae6b562SAlex Deucher 			 finish ? "exit" : "entry");
621f735261bSDave Airlie 	return in_vbl;
622f735261bSDave Airlie }
623c913e23aSRafał Miłecki 
624ce8f5370SAlex Deucher static void radeon_dynpm_idle_work_handler(struct work_struct *work)
625c913e23aSRafał Miłecki {
626c913e23aSRafał Miłecki 	struct radeon_device *rdev;
627d9932a32SMatthew Garrett 	int resched;
628c913e23aSRafał Miłecki 	rdev = container_of(work, struct radeon_device,
629ce8f5370SAlex Deucher 				pm.dynpm_idle_work.work);
630c913e23aSRafał Miłecki 
631d9932a32SMatthew Garrett 	resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
632c913e23aSRafał Miłecki 	mutex_lock(&rdev->pm.mutex);
633ce8f5370SAlex Deucher 	if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
634c913e23aSRafał Miłecki 		unsigned long irq_flags;
635c913e23aSRafał Miłecki 		int not_processed = 0;
636c913e23aSRafał Miłecki 
637c913e23aSRafał Miłecki 		read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
638c913e23aSRafał Miłecki 		if (!list_empty(&rdev->fence_drv.emited)) {
639c913e23aSRafał Miłecki 			struct list_head *ptr;
640c913e23aSRafał Miłecki 			list_for_each(ptr, &rdev->fence_drv.emited) {
641c913e23aSRafał Miłecki 				/* count up to 3, that's enought info */
642c913e23aSRafał Miłecki 				if (++not_processed >= 3)
643c913e23aSRafał Miłecki 					break;
644c913e23aSRafał Miłecki 			}
645c913e23aSRafał Miłecki 		}
646c913e23aSRafał Miłecki 		read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
647c913e23aSRafał Miłecki 
648c913e23aSRafał Miłecki 		if (not_processed >= 3) { /* should upclock */
649ce8f5370SAlex Deucher 			if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
650ce8f5370SAlex Deucher 				rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
651ce8f5370SAlex Deucher 			} else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
652ce8f5370SAlex Deucher 				   rdev->pm.dynpm_can_upclock) {
653ce8f5370SAlex Deucher 				rdev->pm.dynpm_planned_action =
654ce8f5370SAlex Deucher 					DYNPM_ACTION_UPCLOCK;
655ce8f5370SAlex Deucher 				rdev->pm.dynpm_action_timeout = jiffies +
656c913e23aSRafał Miłecki 				msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
657c913e23aSRafał Miłecki 			}
658c913e23aSRafał Miłecki 		} else if (not_processed == 0) { /* should downclock */
659ce8f5370SAlex Deucher 			if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
660ce8f5370SAlex Deucher 				rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
661ce8f5370SAlex Deucher 			} else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
662ce8f5370SAlex Deucher 				   rdev->pm.dynpm_can_downclock) {
663ce8f5370SAlex Deucher 				rdev->pm.dynpm_planned_action =
664ce8f5370SAlex Deucher 					DYNPM_ACTION_DOWNCLOCK;
665ce8f5370SAlex Deucher 				rdev->pm.dynpm_action_timeout = jiffies +
666c913e23aSRafał Miłecki 				msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
667c913e23aSRafał Miłecki 			}
668c913e23aSRafał Miłecki 		}
669c913e23aSRafał Miłecki 
670d7311171SAlex Deucher 		/* Note, radeon_pm_set_clocks is called with static_switch set
671d7311171SAlex Deucher 		 * to false since we want to wait for vbl to avoid flicker.
672d7311171SAlex Deucher 		 */
673ce8f5370SAlex Deucher 		if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
674ce8f5370SAlex Deucher 		    jiffies > rdev->pm.dynpm_action_timeout) {
675ce8f5370SAlex Deucher 			radeon_pm_get_dynpm_state(rdev);
676ce8f5370SAlex Deucher 			radeon_pm_set_clocks(rdev);
677c913e23aSRafał Miłecki 		}
678c913e23aSRafał Miłecki 	}
679c913e23aSRafał Miłecki 	mutex_unlock(&rdev->pm.mutex);
680d9932a32SMatthew Garrett 	ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
681c913e23aSRafał Miłecki 
682ce8f5370SAlex Deucher 	queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
683c913e23aSRafał Miłecki 					msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
684c913e23aSRafał Miłecki }
685c913e23aSRafał Miłecki 
6867433874eSRafał Miłecki /*
6877433874eSRafał Miłecki  * Debugfs info
6887433874eSRafał Miłecki  */
6897433874eSRafał Miłecki #if defined(CONFIG_DEBUG_FS)
6907433874eSRafał Miłecki 
6917433874eSRafał Miłecki static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
6927433874eSRafał Miłecki {
6937433874eSRafał Miłecki 	struct drm_info_node *node = (struct drm_info_node *) m->private;
6947433874eSRafał Miłecki 	struct drm_device *dev = node->minor->dev;
6957433874eSRafał Miłecki 	struct radeon_device *rdev = dev->dev_private;
6967433874eSRafał Miłecki 
6976234077dSRafał Miłecki 	seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
6986234077dSRafał Miłecki 	seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
6996234077dSRafał Miłecki 	seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
7006234077dSRafał Miłecki 	if (rdev->asic->get_memory_clock)
7016234077dSRafał Miłecki 		seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
702*0fcbe947SRafał Miłecki 	if (rdev->pm.current_vddc)
703*0fcbe947SRafał Miłecki 		seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
704aa5120d2SRafał Miłecki 	if (rdev->asic->get_pcie_lanes)
705aa5120d2SRafał Miłecki 		seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7067433874eSRafał Miłecki 
7077433874eSRafał Miłecki 	return 0;
7087433874eSRafał Miłecki }
7097433874eSRafał Miłecki 
7107433874eSRafał Miłecki static struct drm_info_list radeon_pm_info_list[] = {
7117433874eSRafał Miłecki 	{"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
7127433874eSRafał Miłecki };
7137433874eSRafał Miłecki #endif
7147433874eSRafał Miłecki 
715c913e23aSRafał Miłecki static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7167433874eSRafał Miłecki {
7177433874eSRafał Miłecki #if defined(CONFIG_DEBUG_FS)
7187433874eSRafał Miłecki 	return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
7197433874eSRafał Miłecki #else
7207433874eSRafał Miłecki 	return 0;
7217433874eSRafał Miłecki #endif
7227433874eSRafał Miłecki }
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