1771fe6b9SJerome Glisse /* 2771fe6b9SJerome Glisse * Copyright 2007-8 Advanced Micro Devices, Inc. 3771fe6b9SJerome Glisse * Copyright 2008 Red Hat Inc. 4771fe6b9SJerome Glisse * 5771fe6b9SJerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 6771fe6b9SJerome Glisse * copy of this software and associated documentation files (the "Software"), 7771fe6b9SJerome Glisse * to deal in the Software without restriction, including without limitation 8771fe6b9SJerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9771fe6b9SJerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 10771fe6b9SJerome Glisse * Software is furnished to do so, subject to the following conditions: 11771fe6b9SJerome Glisse * 12771fe6b9SJerome Glisse * The above copyright notice and this permission notice shall be included in 13771fe6b9SJerome Glisse * all copies or substantial portions of the Software. 14771fe6b9SJerome Glisse * 15771fe6b9SJerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16771fe6b9SJerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17771fe6b9SJerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18771fe6b9SJerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19771fe6b9SJerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20771fe6b9SJerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21771fe6b9SJerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 22771fe6b9SJerome Glisse * 23771fe6b9SJerome Glisse * Authors: Dave Airlie 24771fe6b9SJerome Glisse * Alex Deucher 25771fe6b9SJerome Glisse */ 26f9183127SSam Ravnborg 272ef79416SThomas Zimmermann #include <linux/pci.h> 282ef79416SThomas Zimmermann 29f9183127SSam Ravnborg #include <drm/drm_device.h> 30760285e7SDavid Howells #include <drm/radeon_drm.h> 31f9183127SSam Ravnborg 325e0e33f9SHans de Goede #include <acpi/video.h> 335e0e33f9SHans de Goede 34771fe6b9SJerome Glisse #include "radeon.h" 3564a6f8c9SLee Jones #include "radeon_atombios.h" 361ae79be1SLee Jones #include "radeon_legacy_encoders.h" 37771fe6b9SJerome Glisse #include "atom.h" 38771fe6b9SJerome Glisse 391f3b6a45SDave Airlie static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) 401f3b6a45SDave Airlie { 411f3b6a45SDave Airlie struct drm_device *dev = encoder->dev; 421f3b6a45SDave Airlie struct radeon_device *rdev = dev->dev_private; 431f3b6a45SDave Airlie struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 441f3b6a45SDave Airlie struct drm_encoder *clone_encoder; 451f3b6a45SDave Airlie uint32_t index_mask = 0; 461f3b6a45SDave Airlie int count; 471f3b6a45SDave Airlie 481f3b6a45SDave Airlie /* DIG routing gets problematic */ 491f3b6a45SDave Airlie if (rdev->family >= CHIP_R600) 501f3b6a45SDave Airlie return index_mask; 511f3b6a45SDave Airlie /* LVDS/TV are too wacky */ 521f3b6a45SDave Airlie if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 531f3b6a45SDave Airlie return index_mask; 541f3b6a45SDave Airlie /* DVO requires 2x ppll clocks depending on tmds chip */ 551f3b6a45SDave Airlie if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) 561f3b6a45SDave Airlie return index_mask; 571f3b6a45SDave Airlie 581f3b6a45SDave Airlie count = -1; 591f3b6a45SDave Airlie list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) { 601f3b6a45SDave Airlie struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder); 61*8eb94c9bSSrinivasan Shanmugam 621f3b6a45SDave Airlie count++; 631f3b6a45SDave Airlie 641f3b6a45SDave Airlie if (clone_encoder == encoder) 651f3b6a45SDave Airlie continue; 661f3b6a45SDave Airlie if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT)) 671f3b6a45SDave Airlie continue; 681f3b6a45SDave Airlie if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT) 691f3b6a45SDave Airlie continue; 701f3b6a45SDave Airlie else 711f3b6a45SDave Airlie index_mask |= (1 << count); 721f3b6a45SDave Airlie } 731f3b6a45SDave Airlie return index_mask; 741f3b6a45SDave Airlie } 751f3b6a45SDave Airlie 761f3b6a45SDave Airlie void radeon_setup_encoder_clones(struct drm_device *dev) 771f3b6a45SDave Airlie { 781f3b6a45SDave Airlie struct drm_encoder *encoder; 791f3b6a45SDave Airlie 801f3b6a45SDave Airlie list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 811f3b6a45SDave Airlie encoder->possible_clones = radeon_encoder_clones(encoder); 821f3b6a45SDave Airlie } 831f3b6a45SDave Airlie } 841f3b6a45SDave Airlie 85771fe6b9SJerome Glisse uint32_t 865137ee94SAlex Deucher radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac) 87771fe6b9SJerome Glisse { 88771fe6b9SJerome Glisse struct radeon_device *rdev = dev->dev_private; 89771fe6b9SJerome Glisse uint32_t ret = 0; 90771fe6b9SJerome Glisse 91771fe6b9SJerome Glisse switch (supported_device) { 92771fe6b9SJerome Glisse case ATOM_DEVICE_CRT1_SUPPORT: 93771fe6b9SJerome Glisse case ATOM_DEVICE_TV1_SUPPORT: 94771fe6b9SJerome Glisse case ATOM_DEVICE_TV2_SUPPORT: 95771fe6b9SJerome Glisse case ATOM_DEVICE_CRT2_SUPPORT: 96771fe6b9SJerome Glisse case ATOM_DEVICE_CV_SUPPORT: 97771fe6b9SJerome Glisse switch (dac) { 98771fe6b9SJerome Glisse case 1: /* dac a */ 99771fe6b9SJerome Glisse if ((rdev->family == CHIP_RS300) || 100771fe6b9SJerome Glisse (rdev->family == CHIP_RS400) || 101771fe6b9SJerome Glisse (rdev->family == CHIP_RS480)) 1025137ee94SAlex Deucher ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; 103771fe6b9SJerome Glisse else if (ASIC_IS_AVIVO(rdev)) 1045137ee94SAlex Deucher ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1; 105771fe6b9SJerome Glisse else 1065137ee94SAlex Deucher ret = ENCODER_INTERNAL_DAC1_ENUM_ID1; 107771fe6b9SJerome Glisse break; 108771fe6b9SJerome Glisse case 2: /* dac b */ 109771fe6b9SJerome Glisse if (ASIC_IS_AVIVO(rdev)) 1105137ee94SAlex Deucher ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1; 111771fe6b9SJerome Glisse else { 112771fe6b9SJerome Glisse /* if (rdev->family == CHIP_R200) 113*8eb94c9bSSrinivasan Shanmugam * ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; 114*8eb94c9bSSrinivasan Shanmugam * else 115*8eb94c9bSSrinivasan Shanmugam */ 1165137ee94SAlex Deucher ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; 117771fe6b9SJerome Glisse } 118771fe6b9SJerome Glisse break; 119771fe6b9SJerome Glisse case 3: /* external dac */ 120771fe6b9SJerome Glisse if (ASIC_IS_AVIVO(rdev)) 1215137ee94SAlex Deucher ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1; 122771fe6b9SJerome Glisse else 1235137ee94SAlex Deucher ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; 124771fe6b9SJerome Glisse break; 125771fe6b9SJerome Glisse } 126771fe6b9SJerome Glisse break; 127771fe6b9SJerome Glisse case ATOM_DEVICE_LCD1_SUPPORT: 128771fe6b9SJerome Glisse if (ASIC_IS_AVIVO(rdev)) 1295137ee94SAlex Deucher ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1; 130771fe6b9SJerome Glisse else 1315137ee94SAlex Deucher ret = ENCODER_INTERNAL_LVDS_ENUM_ID1; 132771fe6b9SJerome Glisse break; 133771fe6b9SJerome Glisse case ATOM_DEVICE_DFP1_SUPPORT: 134771fe6b9SJerome Glisse if ((rdev->family == CHIP_RS300) || 135771fe6b9SJerome Glisse (rdev->family == CHIP_RS400) || 136771fe6b9SJerome Glisse (rdev->family == CHIP_RS480)) 1375137ee94SAlex Deucher ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; 138771fe6b9SJerome Glisse else if (ASIC_IS_AVIVO(rdev)) 1395137ee94SAlex Deucher ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1; 140771fe6b9SJerome Glisse else 1415137ee94SAlex Deucher ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1; 142771fe6b9SJerome Glisse break; 143771fe6b9SJerome Glisse case ATOM_DEVICE_LCD2_SUPPORT: 144771fe6b9SJerome Glisse case ATOM_DEVICE_DFP2_SUPPORT: 145771fe6b9SJerome Glisse if ((rdev->family == CHIP_RS600) || 146771fe6b9SJerome Glisse (rdev->family == CHIP_RS690) || 147771fe6b9SJerome Glisse (rdev->family == CHIP_RS740)) 1485137ee94SAlex Deucher ret = ENCODER_INTERNAL_DDI_ENUM_ID1; 149771fe6b9SJerome Glisse else if (ASIC_IS_AVIVO(rdev)) 1505137ee94SAlex Deucher ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1; 151771fe6b9SJerome Glisse else 1525137ee94SAlex Deucher ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; 153771fe6b9SJerome Glisse break; 154771fe6b9SJerome Glisse case ATOM_DEVICE_DFP3_SUPPORT: 1555137ee94SAlex Deucher ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1; 156771fe6b9SJerome Glisse break; 157771fe6b9SJerome Glisse } 158771fe6b9SJerome Glisse 159771fe6b9SJerome Glisse return ret; 160771fe6b9SJerome Glisse } 161771fe6b9SJerome Glisse 162bc13018bSAlex Deucher static void radeon_encoder_add_backlight(struct radeon_encoder *radeon_encoder, 163bc13018bSAlex Deucher struct drm_connector *connector) 164bc13018bSAlex Deucher { 165bc13018bSAlex Deucher struct drm_device *dev = radeon_encoder->base.dev; 166bc13018bSAlex Deucher struct radeon_device *rdev = dev->dev_private; 167bc13018bSAlex Deucher bool use_bl = false; 168bc13018bSAlex Deucher 169bc13018bSAlex Deucher if (!(radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))) 170bc13018bSAlex Deucher return; 171bc13018bSAlex Deucher 172bc13018bSAlex Deucher if (radeon_backlight == 0) { 1735e0e33f9SHans de Goede use_bl = false; 174bc13018bSAlex Deucher } else if (radeon_backlight == 1) { 175bc13018bSAlex Deucher use_bl = true; 176bc13018bSAlex Deucher } else if (radeon_backlight == -1) { 1778aff6ad5SAlex Deucher /* Quirks */ 1788aff6ad5SAlex Deucher /* Amilo Xi 2550 only works with acpi bl */ 1798aff6ad5SAlex Deucher if ((rdev->pdev->device == 0x9583) && 1808aff6ad5SAlex Deucher (rdev->pdev->subsystem_vendor == 0x1734) && 1818aff6ad5SAlex Deucher (rdev->pdev->subsystem_device == 0x1107)) 1828aff6ad5SAlex Deucher use_bl = false; 1837a26f9adSNathan-J. Hirschauer /* Older PPC macs use on-GPU backlight controller */ 1847a26f9adSNathan-J. Hirschauer #ifndef CONFIG_PPC_PMAC 185b7bc596eSAlex Deucher /* disable native backlight control on older asics */ 186b7bc596eSAlex Deucher else if (rdev->family < CHIP_R600) 187b7bc596eSAlex Deucher use_bl = false; 1887a26f9adSNathan-J. Hirschauer #endif 1898aff6ad5SAlex Deucher else 190bc13018bSAlex Deucher use_bl = true; 191bc13018bSAlex Deucher } 192bc13018bSAlex Deucher 193bc13018bSAlex Deucher if (use_bl) { 194bc13018bSAlex Deucher if (rdev->is_atom_bios) 195bc13018bSAlex Deucher radeon_atom_backlight_init(radeon_encoder, connector); 196bc13018bSAlex Deucher else 197bc13018bSAlex Deucher radeon_legacy_backlight_init(radeon_encoder, connector); 198bc13018bSAlex Deucher } 1995e0e33f9SHans de Goede 2005e0e33f9SHans de Goede /* 2015e0e33f9SHans de Goede * If there is no native backlight device (which may happen even when 2025e0e33f9SHans de Goede * use_bl==true) try registering an ACPI video backlight device instead. 2035e0e33f9SHans de Goede */ 2045e0e33f9SHans de Goede if (!rdev->mode_info.bl_encoder) 2055e0e33f9SHans de Goede acpi_video_register_backlight(); 206bc13018bSAlex Deucher } 207bc13018bSAlex Deucher 208771fe6b9SJerome Glisse void 209771fe6b9SJerome Glisse radeon_link_encoder_connector(struct drm_device *dev) 210771fe6b9SJerome Glisse { 211771fe6b9SJerome Glisse struct drm_connector *connector; 212771fe6b9SJerome Glisse struct radeon_connector *radeon_connector; 213771fe6b9SJerome Glisse struct drm_encoder *encoder; 214771fe6b9SJerome Glisse struct radeon_encoder *radeon_encoder; 215771fe6b9SJerome Glisse 216771fe6b9SJerome Glisse /* walk the list and link encoders to connectors */ 217771fe6b9SJerome Glisse list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 218771fe6b9SJerome Glisse radeon_connector = to_radeon_connector(connector); 219771fe6b9SJerome Glisse list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 220771fe6b9SJerome Glisse radeon_encoder = to_radeon_encoder(encoder); 221f3728734SAlex Deucher if (radeon_encoder->devices & radeon_connector->devices) { 222cde4c44dSDaniel Vetter drm_connector_attach_encoder(connector, encoder); 223bc13018bSAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 224bc13018bSAlex Deucher radeon_encoder_add_backlight(radeon_encoder, connector); 225f3728734SAlex Deucher } 226771fe6b9SJerome Glisse } 227771fe6b9SJerome Glisse } 228771fe6b9SJerome Glisse } 229771fe6b9SJerome Glisse 2304ce001abSDave Airlie void radeon_encoder_set_active_device(struct drm_encoder *encoder) 2314ce001abSDave Airlie { 2324ce001abSDave Airlie struct drm_device *dev = encoder->dev; 2334ce001abSDave Airlie struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2344ce001abSDave Airlie struct drm_connector *connector; 2354ce001abSDave Airlie 2364ce001abSDave Airlie list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 2374ce001abSDave Airlie if (connector->encoder == encoder) { 2384ce001abSDave Airlie struct radeon_connector *radeon_connector = to_radeon_connector(connector); 239*8eb94c9bSSrinivasan Shanmugam 2404ce001abSDave Airlie radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; 241d9fdaafbSDave Airlie DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", 2424ce001abSDave Airlie radeon_encoder->active_device, radeon_encoder->devices, 2434ce001abSDave Airlie radeon_connector->devices, encoder->encoder_type); 2444ce001abSDave Airlie } 2454ce001abSDave Airlie } 2464ce001abSDave Airlie } 2474ce001abSDave Airlie 2485b1714d3SAlex Deucher struct drm_connector * 249771fe6b9SJerome Glisse radeon_get_connector_for_encoder(struct drm_encoder *encoder) 250771fe6b9SJerome Glisse { 251771fe6b9SJerome Glisse struct drm_device *dev = encoder->dev; 252771fe6b9SJerome Glisse struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 253771fe6b9SJerome Glisse struct drm_connector *connector; 254771fe6b9SJerome Glisse struct radeon_connector *radeon_connector; 255771fe6b9SJerome Glisse 256771fe6b9SJerome Glisse list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 257771fe6b9SJerome Glisse radeon_connector = to_radeon_connector(connector); 25801ad1d9cSLyude Paul if (radeon_encoder->active_device & radeon_connector->devices) 259771fe6b9SJerome Glisse return connector; 260771fe6b9SJerome Glisse } 261771fe6b9SJerome Glisse return NULL; 262771fe6b9SJerome Glisse } 263771fe6b9SJerome Glisse 2649aa59993SAlex Deucher struct drm_connector * 2659aa59993SAlex Deucher radeon_get_connector_for_encoder_init(struct drm_encoder *encoder) 2669aa59993SAlex Deucher { 2679aa59993SAlex Deucher struct drm_device *dev = encoder->dev; 2689aa59993SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2699aa59993SAlex Deucher struct drm_connector *connector; 2709aa59993SAlex Deucher struct radeon_connector *radeon_connector; 2719aa59993SAlex Deucher 2729aa59993SAlex Deucher list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 2739aa59993SAlex Deucher radeon_connector = to_radeon_connector(connector); 2749aa59993SAlex Deucher if (radeon_encoder->devices & radeon_connector->devices) 2759aa59993SAlex Deucher return connector; 2769aa59993SAlex Deucher } 2779aa59993SAlex Deucher return NULL; 2789aa59993SAlex Deucher } 2799aa59993SAlex Deucher 2803f03ced8SAlex Deucher struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder) 2813e4b9982SAlex Deucher { 2823e4b9982SAlex Deucher struct drm_device *dev = encoder->dev; 2833e4b9982SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2843e4b9982SAlex Deucher struct drm_encoder *other_encoder; 2853e4b9982SAlex Deucher struct radeon_encoder *other_radeon_encoder; 2863e4b9982SAlex Deucher 2873e4b9982SAlex Deucher if (radeon_encoder->is_ext_encoder) 2883e4b9982SAlex Deucher return NULL; 2893e4b9982SAlex Deucher 2903e4b9982SAlex Deucher list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2913e4b9982SAlex Deucher if (other_encoder == encoder) 2923e4b9982SAlex Deucher continue; 2933e4b9982SAlex Deucher other_radeon_encoder = to_radeon_encoder(other_encoder); 2943e4b9982SAlex Deucher if (other_radeon_encoder->is_ext_encoder && 2953e4b9982SAlex Deucher (radeon_encoder->devices & other_radeon_encoder->devices)) 2963e4b9982SAlex Deucher return other_encoder; 2973e4b9982SAlex Deucher } 2983e4b9982SAlex Deucher return NULL; 2993e4b9982SAlex Deucher } 3003e4b9982SAlex Deucher 3011d33e1fcSAlex Deucher u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder) 302d7fa8bb3SAlex Deucher { 3033f03ced8SAlex Deucher struct drm_encoder *other_encoder = radeon_get_external_encoder(encoder); 304d7fa8bb3SAlex Deucher 305d7fa8bb3SAlex Deucher if (other_encoder) { 306d7fa8bb3SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder); 307d7fa8bb3SAlex Deucher 308d7fa8bb3SAlex Deucher switch (radeon_encoder->encoder_id) { 309d7fa8bb3SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS: 310d7fa8bb3SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG: 311dc87cd5cSAlex Deucher return radeon_encoder->encoder_id; 312d7fa8bb3SAlex Deucher default: 313dc87cd5cSAlex Deucher return ENCODER_OBJECT_ID_NONE; 314d7fa8bb3SAlex Deucher } 315d7fa8bb3SAlex Deucher } 316dc87cd5cSAlex Deucher return ENCODER_OBJECT_ID_NONE; 317d7fa8bb3SAlex Deucher } 318d7fa8bb3SAlex Deucher 3193515387bSAlex Deucher void radeon_panel_mode_fixup(struct drm_encoder *encoder, 3203515387bSAlex Deucher struct drm_display_mode *adjusted_mode) 3213515387bSAlex Deucher { 3223515387bSAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3233515387bSAlex Deucher struct drm_device *dev = encoder->dev; 3243515387bSAlex Deucher struct radeon_device *rdev = dev->dev_private; 3253515387bSAlex Deucher struct drm_display_mode *native_mode = &radeon_encoder->native_mode; 326*8eb94c9bSSrinivasan Shanmugam unsigned int hblank = native_mode->htotal - native_mode->hdisplay; 327*8eb94c9bSSrinivasan Shanmugam unsigned int vblank = native_mode->vtotal - native_mode->vdisplay; 328*8eb94c9bSSrinivasan Shanmugam unsigned int hover = native_mode->hsync_start - native_mode->hdisplay; 329*8eb94c9bSSrinivasan Shanmugam unsigned int vover = native_mode->vsync_start - native_mode->vdisplay; 330*8eb94c9bSSrinivasan Shanmugam unsigned int hsync_width = native_mode->hsync_end - native_mode->hsync_start; 331*8eb94c9bSSrinivasan Shanmugam unsigned int vsync_width = native_mode->vsync_end - native_mode->vsync_start; 3323515387bSAlex Deucher 3333515387bSAlex Deucher adjusted_mode->clock = native_mode->clock; 3343515387bSAlex Deucher adjusted_mode->flags = native_mode->flags; 3353515387bSAlex Deucher 3363515387bSAlex Deucher if (ASIC_IS_AVIVO(rdev)) { 3373515387bSAlex Deucher adjusted_mode->hdisplay = native_mode->hdisplay; 3383515387bSAlex Deucher adjusted_mode->vdisplay = native_mode->vdisplay; 3393515387bSAlex Deucher } 3403515387bSAlex Deucher 3413515387bSAlex Deucher adjusted_mode->htotal = native_mode->hdisplay + hblank; 3423515387bSAlex Deucher adjusted_mode->hsync_start = native_mode->hdisplay + hover; 3433515387bSAlex Deucher adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; 3443515387bSAlex Deucher 3453515387bSAlex Deucher adjusted_mode->vtotal = native_mode->vdisplay + vblank; 3463515387bSAlex Deucher adjusted_mode->vsync_start = native_mode->vdisplay + vover; 3473515387bSAlex Deucher adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width; 3483515387bSAlex Deucher 3493515387bSAlex Deucher drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); 3503515387bSAlex Deucher 3513515387bSAlex Deucher if (ASIC_IS_AVIVO(rdev)) { 3523515387bSAlex Deucher adjusted_mode->crtc_hdisplay = native_mode->hdisplay; 3533515387bSAlex Deucher adjusted_mode->crtc_vdisplay = native_mode->vdisplay; 3543515387bSAlex Deucher } 3553515387bSAlex Deucher 3563515387bSAlex Deucher adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank; 3573515387bSAlex Deucher adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover; 3583515387bSAlex Deucher adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width; 3593515387bSAlex Deucher 3603515387bSAlex Deucher adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank; 3613515387bSAlex Deucher adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover; 3623515387bSAlex Deucher adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width; 3633515387bSAlex Deucher 3643515387bSAlex Deucher } 3653515387bSAlex Deucher 3669aa59993SAlex Deucher bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 3679aa59993SAlex Deucher u32 pixel_clock) 3689aa59993SAlex Deucher { 3691b2681baSAlex Deucher struct drm_device *dev = encoder->dev; 3701b2681baSAlex Deucher struct radeon_device *rdev = dev->dev_private; 3719aa59993SAlex Deucher struct drm_connector *connector; 3729aa59993SAlex Deucher struct radeon_connector *radeon_connector; 3739aa59993SAlex Deucher struct radeon_connector_atom_dig *dig_connector; 3749aa59993SAlex Deucher 3759aa59993SAlex Deucher connector = radeon_get_connector_for_encoder(encoder); 3769aa59993SAlex Deucher /* if we don't have an active device yet, just use one of 3779aa59993SAlex Deucher * the connectors tied to the encoder. 3789aa59993SAlex Deucher */ 3799aa59993SAlex Deucher if (!connector) 3809aa59993SAlex Deucher connector = radeon_get_connector_for_encoder_init(encoder); 3819aa59993SAlex Deucher radeon_connector = to_radeon_connector(connector); 3829aa59993SAlex Deucher 3839aa59993SAlex Deucher switch (connector->connector_type) { 3849aa59993SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 3859aa59993SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: 3869aa59993SAlex Deucher if (radeon_connector->use_digital) { 3879aa59993SAlex Deucher /* HDMI 1.3 supports up to 340 Mhz over single link */ 388377bd8a9SAlex Deucher if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector_edid(connector))) { 3899aa59993SAlex Deucher if (pixel_clock > 340000) 3909aa59993SAlex Deucher return true; 3919aa59993SAlex Deucher else 3929aa59993SAlex Deucher return false; 3939aa59993SAlex Deucher } else { 3949aa59993SAlex Deucher if (pixel_clock > 165000) 3959aa59993SAlex Deucher return true; 3969aa59993SAlex Deucher else 3979aa59993SAlex Deucher return false; 3989aa59993SAlex Deucher } 3999aa59993SAlex Deucher } else 4009aa59993SAlex Deucher return false; 4019aa59993SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 4029aa59993SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 4039aa59993SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 4049aa59993SAlex Deucher dig_connector = radeon_connector->con_priv; 4059aa59993SAlex Deucher if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 4069aa59993SAlex Deucher (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 4079aa59993SAlex Deucher return false; 4089aa59993SAlex Deucher else { 4099aa59993SAlex Deucher /* HDMI 1.3 supports up to 340 Mhz over single link */ 410377bd8a9SAlex Deucher if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector_edid(connector))) { 4119aa59993SAlex Deucher if (pixel_clock > 340000) 4129aa59993SAlex Deucher return true; 4139aa59993SAlex Deucher else 4149aa59993SAlex Deucher return false; 4159aa59993SAlex Deucher } else { 4169aa59993SAlex Deucher if (pixel_clock > 165000) 4179aa59993SAlex Deucher return true; 4189aa59993SAlex Deucher else 4199aa59993SAlex Deucher return false; 4209aa59993SAlex Deucher } 4219aa59993SAlex Deucher } 4229aa59993SAlex Deucher default: 4239aa59993SAlex Deucher return false; 4249aa59993SAlex Deucher } 4259aa59993SAlex Deucher } 4269aa59993SAlex Deucher 427d740a933SAlex Deucher bool radeon_encoder_is_digital(struct drm_encoder *encoder) 428d740a933SAlex Deucher { 429d740a933SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 430*8eb94c9bSSrinivasan Shanmugam 431d740a933SAlex Deucher switch (radeon_encoder->encoder_id) { 432d740a933SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVDS: 433d740a933SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 434d740a933SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 435d740a933SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 436d740a933SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DVO1: 437d740a933SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 438d740a933SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DDI: 439d740a933SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 440d740a933SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 441d740a933SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 442d740a933SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 443d740a933SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 444d740a933SAlex Deucher return true; 445d740a933SAlex Deucher default: 446d740a933SAlex Deucher return false; 447d740a933SAlex Deucher } 448d740a933SAlex Deucher } 449