xref: /openbmc/linux/drivers/gpu/drm/radeon/radeon_encoders.c (revision 64a6f8c91071c6e09ff3152916823e4d45801d28)
1771fe6b9SJerome Glisse /*
2771fe6b9SJerome Glisse  * Copyright 2007-8 Advanced Micro Devices, Inc.
3771fe6b9SJerome Glisse  * Copyright 2008 Red Hat Inc.
4771fe6b9SJerome Glisse  *
5771fe6b9SJerome Glisse  * Permission is hereby granted, free of charge, to any person obtaining a
6771fe6b9SJerome Glisse  * copy of this software and associated documentation files (the "Software"),
7771fe6b9SJerome Glisse  * to deal in the Software without restriction, including without limitation
8771fe6b9SJerome Glisse  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9771fe6b9SJerome Glisse  * and/or sell copies of the Software, and to permit persons to whom the
10771fe6b9SJerome Glisse  * Software is furnished to do so, subject to the following conditions:
11771fe6b9SJerome Glisse  *
12771fe6b9SJerome Glisse  * The above copyright notice and this permission notice shall be included in
13771fe6b9SJerome Glisse  * all copies or substantial portions of the Software.
14771fe6b9SJerome Glisse  *
15771fe6b9SJerome Glisse  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16771fe6b9SJerome Glisse  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17771fe6b9SJerome Glisse  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18771fe6b9SJerome Glisse  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19771fe6b9SJerome Glisse  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20771fe6b9SJerome Glisse  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21771fe6b9SJerome Glisse  * OTHER DEALINGS IN THE SOFTWARE.
22771fe6b9SJerome Glisse  *
23771fe6b9SJerome Glisse  * Authors: Dave Airlie
24771fe6b9SJerome Glisse  *          Alex Deucher
25771fe6b9SJerome Glisse  */
26f9183127SSam Ravnborg 
272ef79416SThomas Zimmermann #include <linux/pci.h>
282ef79416SThomas Zimmermann 
29760285e7SDavid Howells #include <drm/drm_crtc_helper.h>
30f9183127SSam Ravnborg #include <drm/drm_device.h>
31760285e7SDavid Howells #include <drm/radeon_drm.h>
32f9183127SSam Ravnborg 
33771fe6b9SJerome Glisse #include "radeon.h"
34*64a6f8c9SLee Jones #include "radeon_atombios.h"
351ae79be1SLee Jones #include "radeon_legacy_encoders.h"
36771fe6b9SJerome Glisse #include "atom.h"
37771fe6b9SJerome Glisse 
381f3b6a45SDave Airlie static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
391f3b6a45SDave Airlie {
401f3b6a45SDave Airlie 	struct drm_device *dev = encoder->dev;
411f3b6a45SDave Airlie 	struct radeon_device *rdev = dev->dev_private;
421f3b6a45SDave Airlie 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
431f3b6a45SDave Airlie 	struct drm_encoder *clone_encoder;
441f3b6a45SDave Airlie 	uint32_t index_mask = 0;
451f3b6a45SDave Airlie 	int count;
461f3b6a45SDave Airlie 
471f3b6a45SDave Airlie 	/* DIG routing gets problematic */
481f3b6a45SDave Airlie 	if (rdev->family >= CHIP_R600)
491f3b6a45SDave Airlie 		return index_mask;
501f3b6a45SDave Airlie 	/* LVDS/TV are too wacky */
511f3b6a45SDave Airlie 	if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
521f3b6a45SDave Airlie 		return index_mask;
531f3b6a45SDave Airlie 	/* DVO requires 2x ppll clocks depending on tmds chip */
541f3b6a45SDave Airlie 	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
551f3b6a45SDave Airlie 		return index_mask;
561f3b6a45SDave Airlie 
571f3b6a45SDave Airlie 	count = -1;
581f3b6a45SDave Airlie 	list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
591f3b6a45SDave Airlie 		struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
601f3b6a45SDave Airlie 		count++;
611f3b6a45SDave Airlie 
621f3b6a45SDave Airlie 		if (clone_encoder == encoder)
631f3b6a45SDave Airlie 			continue;
641f3b6a45SDave Airlie 		if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
651f3b6a45SDave Airlie 			continue;
661f3b6a45SDave Airlie 		if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
671f3b6a45SDave Airlie 			continue;
681f3b6a45SDave Airlie 		else
691f3b6a45SDave Airlie 			index_mask |= (1 << count);
701f3b6a45SDave Airlie 	}
711f3b6a45SDave Airlie 	return index_mask;
721f3b6a45SDave Airlie }
731f3b6a45SDave Airlie 
741f3b6a45SDave Airlie void radeon_setup_encoder_clones(struct drm_device *dev)
751f3b6a45SDave Airlie {
761f3b6a45SDave Airlie 	struct drm_encoder *encoder;
771f3b6a45SDave Airlie 
781f3b6a45SDave Airlie 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
791f3b6a45SDave Airlie 		encoder->possible_clones = radeon_encoder_clones(encoder);
801f3b6a45SDave Airlie 	}
811f3b6a45SDave Airlie }
821f3b6a45SDave Airlie 
83771fe6b9SJerome Glisse uint32_t
845137ee94SAlex Deucher radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
85771fe6b9SJerome Glisse {
86771fe6b9SJerome Glisse 	struct radeon_device *rdev = dev->dev_private;
87771fe6b9SJerome Glisse 	uint32_t ret = 0;
88771fe6b9SJerome Glisse 
89771fe6b9SJerome Glisse 	switch (supported_device) {
90771fe6b9SJerome Glisse 	case ATOM_DEVICE_CRT1_SUPPORT:
91771fe6b9SJerome Glisse 	case ATOM_DEVICE_TV1_SUPPORT:
92771fe6b9SJerome Glisse 	case ATOM_DEVICE_TV2_SUPPORT:
93771fe6b9SJerome Glisse 	case ATOM_DEVICE_CRT2_SUPPORT:
94771fe6b9SJerome Glisse 	case ATOM_DEVICE_CV_SUPPORT:
95771fe6b9SJerome Glisse 		switch (dac) {
96771fe6b9SJerome Glisse 		case 1: /* dac a */
97771fe6b9SJerome Glisse 			if ((rdev->family == CHIP_RS300) ||
98771fe6b9SJerome Glisse 			    (rdev->family == CHIP_RS400) ||
99771fe6b9SJerome Glisse 			    (rdev->family == CHIP_RS480))
1005137ee94SAlex Deucher 				ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
101771fe6b9SJerome Glisse 			else if (ASIC_IS_AVIVO(rdev))
1025137ee94SAlex Deucher 				ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
103771fe6b9SJerome Glisse 			else
1045137ee94SAlex Deucher 				ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
105771fe6b9SJerome Glisse 			break;
106771fe6b9SJerome Glisse 		case 2: /* dac b */
107771fe6b9SJerome Glisse 			if (ASIC_IS_AVIVO(rdev))
1085137ee94SAlex Deucher 				ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
109771fe6b9SJerome Glisse 			else {
110771fe6b9SJerome Glisse 				/*if (rdev->family == CHIP_R200)
1115137ee94SAlex Deucher 				  ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
112771fe6b9SJerome Glisse 				  else*/
1135137ee94SAlex Deucher 				ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
114771fe6b9SJerome Glisse 			}
115771fe6b9SJerome Glisse 			break;
116771fe6b9SJerome Glisse 		case 3: /* external dac */
117771fe6b9SJerome Glisse 			if (ASIC_IS_AVIVO(rdev))
1185137ee94SAlex Deucher 				ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
119771fe6b9SJerome Glisse 			else
1205137ee94SAlex Deucher 				ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
121771fe6b9SJerome Glisse 			break;
122771fe6b9SJerome Glisse 		}
123771fe6b9SJerome Glisse 		break;
124771fe6b9SJerome Glisse 	case ATOM_DEVICE_LCD1_SUPPORT:
125771fe6b9SJerome Glisse 		if (ASIC_IS_AVIVO(rdev))
1265137ee94SAlex Deucher 			ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
127771fe6b9SJerome Glisse 		else
1285137ee94SAlex Deucher 			ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
129771fe6b9SJerome Glisse 		break;
130771fe6b9SJerome Glisse 	case ATOM_DEVICE_DFP1_SUPPORT:
131771fe6b9SJerome Glisse 		if ((rdev->family == CHIP_RS300) ||
132771fe6b9SJerome Glisse 		    (rdev->family == CHIP_RS400) ||
133771fe6b9SJerome Glisse 		    (rdev->family == CHIP_RS480))
1345137ee94SAlex Deucher 			ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
135771fe6b9SJerome Glisse 		else if (ASIC_IS_AVIVO(rdev))
1365137ee94SAlex Deucher 			ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
137771fe6b9SJerome Glisse 		else
1385137ee94SAlex Deucher 			ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
139771fe6b9SJerome Glisse 		break;
140771fe6b9SJerome Glisse 	case ATOM_DEVICE_LCD2_SUPPORT:
141771fe6b9SJerome Glisse 	case ATOM_DEVICE_DFP2_SUPPORT:
142771fe6b9SJerome Glisse 		if ((rdev->family == CHIP_RS600) ||
143771fe6b9SJerome Glisse 		    (rdev->family == CHIP_RS690) ||
144771fe6b9SJerome Glisse 		    (rdev->family == CHIP_RS740))
1455137ee94SAlex Deucher 			ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
146771fe6b9SJerome Glisse 		else if (ASIC_IS_AVIVO(rdev))
1475137ee94SAlex Deucher 			ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
148771fe6b9SJerome Glisse 		else
1495137ee94SAlex Deucher 			ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
150771fe6b9SJerome Glisse 		break;
151771fe6b9SJerome Glisse 	case ATOM_DEVICE_DFP3_SUPPORT:
1525137ee94SAlex Deucher 		ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
153771fe6b9SJerome Glisse 		break;
154771fe6b9SJerome Glisse 	}
155771fe6b9SJerome Glisse 
156771fe6b9SJerome Glisse 	return ret;
157771fe6b9SJerome Glisse }
158771fe6b9SJerome Glisse 
159bc13018bSAlex Deucher static void radeon_encoder_add_backlight(struct radeon_encoder *radeon_encoder,
160bc13018bSAlex Deucher 					 struct drm_connector *connector)
161bc13018bSAlex Deucher {
162bc13018bSAlex Deucher 	struct drm_device *dev = radeon_encoder->base.dev;
163bc13018bSAlex Deucher 	struct radeon_device *rdev = dev->dev_private;
164bc13018bSAlex Deucher 	bool use_bl = false;
165bc13018bSAlex Deucher 
166bc13018bSAlex Deucher 	if (!(radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)))
167bc13018bSAlex Deucher 		return;
168bc13018bSAlex Deucher 
169bc13018bSAlex Deucher 	if (radeon_backlight == 0) {
170bc13018bSAlex Deucher 		return;
171bc13018bSAlex Deucher 	} else if (radeon_backlight == 1) {
172bc13018bSAlex Deucher 		use_bl = true;
173bc13018bSAlex Deucher 	} else if (radeon_backlight == -1) {
1748aff6ad5SAlex Deucher 		/* Quirks */
1758aff6ad5SAlex Deucher 		/* Amilo Xi 2550 only works with acpi bl */
1768aff6ad5SAlex Deucher 		if ((rdev->pdev->device == 0x9583) &&
1778aff6ad5SAlex Deucher 		    (rdev->pdev->subsystem_vendor == 0x1734) &&
1788aff6ad5SAlex Deucher 		    (rdev->pdev->subsystem_device == 0x1107))
1798aff6ad5SAlex Deucher 			use_bl = false;
1807a26f9adSNathan-J. Hirschauer /* Older PPC macs use on-GPU backlight controller */
1817a26f9adSNathan-J. Hirschauer #ifndef CONFIG_PPC_PMAC
182b7bc596eSAlex Deucher 		/* disable native backlight control on older asics */
183b7bc596eSAlex Deucher 		else if (rdev->family < CHIP_R600)
184b7bc596eSAlex Deucher 			use_bl = false;
1857a26f9adSNathan-J. Hirschauer #endif
1868aff6ad5SAlex Deucher 		else
187bc13018bSAlex Deucher 			use_bl = true;
188bc13018bSAlex Deucher 	}
189bc13018bSAlex Deucher 
190bc13018bSAlex Deucher 	if (use_bl) {
191bc13018bSAlex Deucher 		if (rdev->is_atom_bios)
192bc13018bSAlex Deucher 			radeon_atom_backlight_init(radeon_encoder, connector);
193bc13018bSAlex Deucher 		else
194bc13018bSAlex Deucher 			radeon_legacy_backlight_init(radeon_encoder, connector);
195bc13018bSAlex Deucher 	}
196bc13018bSAlex Deucher }
197bc13018bSAlex Deucher 
198771fe6b9SJerome Glisse void
199771fe6b9SJerome Glisse radeon_link_encoder_connector(struct drm_device *dev)
200771fe6b9SJerome Glisse {
201771fe6b9SJerome Glisse 	struct drm_connector *connector;
202771fe6b9SJerome Glisse 	struct radeon_connector *radeon_connector;
203771fe6b9SJerome Glisse 	struct drm_encoder *encoder;
204771fe6b9SJerome Glisse 	struct radeon_encoder *radeon_encoder;
205771fe6b9SJerome Glisse 
206771fe6b9SJerome Glisse 	/* walk the list and link encoders to connectors */
207771fe6b9SJerome Glisse 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
208771fe6b9SJerome Glisse 		radeon_connector = to_radeon_connector(connector);
209771fe6b9SJerome Glisse 		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
210771fe6b9SJerome Glisse 			radeon_encoder = to_radeon_encoder(encoder);
211f3728734SAlex Deucher 			if (radeon_encoder->devices & radeon_connector->devices) {
212cde4c44dSDaniel Vetter 				drm_connector_attach_encoder(connector, encoder);
213bc13018bSAlex Deucher 				if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
214bc13018bSAlex Deucher 					radeon_encoder_add_backlight(radeon_encoder, connector);
215f3728734SAlex Deucher 			}
216771fe6b9SJerome Glisse 		}
217771fe6b9SJerome Glisse 	}
218771fe6b9SJerome Glisse }
219771fe6b9SJerome Glisse 
2204ce001abSDave Airlie void radeon_encoder_set_active_device(struct drm_encoder *encoder)
2214ce001abSDave Airlie {
2224ce001abSDave Airlie 	struct drm_device *dev = encoder->dev;
2234ce001abSDave Airlie 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2244ce001abSDave Airlie 	struct drm_connector *connector;
2254ce001abSDave Airlie 
2264ce001abSDave Airlie 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2274ce001abSDave Airlie 		if (connector->encoder == encoder) {
2284ce001abSDave Airlie 			struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2294ce001abSDave Airlie 			radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
230d9fdaafbSDave Airlie 			DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
2314ce001abSDave Airlie 				  radeon_encoder->active_device, radeon_encoder->devices,
2324ce001abSDave Airlie 				  radeon_connector->devices, encoder->encoder_type);
2334ce001abSDave Airlie 		}
2344ce001abSDave Airlie 	}
2354ce001abSDave Airlie }
2364ce001abSDave Airlie 
2375b1714d3SAlex Deucher struct drm_connector *
238771fe6b9SJerome Glisse radeon_get_connector_for_encoder(struct drm_encoder *encoder)
239771fe6b9SJerome Glisse {
240771fe6b9SJerome Glisse 	struct drm_device *dev = encoder->dev;
241771fe6b9SJerome Glisse 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
242771fe6b9SJerome Glisse 	struct drm_connector *connector;
243771fe6b9SJerome Glisse 	struct radeon_connector *radeon_connector;
244771fe6b9SJerome Glisse 
245771fe6b9SJerome Glisse 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
246771fe6b9SJerome Glisse 		radeon_connector = to_radeon_connector(connector);
2479843ead0SDave Airlie 		if (radeon_encoder->is_mst_encoder) {
2489843ead0SDave Airlie 			struct radeon_encoder_mst *mst_enc;
2499843ead0SDave Airlie 
2509843ead0SDave Airlie 			if (!radeon_connector->is_mst_connector)
2519843ead0SDave Airlie 				continue;
2529843ead0SDave Airlie 
2539843ead0SDave Airlie 			mst_enc = radeon_encoder->enc_priv;
2549843ead0SDave Airlie 			if (mst_enc->connector == radeon_connector->mst_port)
2559843ead0SDave Airlie 				return connector;
2569843ead0SDave Airlie 		} else if (radeon_encoder->active_device & radeon_connector->devices)
257771fe6b9SJerome Glisse 			return connector;
258771fe6b9SJerome Glisse 	}
259771fe6b9SJerome Glisse 	return NULL;
260771fe6b9SJerome Glisse }
261771fe6b9SJerome Glisse 
2629aa59993SAlex Deucher struct drm_connector *
2639aa59993SAlex Deucher radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
2649aa59993SAlex Deucher {
2659aa59993SAlex Deucher 	struct drm_device *dev = encoder->dev;
2669aa59993SAlex Deucher 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2679aa59993SAlex Deucher 	struct drm_connector *connector;
2689aa59993SAlex Deucher 	struct radeon_connector *radeon_connector;
2699aa59993SAlex Deucher 
2709aa59993SAlex Deucher 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2719aa59993SAlex Deucher 		radeon_connector = to_radeon_connector(connector);
2729aa59993SAlex Deucher 		if (radeon_encoder->devices & radeon_connector->devices)
2739aa59993SAlex Deucher 			return connector;
2749aa59993SAlex Deucher 	}
2759aa59993SAlex Deucher 	return NULL;
2769aa59993SAlex Deucher }
2779aa59993SAlex Deucher 
2783f03ced8SAlex Deucher struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder)
2793e4b9982SAlex Deucher {
2803e4b9982SAlex Deucher 	struct drm_device *dev = encoder->dev;
2813e4b9982SAlex Deucher 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2823e4b9982SAlex Deucher 	struct drm_encoder *other_encoder;
2833e4b9982SAlex Deucher 	struct radeon_encoder *other_radeon_encoder;
2843e4b9982SAlex Deucher 
2853e4b9982SAlex Deucher 	if (radeon_encoder->is_ext_encoder)
2863e4b9982SAlex Deucher 		return NULL;
2873e4b9982SAlex Deucher 
2883e4b9982SAlex Deucher 	list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2893e4b9982SAlex Deucher 		if (other_encoder == encoder)
2903e4b9982SAlex Deucher 			continue;
2913e4b9982SAlex Deucher 		other_radeon_encoder = to_radeon_encoder(other_encoder);
2923e4b9982SAlex Deucher 		if (other_radeon_encoder->is_ext_encoder &&
2933e4b9982SAlex Deucher 		    (radeon_encoder->devices & other_radeon_encoder->devices))
2943e4b9982SAlex Deucher 			return other_encoder;
2953e4b9982SAlex Deucher 	}
2963e4b9982SAlex Deucher 	return NULL;
2973e4b9982SAlex Deucher }
2983e4b9982SAlex Deucher 
2991d33e1fcSAlex Deucher u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder)
300d7fa8bb3SAlex Deucher {
3013f03ced8SAlex Deucher 	struct drm_encoder *other_encoder = radeon_get_external_encoder(encoder);
302d7fa8bb3SAlex Deucher 
303d7fa8bb3SAlex Deucher 	if (other_encoder) {
304d7fa8bb3SAlex Deucher 		struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder);
305d7fa8bb3SAlex Deucher 
306d7fa8bb3SAlex Deucher 		switch (radeon_encoder->encoder_id) {
307d7fa8bb3SAlex Deucher 		case ENCODER_OBJECT_ID_TRAVIS:
308d7fa8bb3SAlex Deucher 		case ENCODER_OBJECT_ID_NUTMEG:
309dc87cd5cSAlex Deucher 			return radeon_encoder->encoder_id;
310d7fa8bb3SAlex Deucher 		default:
311dc87cd5cSAlex Deucher 			return ENCODER_OBJECT_ID_NONE;
312d7fa8bb3SAlex Deucher 		}
313d7fa8bb3SAlex Deucher 	}
314dc87cd5cSAlex Deucher 	return ENCODER_OBJECT_ID_NONE;
315d7fa8bb3SAlex Deucher }
316d7fa8bb3SAlex Deucher 
3173515387bSAlex Deucher void radeon_panel_mode_fixup(struct drm_encoder *encoder,
3183515387bSAlex Deucher 			     struct drm_display_mode *adjusted_mode)
3193515387bSAlex Deucher {
3203515387bSAlex Deucher 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3213515387bSAlex Deucher 	struct drm_device *dev = encoder->dev;
3223515387bSAlex Deucher 	struct radeon_device *rdev = dev->dev_private;
3233515387bSAlex Deucher 	struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
3243515387bSAlex Deucher 	unsigned hblank = native_mode->htotal - native_mode->hdisplay;
3253515387bSAlex Deucher 	unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
3263515387bSAlex Deucher 	unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
3273515387bSAlex Deucher 	unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
3283515387bSAlex Deucher 	unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
3293515387bSAlex Deucher 	unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
3303515387bSAlex Deucher 
3313515387bSAlex Deucher 	adjusted_mode->clock = native_mode->clock;
3323515387bSAlex Deucher 	adjusted_mode->flags = native_mode->flags;
3333515387bSAlex Deucher 
3343515387bSAlex Deucher 	if (ASIC_IS_AVIVO(rdev)) {
3353515387bSAlex Deucher 		adjusted_mode->hdisplay = native_mode->hdisplay;
3363515387bSAlex Deucher 		adjusted_mode->vdisplay = native_mode->vdisplay;
3373515387bSAlex Deucher 	}
3383515387bSAlex Deucher 
3393515387bSAlex Deucher 	adjusted_mode->htotal = native_mode->hdisplay + hblank;
3403515387bSAlex Deucher 	adjusted_mode->hsync_start = native_mode->hdisplay + hover;
3413515387bSAlex Deucher 	adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
3423515387bSAlex Deucher 
3433515387bSAlex Deucher 	adjusted_mode->vtotal = native_mode->vdisplay + vblank;
3443515387bSAlex Deucher 	adjusted_mode->vsync_start = native_mode->vdisplay + vover;
3453515387bSAlex Deucher 	adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
3463515387bSAlex Deucher 
3473515387bSAlex Deucher 	drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
3483515387bSAlex Deucher 
3493515387bSAlex Deucher 	if (ASIC_IS_AVIVO(rdev)) {
3503515387bSAlex Deucher 		adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
3513515387bSAlex Deucher 		adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
3523515387bSAlex Deucher 	}
3533515387bSAlex Deucher 
3543515387bSAlex Deucher 	adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
3553515387bSAlex Deucher 	adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
3563515387bSAlex Deucher 	adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
3573515387bSAlex Deucher 
3583515387bSAlex Deucher 	adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
3593515387bSAlex Deucher 	adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
3603515387bSAlex Deucher 	adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
3613515387bSAlex Deucher 
3623515387bSAlex Deucher }
3633515387bSAlex Deucher 
3649aa59993SAlex Deucher bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
3659aa59993SAlex Deucher 				    u32 pixel_clock)
3669aa59993SAlex Deucher {
3671b2681baSAlex Deucher 	struct drm_device *dev = encoder->dev;
3681b2681baSAlex Deucher 	struct radeon_device *rdev = dev->dev_private;
3699aa59993SAlex Deucher 	struct drm_connector *connector;
3709aa59993SAlex Deucher 	struct radeon_connector *radeon_connector;
3719aa59993SAlex Deucher 	struct radeon_connector_atom_dig *dig_connector;
3729aa59993SAlex Deucher 
3739aa59993SAlex Deucher 	connector = radeon_get_connector_for_encoder(encoder);
3749aa59993SAlex Deucher 	/* if we don't have an active device yet, just use one of
3759aa59993SAlex Deucher 	 * the connectors tied to the encoder.
3769aa59993SAlex Deucher 	 */
3779aa59993SAlex Deucher 	if (!connector)
3789aa59993SAlex Deucher 		connector = radeon_get_connector_for_encoder_init(encoder);
3799aa59993SAlex Deucher 	radeon_connector = to_radeon_connector(connector);
3809aa59993SAlex Deucher 
3819aa59993SAlex Deucher 	switch (connector->connector_type) {
3829aa59993SAlex Deucher 	case DRM_MODE_CONNECTOR_DVII:
3839aa59993SAlex Deucher 	case DRM_MODE_CONNECTOR_HDMIB:
3849aa59993SAlex Deucher 		if (radeon_connector->use_digital) {
3859aa59993SAlex Deucher 			/* HDMI 1.3 supports up to 340 Mhz over single link */
386377bd8a9SAlex Deucher 			if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
3879aa59993SAlex Deucher 				if (pixel_clock > 340000)
3889aa59993SAlex Deucher 					return true;
3899aa59993SAlex Deucher 				else
3909aa59993SAlex Deucher 					return false;
3919aa59993SAlex Deucher 			} else {
3929aa59993SAlex Deucher 				if (pixel_clock > 165000)
3939aa59993SAlex Deucher 					return true;
3949aa59993SAlex Deucher 				else
3959aa59993SAlex Deucher 					return false;
3969aa59993SAlex Deucher 			}
3979aa59993SAlex Deucher 		} else
3989aa59993SAlex Deucher 			return false;
3999aa59993SAlex Deucher 	case DRM_MODE_CONNECTOR_DVID:
4009aa59993SAlex Deucher 	case DRM_MODE_CONNECTOR_HDMIA:
4019aa59993SAlex Deucher 	case DRM_MODE_CONNECTOR_DisplayPort:
4029843ead0SDave Airlie 		if (radeon_connector->is_mst_connector)
4039843ead0SDave Airlie 			return false;
4049843ead0SDave Airlie 
4059aa59993SAlex Deucher 		dig_connector = radeon_connector->con_priv;
4069aa59993SAlex Deucher 		if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
4079aa59993SAlex Deucher 		    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
4089aa59993SAlex Deucher 			return false;
4099aa59993SAlex Deucher 		else {
4109aa59993SAlex Deucher 			/* HDMI 1.3 supports up to 340 Mhz over single link */
411377bd8a9SAlex Deucher 			if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
4129aa59993SAlex Deucher 				if (pixel_clock > 340000)
4139aa59993SAlex Deucher 					return true;
4149aa59993SAlex Deucher 				else
4159aa59993SAlex Deucher 					return false;
4169aa59993SAlex Deucher 			} else {
4179aa59993SAlex Deucher 				if (pixel_clock > 165000)
4189aa59993SAlex Deucher 					return true;
4199aa59993SAlex Deucher 				else
4209aa59993SAlex Deucher 					return false;
4219aa59993SAlex Deucher 			}
4229aa59993SAlex Deucher 		}
4239aa59993SAlex Deucher 	default:
4249aa59993SAlex Deucher 		return false;
4259aa59993SAlex Deucher 	}
4269aa59993SAlex Deucher }
4279aa59993SAlex Deucher 
428d740a933SAlex Deucher bool radeon_encoder_is_digital(struct drm_encoder *encoder)
429d740a933SAlex Deucher {
430d740a933SAlex Deucher 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
431d740a933SAlex Deucher 	switch (radeon_encoder->encoder_id) {
432d740a933SAlex Deucher 	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
433d740a933SAlex Deucher 	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
434d740a933SAlex Deucher 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
435d740a933SAlex Deucher 	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
436d740a933SAlex Deucher 	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
437d740a933SAlex Deucher 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
438d740a933SAlex Deucher 	case ENCODER_OBJECT_ID_INTERNAL_DDI:
439d740a933SAlex Deucher 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
440d740a933SAlex Deucher 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
441d740a933SAlex Deucher 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
442d740a933SAlex Deucher 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
443d740a933SAlex Deucher 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
444d740a933SAlex Deucher 		return true;
445d740a933SAlex Deucher 	default:
446d740a933SAlex Deucher 		return false;
447d740a933SAlex Deucher 	}
448d740a933SAlex Deucher }
449